JPH07114796A - Semiconductor non-volatile memory - Google Patents

Abstract

PURPOSE:To prevent misreading and to obtain a superior data holding characteristic even if dispersion of a erasing characteristic of a memory cell occurs by providing a source decoder, a source voltage supplying circuit, and a sense amplifier. CONSTITUTION:A source decoder 3 selects one of plural source lines at the time of read-out, a source voltage circuit 2 selectively applies voltage activating a memory cell transistor to a selected source line and applies voltage inactivating a transistor to a source line of non-selection. A sense amplifier 8 has a detecting level by which a current flowing between a drain and a source of a selection memory cell transistor connected to between a selected source line and a selected bit line and a current flowing between a drain and a source of a non-selection memory cell transistor connected to between a selected source line and a selected bit line can be discriminated. Thereby, misreading is prevented even if a memory cell being in a over erasing state exists on a selected bit line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor nonvolatile memory capable of electrically rewriting stored contents.

[0002]

2. Description of the Related Art As an electrically erasable semiconductor nonvolatile memory, an EEPROM (Electrically) is used.
An erasable program ROM) is generally known, and in this EEPROM, a memory cell has a stack type structure having a floating gate electrode and a control gate electrode.

FIG. 5 is a configuration diagram showing a configuration of a conventional EEPROM disclosed in Japanese Patent Laid-Open No. 1777561/1990, in which memory cells are arranged in rows and columns, and a periphery for writing and reading is arranged around the memory cells. The circuit is arranged.

FIG. 6 is a diagram showing the circuit operation of FIG.
4 shows the relationship between the cell applied voltage and the operation mode of the EEPROM. As shown in FIG. 5, memory cell transistors 71-1-1 to 71-3-3 are arranged in a matrix, and the EEPROM transistor gates forming this memory cell are word lines 72-1 to 72-1 in each same row. 72-3
It is connected to the.

In addition, the memory cells belonging to the same row are commonly connected to the source lines 73-1 and 73-2. Further, the drains of the memory cells belonging to the same column are commonly connected to the bit lines 74-1 to 74-3. Word line 72-1
72-3 are connected to the row decoder 75 via the switching circuit 76. The switching circuit 76 responds to the row selection output operation mode designating signal of the row decoder 75 in response to the word lines 72-1 ...
72-3 and source lines 73-1 and 73-2 are switched and selected. The bit lines 74-1 to 74-3 are connected to the column selection gate 79, and perform column selection according to the column selection output of the column decoder 78, and the voltage of the bit line according to the operation mode designating signal. The operation of switching and selecting is performed.

A sense amplifier 81 is connected to the column decoder 78 and performs an operation of reading the contents of the selected memory cell. When selectively reading the memory cell 71-1-2, the source line potential Vs of the source line 73-1 is set to the ground potential, and the selected word line 72-1 is driven.
The drain line potential Vg is set to 5V (power supply voltage Vcc), the potential of the unselected word line is set to the ground potential, and the bit line potential Vd of the selected bit line 74-2 is set to 3V (Vd).
And the potential of the non-selected bit line is set to the ground potential. The potential Vd is a voltage generated internally from the external supply voltage Vex.

By thus applying the read voltage to the selected memory cell, the data content ("0", "1") of the selected memory cell is read to the bit line, sensed and amplified by the sense amplifier 81, and output. To be done. When over-erasing occurs in erasing the above-mentioned EEPROM cell, the threshold voltage Vth of the erased cell transistor becomes negative,
At the time of subsequent reading, there is a possibility that an erroneous reading occurs due to the erroneous selection. That is, when excessive positive charges are accumulated in the floating gate electrode due to overerasure, the channel under the floating gate electrode is inverted to become a depletion type.

Therefore, in order to prevent the erroneous selection state at the time of reading, the electron extraction condition at the time of erasing is optimized so that the threshold voltage Vth of the cell transistor after erasing is optimized.
To ensure that When the operation mode is other than read, each potential is set to Vg, Vd, and Vs of 0 V, 20 V, and open potential when erase “1”, and 12.5 V, 10 V, and 0 V when write “0”.
Then, it is set to 0V, 0V, 0V at the time of writing "1".

FIG. 7 is a block diagram of another conventional non-volatile memory, and FIG. 8 is a diagram showing the circuit operation of FIG.
It corresponds to FIG. The configuration is almost the same as the configuration of the conventional example shown in FIG. 5, but the voltage setting for the cell transistor in the read mode is different from that of the conventional example described above.

In the circuit of FIG. 7, the source line potential Vs during reading is set to 2V. Therefore, in order to supply the source line potential, for example, it is necessary to step down the power supply voltage Vcc by a resistance dividing circuit or the like to generate a predetermined positive voltage (for example, 2V), which is provided as the voltage supply circuit 1. There is. The voltage supply circuit 1 is connected to the switching circuit 76 and the column selection gate 79, respectively. In the case of this conventional example, since the voltage supply of 3V required in the first conventional example is not necessary, this supply circuit is omitted. However,
The switching circuit 76 and the column selection gate 79 are different from the first prior art example in that the output voltage of the voltage supply circuit 1 is used in the read mode. Since other configurations are the same as those of the first conventional example shown in FIG. 5, the same reference numerals are given to the same portions, and the description thereof will be omitted.

Also in the circuit of FIG. 7, when the operation modes are erase "1", write "0", and write "1", the set potentials of Vg, Vd and Vs are the first conventional example shown in FIG. Since it is the same as the case 1, only the read operation mode will be described. The read operation mode in the circuit of FIG. 7 will be described focusing on the memory cell transistor 71-2-2 connected to one set of the word line 72-2, the source line 73-1 and the bit line 74-2.

The word line 72-2 selected at the time of reading is set to, for example, 5 V (Vcc power supply voltage), the unselected word line is set to the ground potential, and the potential of the source line 73-1 is set to 2.
Set to V. Further selected bit line 74-2
Is set to 5V (Vcc power supply voltage), and the potential of the non-selected bit line is set to 2V.

When the read voltage is applied to the selected memory cell under such an applied voltage condition, the data content ("0" or "1") of the selected memory cell is read to the bit line and sensed by the sense amplifier 81.・ Amplified and output. In this conventional example, a positive voltage (2 V in this conventional example) is applied to the one of the source lines or bit lines to which a low bias voltage is normally applied (source line in this conventional example) for all memory cells during reading. Is set, and a drain voltage (5 V) larger than the drain voltage (3 V) of the first conventional example is applied to the memory cell of the bit line selected by this positive voltage to obtain the required drain-source voltage. To ensure.

Therefore, the same effect as when the back gate bias is applied to all the cells occurs. Therefore, even for a memory transistor cell in which the threshold voltage Vth after erase becomes negative due to over-erasure, the threshold voltage Vth
Is read out, it is relieved by shifting to a substantially positive value.

[0015]

In the case of the first conventional example, the erroneous selection due to overerasure at the time of reading is prevented only by optimizing the electron extraction condition at the time of erasing. However, it is necessary to accurately control the shape of the floating gate electrode, and such control is extremely difficult.If variations occur in the erase characteristics of each memory cell, erroneous selection cannot be prevented and erroneous reading cannot be performed. There is a problem of getting up.

In the case of the second conventional example, the back gate bias effect is used to prevent erroneous selection due to overerasure during reading, so that the threshold of the overerased memory cell is apparently positive. This is done by correcting the value. Therefore, since a high voltage corresponding to the power supply voltage is always biased to the drain of the memory cell, a bias in the soft erase state is applied, which deteriorates the data retention characteristic of the normally written memory cell. ,
Alternatively, in the worst case, there is a problem that data is destroyed.

The present invention has been made in order to solve the above-mentioned problems, and does not cause erroneous reading even if the erase characteristics of the memory cells vary, and has excellent data retention characteristics of the memory cells. Another object of the present invention is to provide a semiconductor nonvolatile memory.

[0018]

According to the present invention, memory cell transistors having floating gate electrodes and control gate electrodes are arranged in a matrix, and the drains of the memory cell transistors belonging to the same column are commonly connected to a bit line. Then, each control gate electrode of the memory cell transistors belonging to the same row is commonly connected to a word line, and each source of the memory cell transistors belonging to the same row is commonly connected to a source line to form a cell array. In a semiconductor non-volatile memory that reads stored information of a selected memory cell transistor through a sense amplifier, a source decoder that selects one of a plurality of source lines at the time of reading and a selected source line are selected. The voltage that activates the memory cell transistor is applied to the unselected source line. A source voltage supply circuit for selectively applying a voltage that inactivates the transistor, and as a sense amplifier between the drain and source of the selected memory cell transistor connected between the selected source line and the selected bit line. And a current flowing between the drain and the source of a non-selected memory cell transistor connected between the selected source line and the selected bit line.

[0019]

According to the present invention, even if all the memory cells other than the selected memory cell are in the over-erased state, a potential is supplied so that all the memory cells connected to the non-selected source line are cut off. . That is, regardless of the memory capacity, the overerased memory cells that are affected when reading the selected memory cell are limited to only one non-selected cell connected to the selected source line.
By using, as the sense amplifier, a sense amplifier having a detection level capable of distinguishing the current flowing between the drain and source of the selected memory cell transistor and the current flowing between the drain and source of the non-selected memory cell transistor, The influence of the over-erased memory cell is ignored. Therefore, even for a memory cell transistor whose threshold voltage after erasure becomes negative due to overerasure,
This can be substantially ignored when reading the negative threshold voltage, and erroneous reading at the time of reading can be prevented.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a semiconductor nonvolatile memory according to an embodiment of the present invention. Non-volatile memory is EEPROM, FLASH MEMORY
Etc. are possible. Further, FIG. 3 is a diagram showing the relationship between the operation mode and the cell applied voltage in each operation mode in the circuit of FIG.

The arrangement of the memory cell array and the connection with the peripheral circuits employ a circuit configuration similar to that of the conventional example shown in FIGS. 5 and 7, but the configuration of the source line and the reading when the memory cell array is formed. The voltage setting for the cell transistor at this time is different from that of the conventional example as shown in FIG. 3, and a source decoder 3 and a source voltage supply circuit 2 are added correspondingly. Moreover, the operating conditions of the sense amplifier 8 are different from those of the conventional circuit.

The source decoder 3 has source lines 73-1 and 7-3.
3-2, and one of the source lines is selected.
The ground potential is supplied from the source voltage supply circuit 2 to the selected source line, and the potential of 2V is supplied from the source voltage supply circuit 2 to the unselected source line. In addition, the source line 73- selected by the source decoder 3
1 and the selected bit line 74-2 are configured so that memory cell transistors 71-1-2 and 71-2-2, whose sources and drains are respectively connected, exist as a pair. . One of the pair of memory cell transistors is selected and the other is unselected.

Next, regarding the read operation mode in the circuit of FIG. 1, pay attention to the memory cell transistor 71-2-2 connected to the set of the word line 72-2, the source line 73-1 and the bit line 74-2. And explain.

At the time of reading, the selected word line 72-
The potential of 2 is set to 5 V (Vcc power supply voltage), the unselected word line is set to the ground potential, the selected source line 73-1 is set to the ground potential, and the unselected source line 73-2 is set.
Is set to 2V. Further, the bit line 74 connected to the drain of the memory cell transistor 71-2-2
-2 to 2V (the same potential as the unselected source line 73-2),
The non-selected bit lines 74-1 and 74-3 are set to the open state.

On the other hand, the sense amplifier 8 which is connected to the bit line 74-2 through the column selection gate 79 and detects the data content of the memory cell has a non-selected word line 72-1 and a non-selected word line 72-1 as shown in FIG. Unselected memory cells 71 connected to a set of selected bit line 74-2 and selected source line 73-1
The current (30 μA) that flows when -1-2 is in an over-erased state (for example, Vth = -2 V) and the current that flows when a normally written memory cell is selected (315 μA).
The detection level is set between A) and A). (In the present embodiment, the following description will be made assuming that it is set to 100 μA, for example.) Here, the selected memory cell is in the erased state (depletion state), and the unselected memory connected to the selected source line is in the over-erased state (for example, -2V), the current flowing through the selected bit line is about 345 μA, which can be sufficiently detected by the sense amplifier 8. On the other hand, when the selected memory cell is in the written state and the unselected memory cell connected to the selected source line is in the over-erased state as described above, the current flowing through the selected bit line is about 30 μA, and the sense amplifier 8
There is a sufficient margin for the detection level of 100 μA, and it becomes possible to detect the writing state.

By applying a read voltage to each of the selected memory cell and the non-selected memory cell using such a sense amplifier 8, the data of the selected memory cell is read to the bit line 74-2, and the column selection gate 79. Is sensed / amplified by the sense amplifier 8 and output. It should be noted that erasing / writing is performed in the same manner as in a normal nonvolatile memory. For example, when performing batch erasing, all word lines are set to the ground potential, all source lines are set to 20V (erasing voltage Vpp), and all bit lines are set to an open state. As a result, a high voltage is applied between the source region of the memory cell and the control gate, and the electrons in the floating gate electrode are discharged to the source region by utilizing the tunnel current, and the erased state is set.

The detection level of the sense amplifier 8 can be set by using various circuits. FIG. 2 is a block diagram showing another embodiment of the present invention including a detection level setting circuit. The reference column line 74-R is configured to be connected to the sense amplifier 8 via the reference column selection gate 83. This reference column line 7
4-R is selected by selecting the reference column selection gate 83 by a control signal (not shown), and the voltage (for example, 2 V) applied to this is applied to a predetermined circuit in the sense amplifier 8. Thereby, the predetermined detection level is set.

The reference column selection gate 83
Reference memory cells 71-1-R to 71-3-
R is a memory cell transistor 71-1-1 to 71-3-
3 are connected in the same relationship as the tangential state. In setting the detection level, in addition to the method of selecting the reference column line 74-R as described above, there is also a method of selecting the reference memory cells 71-1-R to 71-3-R.

For example, reference memory cells 71-1 -R and 71-2 connected to the source line 73-1 by a common source.
-R and is selected, and reference word line 72-2
-R is activated to activate the reference memory cell 71-2-R
Select. At this time, the reference memory cell 71-2
If −R is intentionally set in advance to be in the over-erased state, the detection level can be set according to the over-erased state.

In the above embodiment, the number of reference column lines is only one, but it is also possible to use a plurality of reference column lines. In that case, the reference column select gate 83 The configuration also needs to be changed. Further, the number of reference memory cells is not limited to the embodiment shown in FIG. 2, and it is possible to select any number.

[0031]

As described in detail based on the above embodiments, in the present invention, a predetermined voltage is applied to the source decoder for selecting the source line and the selected source line and the non-selected source line, respectively. The memory cell in the over-erased state is selected because it has a source voltage supply circuit for supplying and a sense amplifier having a detection level capable of distinguishing the current flowing between the drain and source of the selected memory transistor and the non-selected memory transistor. Even if it exists on the bit line, there is an advantage that erroneous reading does not occur.

Further, since there is no risk of erroneous reading even if there is a memory cell in the over-erased state, it is not necessary to accurately align the threshold voltages of the memory cells during the erase operation, and complicated erase and confirmation are required. Control can be omitted and the erase time can be shortened.

Furthermore, since there is no risk of erroneous reading even if there are over-erased memory cells, it is possible to provide a semiconductor non-volatile memory that can be realized even if there are variations in the gate oxide film of the memory cells. .

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor nonvolatile memory according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a semiconductor nonvolatile memory according to another embodiment of the present invention.

FIG. 3 is a diagram showing a circuit operation of FIG.

FIG. 4 is a diagram illustrating a detection operation of the circuit of FIG.

FIG. 5 is a configuration diagram of a conventional semiconductor nonvolatile memory

6 is a diagram showing the circuit operation of FIG.

FIG. 7 is a configuration diagram of another conventional semiconductor nonvolatile memory.

8 is a diagram showing the circuit operation of FIG.

[Explanation of symbols]

1 Voltage Supply Circuit 2 Source Voltage Supply Circuit 3 Source Decoder 8 Sense Amplifier 71-1-1 to 71-3-3 Memory Cell Transistor 72-1 to 72-3 Word Line 73-1, 73-2 Source Line 74-1 To 74-3 bit line 71-1-R to 71-3-R reference memory cell 72-1-R to 72-3-R reference word line 74-R reference column line 83 reference column select gate

Claims (8)

[Claims] 1. The memory cell transistors having floating gate electrodes and control gate electrodes are arranged in rows and columns, the drains of the memory cell transistors belonging to the same column are commonly connected to a bit line, and the drains belong to the same row. Each control gate electrode of the memory cell transistors is commonly connected to a word line, and each source of the memory cell transistors belonging to the same row is commonly connected to a source line to form a cell array, and a selected memory cell in this cell array is formed. In a semiconductor non-volatile memory that reads information stored in a transistor through a sense amplifier, a source decoder that selects one of the plurality of source lines at the time of reading, and a selected memory cell transistor for the selected source line The voltage that activates the A source voltage supply circuit for selectively applying a voltage that inactivates the voltage between the drain and source of the selected memory cell transistor connected between the selected source line and the selected bit line as the sense amplifier. And a current flowing between the drain and the source of the non-selected memory cell transistor connected between the selected source line and the selected bit line. Semiconductor non-volatile memory. 2. The memory cell transistor having a source and a drain connected between the source line selected by the source decoder and the selected bit line is present as a pair. Item 2. The semiconductor nonvolatile memory according to item 1. 3. The semiconductor nonvolatile memory according to claim 1, wherein a detection level of the sense amplifier is set by using a reference memory cell. 4. The semiconductor nonvolatile memory according to claim 3, wherein the reference memory cell is a memory cell intentionally set in an over-erased state. 5. The semiconductor non-volatile memory according to claim 3, wherein a plurality of memory cells are used as the reference memory cells. 6. The semiconductor nonvolatile memory according to claim 1, wherein a detection level of the sense amplifier is set by using a reference column line. 7. The semiconductor non-volatile memory according to claim 6, wherein the memory cell group connected to the reference column line includes a memory cell intentionally over-erased. 8. The semiconductor nonvolatile memory according to claim 6, wherein the reference column line is configured by using a plurality of reference column lines.