KR100797301B1 - Ion implant method to adjust threshold voltage on mosfet by transition metal doping - Google Patents

Ion implant method to adjust threshold voltage on mosfet by transition metal doping Download PDF

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KR100797301B1
KR100797301B1 KR1020060125434A KR20060125434A KR100797301B1 KR 100797301 B1 KR100797301 B1 KR 100797301B1 KR 1020060125434 A KR1020060125434 A KR 1020060125434A KR 20060125434 A KR20060125434 A KR 20060125434A KR 100797301 B1 KR100797301 B1 KR 100797301B1
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transition metal
well
ion implantation
threshold voltage
mosfet
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KR1020060125434A
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Korean (ko)
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박찬혁
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising transition metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]

Abstract

An ion implantation method for a threshold voltage adjustment of a MOSFET(Metal Oxide Semiconductor Filed Effect Transistor) gate through a transition metal doping is provided to control a pinch-off being saturated according to a drain voltage and to generate a channel by using polarization. A p-well(210), an n-well(220), and an isolation layer(250) are formed on a semiconductor substrate and then an ion implantation process for adjusting a gate threshold voltage is performed. The ion implantation process is simultaneously performed on the p-well and the n-well by using a transition metal. The transition metal is one selected from Mn, Ni, and Co. The ion implantation process is performed at 1.3~7.0E15 atm/cm^2 and 10 KeV~50 Kev. Therefore, a pinch-off being saturated according to a drain voltage is controlled and a channel is generated by using polarization.

Description

전이금속 도핑에 의한 ＭＯＳＦＥＴ 게이트 문턱전압 조정을 위한 이온주입방법 {Ion implant method to adjust threshold voltage on MOSFET by transition metal doping}Ion implant method to adjust threshold voltage on MOSFET by transition metal doping}

도 1a 내지 도 1b는 종래의 문턱전압 조정을 위한 이온주입 과정을 도시한 도면,1A to 1B illustrate an ion implantation process for adjusting a threshold voltage according to the related art;

도 2a 내지 도 2b는 본 발명에 의한 전이금속 도핑에 의한 MOSFET 게이트 문턱전압 조정을 위한 이온 주입 과정을 차례대로 도시한 도면,2A to 2B are views sequentially illustrating an ion implantation process for adjusting the MOSFET gate threshold voltage by transition metal doping according to the present invention;

도 3은 본 발명에 의한 MOSFET 채널 형성 모습이다.3 shows a MOSFET channel formation according to the present invention.

* 도면의 주요 부호에 대한 설명* Description of the main symbols in the drawing

200 : 반도체 기판 210 : p웰200: semiconductor substrate 210: p well

220 : n웰 260 : 전이금속220: n well 260: transition metal

330 : 공핍층330 depletion layer

본 발명은 트랜지스터 제조 방법에 관한 것으로서, 상세하게는 n웰과 p웰에 동시에 전이금속을 도핑시켜서 MOSFET의 게이트 문턱전압을 조정할 수 있는 전이금속 도핑에 의한 MOSFET 게이트 문턱전압 조정을 위한 이온주입방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a transistor, and more particularly, to an ion implantation method for controlling a MOSFET gate threshold voltage by transition metal doping, in which n and p wells are simultaneously doped with a transition metal to adjust a gate threshold voltage of the MOSFET. It is about.

MOSFET은 일반적으로 소스, 드레인, 게이트로 구성된다. 게이트에 인가된 전압에 의해서 트리거(triggered)될 때 게이트 아래의 채널영역이 전도성으로 될때까지는 소스와 드레인 사이에 전류가 흐르지 않는다. 문턱전압(Vth)은 증가형 모드 트랜지스터를 턴온(turn on)시키는 소스와 드레인 사이에 전도성의 채널을 형성하기 위해서 요구되는 전압의 크기이다. MOSFETs typically consist of a source, drain, and gate. When triggered by the voltage applied to the gate, no current flows between the source and drain until the channel region under the gate becomes conductive. The threshold voltage V th is the magnitude of the voltage required to form a conductive channel between the source and the drain that turns on the incremental mode transistor.

최근에는 반도체 소자가 고집적화, 고밀도화됨에 따라서 트랜지스터의 채널의 길이도 짧아지게 되고, 채널길이의 감소는 숏 채널 효과(short channel effect)가 발생하여 문턱전압이 감소하게 되었다. 그러나 이러한 문턱 전압의 감소는 누설전류 증가등의 문제를 유발한다.In recent years, as semiconductor devices become more integrated and denser, shorter channel lengths of transistors become shorter, and shorter channel lengths result in short channel effects resulting in lower threshold voltages. However, such a decrease in threshold voltage causes problems such as an increase in leakage current.

따라서 이러한 문제점을 해결하기 위하여 문턱전압을 조절해야 하는데, 문턱전압은 채널영역에서 도펀트 농도에 매우 민감하다. 최적 소자 성능을 위해 도펀트는 요구된 도펀트 농도의 채널 영역을 조절하기 위해 실리콘층 아래에 주입된다. 이것은 MOS 게이트 문턱전압 조정을 위한 이온주입(Vth Implant)이라고 불려지고, 소자의 성능에 대한 기본적인 중요한 파라미터이다. nMOS(n-채널)의 경우에는 Boron와 같은 p형 도펀트를 주입하고, pMOS(p-채널)의 경우에는 Phosphorous와 같은 n형 도펀트를 주입한다.Therefore, in order to solve this problem, the threshold voltage must be adjusted. The threshold voltage is very sensitive to the dopant concentration in the channel region. For optimal device performance, dopants are implanted under the silicon layer to adjust the channel region of the required dopant concentration. This is called V th Implant for MOS gate threshold adjustment and is a fundamental important parameter for the device's performance. In the case of nMOS (n-channel), a p-type dopant such as Boron is implanted, and in the case of pMOS (p-channel), an n-type dopant such as Phosphorous is implanted.

도 1a 내지 도 1c는 종래의 문턱전압 조정을 위한 이온주입 과정을 도시한 것이다. 도 1a와 같이 반도체 기판(100)이 있으며, 이는 STI(150)에 의해 분리되어서 왼쪽은 nMOS를 형성하기 위하여 p웰(110)이 형성되어 있으며, 오른쪽에는 pMOS를 형성하기 위하여 n웰(120)이 형성되어 있다. 다음으로 도 1b와 같이 MOS 게이트 문턱전압 조정을 위하여 p웰(110)에는 Boron(161)를 주입하고, 도 1c와 같이 n웰(120)에는 Phosphorous(171)를 주입한다. 1A to 1C illustrate a conventional ion implantation process for adjusting a threshold voltage. As shown in FIG. 1A, there is a semiconductor substrate 100, which is separated by the STI 150 so that the p well 110 is formed on the left to form nMOS, and the n well 120 is formed on the right to form pMOS. Is formed. Next, Boron 161 is injected into the p well 110 to adjust the MOS gate threshold voltage as shown in FIG. 1B, and Phosphorous 171 is injected into the n well 120 as shown in FIG. 1C.

즉, 먼저 p웰(110)에 Boron(161)을 주입하기 위해서 사진공정을 통하여 포토레지스트(160)로 p웰(110)의 상부만 개방한 후, Boron(161)을 이온주입한다. 마찬가지로 n웰(120)에 Phosphorous(171)를 주입하기 위하여 사진 공정을 통하여 포토레지스트(170)로 n웰(120)의 상부만 개방한 후, Phosphorous(171)를 이온 주입한다. That is, first, only the upper portion of the p well 110 is opened to the photoresist 160 through the photolithography process to inject the boron 161 into the p well 110, and then the ion is implanted into the boron 161. Similarly, in order to inject the phosphorous 171 into the n well 120, only the top of the n well 120 is opened to the photoresist 170 through a photolithography process, and then the phosphorous 171 is ion implanted.

결국 MOS 게이트 문턱전압 조정을 위한 이온주입과정은 두번의 사진공정과 두번의 이온주입과정을 복잡한 절차를 거쳐야 하며, 아울러 이러한 공정을 거치면서 이온주입의 깊이를 정확하게 조절하기 어려우며, 또한 후속공정에서의 열처리로 인하여 확산이 되는 등의 많은 문제점이 있었다. As a result, the ion implantation process for adjusting the MOS gate threshold voltage requires a complicated process of two photographic processes and two ion implantation processes. There are many problems such as diffusion due to heat treatment.

본 발명은 상기된 문제점을 해결하기 위하여 안출된 것으로서, nMOS와 pMOS에서 게이트 문턱전압 조정을 위한 이온주입 공정을 단일화하며, 트랜지스터의 문턱전압의 조절이 용이하며, 반도체 소자의 크기가 작아짐에 따른 숏 채널 효과(short channel effect)의 영향을 최소화할 수 있는 전이금속 도핑에 의한 MOSFET 게이트 문턱전압 조정을 위한 이온주입방법을 제공함에 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and unifies the ion implantation process for adjusting the gate threshold voltage in the nMOS and pMOS, easily adjusts the threshold voltage of the transistor, and shortens the size of the semiconductor device due to its smaller size. An object of the present invention is to provide an ion implantation method for controlling the MOSFET gate threshold voltage by transition metal doping that can minimize the effect of a short channel effect.

본 발명에 의한 전이금속 도핑에 의한 MOSFET 게이트 문턱전압 조정을 위한 이온주입방법은 반도체 기판에 p웰, n웰과 소자분리막을 형성한 후에 게이트 문턱전압을 조정하기 위한 이온주입공정을 진행함에 있어서, 상기 이온주입공정은 상기 p웰과 n웰에서 전이금속을 이용하여 동시에 실시되는 것을 특징으로 한다.In the ion implantation method for controlling the MOSFET gate threshold voltage by transition metal doping according to the present invention, after forming the p well, n well and the device isolation film in the semiconductor substrate, in the ion implantation process for adjusting the gate threshold voltage, The ion implantation process is carried out simultaneously using a transition metal in the p well and n well.

본 발명의 다른 바람직한 특징에 의하면, 상기 전이금속은 Mn, Ni, Co중에서 선택된 어느 하나인 것을 특징으로 한다. According to another preferred feature of the invention, the transition metal is characterized in that any one selected from Mn, Ni, Co.

본 발명의 다른 바람직한 특징에 의하면, 상기 전이금속의 주입은 1.3~7.0E15 개/Cm2,10KeV~ 50KeV의 낮은 에너지 조건에서 실시된다.According to another preferred feature of the invention, the transition metal is injected at low energy conditions of 1.3 to 7.0E15 pieces / Cm 2 , 10 KeV to 50 KeV.

이하 예시도면에 의거하여 본 발명의 일실시예에 대한 구성 및 작용을 상세히 설명한다. 다만, 아래의 실시예는 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 충분히 이해할 수 있도록 제공되는 것이지, 본 발명의 범위가 다음에 기술되는 실시예에 의해 한정되는 것은 아니다.Hereinafter, the configuration and operation of an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, the following examples are provided to enable those skilled in the art to fully understand the present invention, but the scope of the present invention is not limited by the embodiments described below.

도 2a 내지 도 2b는 본 발명에 의한 전이금속 도핑에 의한 MOSFET 게이트 문턱전압 조정을 위한 이온주입조정 과정을 차례대로 도시한 도면이다. 도 2a와 같이 종래의 방법과 동일하게 반도체 기판(200)위에 소자분리막(250)과 상기 소자분리막의 왼쪽에는 nMOS용 p웰(210)을 형성하고, 상기 소자분리막의 오른쪽에는 pMOS용 n웰(220)을 각각 형성한다. 다음으로 도 2b와 같이 p웰(210)과 n웰(220) 전체에 걸쳐서 전이금속(260)을 주입한다.2A to 2B are diagrams sequentially illustrating an ion implantation adjustment process for adjusting the MOSFET gate threshold voltage by transition metal doping according to the present invention. As shown in FIG. 2A, an nMOS p well 210 is formed on the semiconductor substrate 200 on the semiconductor substrate 200 and the left side of the device isolation layer, and an n well (pMOS) is formed on the right side of the device isolation layer. 220, respectively. Next, as illustrated in FIG. 2B, the transition metal 260 is injected into the entire p well 210 and the n well 220.

전이금속은 장주기형 주기율표에서 3A~7A족 및 8족 그리고 1B족에 속한 금속원소를 말한다. 전이원소의 특징은 다음과 같다. ① 대부분 중금속으로 단단하고 세며 녹는점과 끓는점이 높다. ② M 또는 그 이상의 전자껍질에 전자가 차 있는 원소들로, 최외각에 있는 전자만이 원자가전자의 역할을 하는 것이 아니라 안쪽의 전자도 원자가전자의 역할을 하므로 복잡한 원자가를 갖는다. ③ 여러 가지 착이온을 만들기 쉽고 그 대부분의 착이온은 색을 가진다. ④ 상호간 또는 다른 금속과 합금을 만든다. ⑤ 대개 수소보다 이온화 경향이 크다. ⑥ 상자성(常磁性)을 띤다.Transition metals are metal elements belonging to groups 3A-7A, 8, and 1B of the long-period periodic table. The characteristics of the transition element are as follows. ① Most of them are heavy metal, hard and strong, high melting point and high boiling point. ② M or more electron shells are filled with electrons, and the electrons in the outermost shell not only serve as valence electrons but also the inner electrons play the role of valence electrons. ③ It is easy to make various complex ions and most of them have color. ④ Make alloys with each other or with other metals. ⑤ It is usually more ionized than hydrogen. ⑥ paramagnetic (常 磁性).

그외에도 전이금속은 분극(polarization)되는 경향이 있어서, 본 발명과 같이 전이금속을 얇게 도핑한 반도체 기판위의 게이트에 전압을 가하게 되면 전이금속은 분극되어지는데, 이는 마치 채널과 같은 역할을 수행할 수 있다. 즉 다시 말해서 전이금속을 도핑하면 무질서하게 분포하다가, 전압을 가하면 전자가 한쪽으로 쏠리는 현상을 나타내는 것이다. 이것은 최근 강자성체(ferromagnetic)와 같은 곳에 사용이 되고 있으며, 게이트에 양의 전압을 가하면 게이트와 실리콘 계면에 분극이 일어나는데 전자가 게이트쪽으로 쏠리게 된다. 본 발명에서의 전이금속은 특별한 제한은 없지만, 특히 Ni, Mn, Co 중에서 선택된 어느 하나인 것이 바람직하다.In addition, the transition metal tends to be polarized. When the voltage is applied to the gate on the thinly doped semiconductor substrate as in the present invention, the transition metal is polarized, which acts as a channel. Can be. In other words, the doping of the transition metal causes disordered distribution, and when voltage is applied, electrons are directed to one side. It is recently used in places such as ferromagnetic, and when a positive voltage is applied to the gate, polarization occurs at the gate and silicon interface, and electrons are directed toward the gate. The transition metal in the present invention is not particularly limited, but is preferably any one selected from Ni, Mn, and Co.

상기 전이금속의 주입은 표면에 얕게 주입하려면 중간 전류(medium current)를 이용하는 주입장비에서 1.3~7.0E15 개/Cm2,10KeV~ 50KeV의 조건하에 실시한다. 상한치를 초과하면 너무 깊이 주입되어서 펀치 스루 임플란트(punch through implant)가 된 곳까지 들어가서 소자의 펀치 스루 특성을 저하시킨다. 그래서 하한치보다 낮은 에너지로 공정을 진행하면 전이금속의 질량이 다른 원소에 비해서 상대적으로 크기 때문에 일정 깊이 주입될 수가 없다. 그래서 제시한 조건과 같이 낮은 에너지 조건에서 실시된다.The injection of the transition metal is carried out under the condition of 1.3 ~ 7.0E15 pieces / Cm 2 , 10KeV ~ 50KeV in the injection equipment using a medium current (medium current) to shallowly injected to the surface. If the upper limit is exceeded, it is injected too deeply to become a punch through implant, thereby degrading the punch-through characteristics of the device. Therefore, if the process is carried out with energy lower than the lower limit, the mass of the transition metal is relatively large compared to other elements and thus cannot be injected at a certain depth. Thus, it is carried out at low energy conditions as shown.

도 3은 본 발명에 의해 전이금속이 도핑된 nMOS에서의 채널 형성 도면으로 서, 게이트(300)에 양극을 인가하면, 게이트 하부의 전이금속이 분극화되어 일정한 공핍층(330)이 생기게 되고, 이것이 채널과 같은 역할을 수행한다. 3 is a diagram illustrating a channel formation in an nMOS doped transition metal according to the present invention. When an anode is applied to the gate 300, the transition metal under the gate is polarized to form a constant depletion layer 330. It acts like a channel.

분극 현상은 게이트에 음의 전압을 가했을 경우에 양의 전하가 게이트쪽, 전자가 아래쪽으로 쏠리게 되고, 양으로 바꿨을 경우에는 반대의 특성이 나타난다. 또한 핀치오프현상은 기존에는 공핍층에 따라서 발생을 하며, 이와 같은 현상이 발생하였을 경우에는 전자의 가속이 되어서 절연파괴가 발생을 한다. 본 발명을 하였을 경우에는 공핍층으로 채널이 생성된 것이 아니라, 실리콘 표면위에 임플란트한 전이 금속에 의해 채널이 생성되었기 때문에 일정한 전압에서만 항복(breakdown) 전압이 발생한다.The polarization phenomenon causes the positive charge to be directed toward the gate and the electron to the bottom when a negative voltage is applied to the gate. In addition, the pinch-off phenomenon is conventionally generated according to the depletion layer, and when such a phenomenon occurs, the breakdown occurs due to the acceleration of electrons. In the case of the present invention, the breakdown voltage is generated only at a constant voltage because the channel is generated by the transition metal implanted on the silicon surface, rather than the channel created by the depletion layer.

즉, 본 발명과 같이 분극에 의한 채널의 장점은 콘트롤이 용이하며, 동시에 드레인에 걸리는 전압에 따라서 포화되는 핀치오프도 조절이 가능하며, 또한 소스 드레인의 공핍에 의해서 영향을 적게 받기 때문에 고품질의 MOSFET를 구연할 수 있게 된다.That is, the advantages of the channel due to polarization as in the present invention are easy to control, and at the same time, the saturation pinch-off can be adjusted according to the voltage applied to the drain, and the high quality MOSFET is less affected by the depletion of the source drain. You can talk about.

본 발명을 통하여 문턱전압의 조절이 용이하고, 분극을 통하여 채널을 형성하기 때문에 소스 드레인의 영향을 적게 받으며, 이온주입공정을 한 단계 줄일 수 있는 장점이 있다.Through the present invention, it is easy to adjust the threshold voltage, and because the channel is formed through polarization, it is less affected by the source drain and has an advantage of reducing the ion implantation process by one step.

Claims (3)

반도체 기판에 p웰, n웰과 소자분리막을 형성한 후에 게이트 문턱전압을 조정하기 위한 이온주입공정을 진행함에 있어서, 상기 이온주입공정은 상기 p웰과 n웰에서 전이금속을 이용하여 동시에 실시되는 것을 특징으로 하는 전이금속 도핑에 의한 MOSFET 게이트 문턱전압 조정을 위한 이온주입방법.In the ion implantation process for adjusting the gate threshold voltage after forming the p well, the n well and the device isolation film in the semiconductor substrate, the ion implantation process is carried out simultaneously using a transition metal in the p well and n well An ion implantation method for controlling the MOSFET gate threshold voltage by transition metal doping, characterized in that. 제1항에 있어서, 상기 전이금속은 Mn, Ni, Co 중 선택된 어느 하나인 것을 특징으로 하는 전이금속 도핑에 의한 MOSFET 게이트 문턱전압 조정을 위한 이온주입방법.The ion implantation method of claim 1, wherein the transition metal is any one selected from Mn, Ni, and Co. 제1항에 있어서, 상기 이온주입공정에서의 전이금속의 주입은 1.3~7.0E15 개/Cm2,10KeV~ 50KeV 조건에서 실시되는 것을 특징으로 하는 전이금속 도핑에 의한 MOSFET 게이트 문턱전압 조정을 위한 이온주입방법.The ion implantation method of claim 1, wherein the implantation of the transition metal in the ion implantation process is performed under conditions of 1.3 to 7.0E15 atoms / Cm 2 , 10 KeV to 50 KeV. Injection method.
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