KR100792706B1 - TFT using single crystal silicon nano-wire and method for fabricating of the same - Google Patents

Abstract

In the thin film transistor using single crystal silicon nanowires according to the present invention, a thin film transistor is formed on an insulating substrate, and channels and sources / drains of the thin film transistor are formed on the single crystal silicon nanowires.

Therefore, the thin film transistor using the single crystal silicon nanowires of the present invention has excellent driving characteristics, and can realize system large-scale integration (LSI), and the formation process is performed at low temperature, so that a low temperature process is required for a flexible display. There is an advantage that it is easy to apply.

Monocrystalline Silicon Nanowires, Thin Film Transistors, Transfer, Display

Description

Thin film transistor using single crystal silicon nanowires and its manufacturing method {TFT using single crystal silicon nano-wire and method for fabricating of the same}

1A is a cross-sectional view of a conventional bottom-gate type TFT,

1B is a cross-sectional view of a conventional top-gate type TFT,

2 is a cross-sectional view of a top-gate type TFT according to a first embodiment of the present invention;

3A to 3K are manufacturing process diagrams of the top-gate TFT according to the first embodiment of the present invention;

4 is a single crystal silicon nanowire for a TFT formed in accordance with a fifth embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

210, 325: single crystal silicon nanowire 330: substrate for display production

335: buffer layer 340: gate insulating film

345: gate electrode 350: interlayer insulating film

355 contact hole 360 source / drain electrodes

The present invention relates to a thin film transistor using a single crystal silicon nanowire, and more particularly, to a thin film transistor formed of a single crystal silicon nanowire with a channel and a source / drain.

Liquid crystal displays (LCDs) used in display devices such as televisions and graphic displays have been developed in place of the CRT (Cathod-ray tube). In particular, TFT LCDs with thin film transistors (TFTs) as switching elements in each pixel arranged in a matrix form have high-speed response characteristics and are suitable for high pixel counts. Contributes greatly to realizing this.

1A and 1B are sectional views of a conventional TFT.

1A is a cross-sectional view of a conventional bottom gate type TFT 100 manufactured. As shown in the figure, a buffer layer is formed on an insulating substrate such as glass or plastic, and the front surface of the substrate forms a metal material, and then patterned to form the gate electrode 105.

A gate insulating layer 110 is formed on the entire surface of the substrate using a single layer or a double layer of a silicon oxide film or a silicon nitride layer, and the entire surface of the substrate is deposited with an amorphous silicon layer, and then patterned to form an amorphous silicon layer pattern 115.

An insulating film is formed on the entire surface of the substrate, and then patterned to form an etch stop layer on the channel region in the amorphous silicon layer pattern.

After forming an amorphous silicon layer implanted with a high concentration impurity on the entire surface of the substrate, a pattern is formed using a photoresist pattern and the etch stop layer to form an amorphous silicon layer pattern 120 implanted with a high concentration impurity to form a source / drain region. define.

Subsequently, after the conductive metal is deposited on the entire surface of the substrate, the conductive metal is patterned using a photoresist pattern and the etch stop layer to form a source / drain electrode 125 and an insulating layer 130 is formed on the entire surface of the substrate. The bottom gate type TFT as shown in FIG. 1A may be completed by deposition.

1B is a sectional view of a top gate type TFT. As shown in the figure, a buffer layer 135 is formed on an insulating substrate such as glass or plastic to prevent the penetration of gas or moisture, and an amorphous silicon layer is formed on the buffer layer.

After crystallizing the amorphous silicon layer by a crystallization method, the semiconductor layer 140 formed of a polycrystalline silicon layer is formed by patterning, and the gate insulating layer 145 is formed of a single layer or a double layer of a silicon oxide film or a silicon nitride film.

Subsequently, a gate electrode 150 is formed of a conductor material on the substrate, and an interlayer insulating film 155 is formed using an insulating film.

Then, a predetermined region of the interlayer insulating layer and the gate insulating layer is etched to form a contact hole for opening the predetermined region of the semiconductor layer, and then a source / drain electrode 160 is formed to complete the top gate TFT as shown in FIG. 1B. Can be.

However, the conventional top gate TFT uses a variety of crystallization methods to form a semiconductor layer composed of a poly-silicon layer (Poly-Si), thereby providing an on / off speed than the bottom gate TFT using amorphous silicon. Although fast, it is difficult to apply to a transparent substrate such as glass because the manufacturing process is complicated and the process must be performed at a high temperature to form a polycrystalline silicon layer.

Conventional bottom gate type TFTs can be applied to a transparent substrate such as glass because they are processed at a lower temperature than polycrystalline silicon because they form a channel region with an amorphous silicon layer as mentioned above, but such amorphous silicon has an electron mobility ( Mobility is 0.5 ~ 1 / Vs, which is significantly lower than polycrystalline silicon (50 ~ 100 ㎠ / Vs) and monocrystalline silicon (600 ㎠ / Vs), so it is used only for switching of pixels. Since it is impossible to manufacture a driver circuit for driving, there is a problem that it is difficult to implement a system large scale integration (LSI) on the same substrate.

In addition, although a conventional TFT using amorphous silicon is a low temperature process, its process temperature must be at least 350 ° C. or more, so that it is difficult to apply on a flexible polymer substrate. That is, the conventional TFT using amorphous silicon or polysilicon cannot be applied to a flexible polymer substrate, and thus it is further required to implement a flexible display.

An object of the present invention is to provide a TFT manufacturing method and a TFT using single crystal silicon nanowires having excellent characteristics.

Another object of the present invention is to prepare a TFT in a low temperature process of room temperature or 350 ° C or lower.

Another object of the present invention is to provide a TFT formed on various transparent substrates such as glass and polymer.

Another object of the present invention is to provide a TFT manufacturing method and a TFT capable of system large scale integration (LSI).

It is another object of the present invention to provide a TFT applicable to a flexible display.

Another object of the present invention is to simplify the manufacturing process of the TFT.

In the thin film transistor using single crystal silicon nanowires according to the present invention, a thin film transistor is formed on an insulating substrate, and channels and sources / drains of the thin film transistor are formed on the single crystal silicon nanowires.

In this case, the channel is formed on at least one single crystal silicon nanowire, the substrate is preferably any one of glass, flexible polymer, plastic, quartz, quartz, silicon.

According to an embodiment of the present invention, a method of manufacturing a thin film transistor using single crystal silicon nanowires may include forming single crystal silicon nanowires, transferring the nanowires to a substrate on which a thin film transistor is to be formed, and a gate insulating film on the substrate. Forming a source / drain by forming a gate electrode on the gate insulating film, performing an ion implantation process or a diffusion process using the gate electrode as a mask, and forming an interlayer insulating film on the entire surface of the substrate. Forming a contact hole by etching the interlayer insulating layer on the source / drain, and forming a source / drain electrode by depositing a metal material in the contact hole.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor using single crystal silicon nanowires, the method comprising: forming a single crystal silicon nanowire including a source / drain, transferring the nanowires to a substrate on which a thin film transistor is to be formed; Forming a gate insulating film on the substrate, forming a gate electrode on the gate insulating film, forming an interlayer insulating film on the entire surface of the substrate, and etching the interlayer insulating film on the source / drain. Forming a contact hole and depositing a metal material in the contact hole to form a source / drain electrode.

According to another embodiment of the present invention, a method of manufacturing a thin film transistor using single crystal silicon nanowires may include forming a single crystal silicon nanowire, forming a gate electrode on a substrate on which the thin film transistor is to be formed, and forming an upper portion of the gate electrode. Forming a gate insulating film on the substrate, transferring the nanowires on the gate insulating film, forming an insulating layer on the transferred nanowires, and patterning the ion wire using the insulating layer as a mask Or forming a source / drain by performing a diffusion process and depositing and patterning a metal material on the entire surface of the substrate to form a source / drain electrode.

In another embodiment, a method of manufacturing a thin film transistor using single crystal silicon nanowires includes forming a single crystal silicon nanowire including a source / drain and forming a gate electrode on a substrate on which the thin film transistor is to be formed. Forming a gate insulating film on the gate electrode, transferring the nanowires on the gate insulating film, forming an insulating layer on the transferred nanowires, and patterning the insulating film on the front surface of the substrate; Depositing and patterning the metal material to form source / drain electrodes.

In this case, the forming of the single crystal silicon nanowires including the source / drain may be performed before the formation process of the single crystal silicon nanowires, or the first thermal oxide film or the first thermal oxide layer on the nanowires during the formation of the single crystal silicon nanowires. It can be formed through an ion implantation process or a diffusion process using a second thermal oxide film.

The transfer according to the present invention is performed at a temperature of from room temperature to 350 ° C. or lower, and it is preferable to transfer sequentially from one end of the substrate on which the thin film transistor is to be formed to the other end.

The foregoing terms or words used in this specification and claims are not to be construed as being limited to the common or dictionary meanings, and the inventors properly define the concept of terms in order to explain their invention in the best way. It should be interpreted as meaning and concept corresponding to the technical idea of the present invention based on the principle that it can.

Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

In the present invention, in forming a TFT on a substrate on which a display device is to be manufactured, a single crystal silicon nanowire formed of a source / drain and channel forming material, that is, a semiconductor material using a single crystal silicon substrate is manufactured, and then transferred or printed onto the display substrate. Formed by the method.

In this case, the process of transferring or printing the single crystal silicon nanowires to the display substrate is performed at room temperature or at a temperature of 150 ° C. or lower, and thus it is applicable to transparent substrates such as glass and plastic and substrates of various materials such as flexible polymers. However, it should be a substrate capable of metallization and insulating film formation process necessary for manufacturing TFT.

For this reason, the TFT of the present invention is easily applied to a flexible display as well as a general display.

In addition, the TFT manufacturing method using the single crystal silicon nanowire according to the present invention can be applied to any form such as a bottom gate type TFT, a top gate type TFT, and the like.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

[First Embodiment]

A first embodiment of the present invention relates to a top-gate TFT using a single crystal silicon nanowire and a method of manufacturing the same.

2 is a cross-sectional view of a single crystal silicon nanowire TFT manufactured according to a first embodiment of the present invention. As shown in the figure, the source / drain (S / D) and the channel (channel) are single crystal silicon nanowires ( It is formed on 210.

The TFT manufacturing method as described above will be described in detail with reference to FIGS. 3A to 3K.

1. Formation of Single Crystal Nanowires

The single crystal silicon nanowires in which the source / drain and the channel of the present invention are formed are manufactured using a separate single crystal substrate.

As shown in FIG. 3A, after the single crystal substrate 300 having the crystal structure of (100) is thermally oxidized to form the first thermal oxide film 305, an oxide film pattern (not shown) is formed using a photolithography process.

Thereafter, the oxide layer pattern is used as a mask to anisotropically etch the silicon substrate through a silicon dry etching process such as a DRIE process to form the column structure 310 as shown in FIG. 3B.

At this time, the etching depth of the columnar structure is preferably formed to a depth of the degree of easy transfer process of the nanowires.

Subsequently, when the column structure is re-etched using potassium hydroxide (KOH), which is an anisotropic etching solution, etching is performed in the crystal direction of the (100) substrate, whereby the nanowire structure 315 having an inverted triangular cross section is formed. Is formed.

After removing the first thermal oxide film remaining on the substrate, the silicon substrate is thermally oxidized to form the second thermal oxide film 320. The nanowire structure 315 having an inverted triangular cross section has only its central silicon remaining to form single crystal silicon nanowires 325 having a size of several tens of nanometers to several hundred nanometers. The line width of the single crystal silicon nanowire can be controlled by the conditions for forming the second thermal oxide film or the line width of the initial silicon pattern line.

Then, when the second thermal oxide film is sequentially removed by etching using isotropic dry etching or hydrofluoric acid vapor, the released nanowires 325 are manufactured.

Nanowires may be floating in the air, depending on their length, but may be squeezed down when their length is about 100 μm or more. Both ends or at least one end of the nanowires are supported by a support (not shown) so that the nanowires are not lost even when they are released.

The length of the single crystal silicon nanowires may be manufactured to a length suitable for forming the source / drain of the thin film transistor, and even longer may be used by removing unnecessary parts leaving only the necessary length through an appropriate process. It is also possible to manufacture one thin film transistor with only one nanowire, but several nanowires may be used as one thin film transistor channel as needed.

2. Transfer of Nanowires

Once the monocrystalline silicon nanowires are released, they are transferred to a substrate 330 to be fabricated as a display, as shown in FIG. 3G.

Since the single crystal silicon nanowire 325 according to the present invention has a structure such as an inverted triangular pillar, the transition of the triangular nanowires first touches the substrate during transfer, so that the transfer efficiency is high and advantageous.

The process carried out during transfer is carried out at room temperature or at a temperature of about 150 ° C.

Substrates to be made of the display include glass, quartz, flexible polymers, quartz, plastics, and the like.

In the first embodiment of the present invention, a quartz substrate is used for a substrate manufactured as a display, and a buffer layer is formed on the substrate to prevent penetration of gas or moisture.

In order to more easily attach the single crystal silicon nanowires, the single crystal silicon nanowires may be transferred after uniformly coating an adhesive on a substrate to be manufactured as a display. At this time, the used pressure-sensitive adhesive can be easily removed by performing a plasma dry etching process.

If the substrate itself to be manufactured as a display has adhesive properties, the single crystal silicon nanowires may be transferred without coating the adhesive.

In the transfer process, when using a large-area substrate, it is possible to prevent bubble traps and the like by sequentially bonding from one side to the other as shown in FIG. 3F rather than simultaneously bonding the two substrates. The transfer error can be reduced, and even when both substrates are separated after the transfer is completed, they are sequentially separated from one side to the other as shown in FIG. 3G.

3. Gate insulating film and gate formation

3H illustrates a cross section after the transfer is completed, and it can be seen that the nanowires 325 are transferred on the display fabrication substrate 330 on which the buffer layer 335 is formed.

Thereafter, a process of forming the gate insulating film 340 on the surface of the nanowire is performed.

In this case, the gate insulating film may be formed using a silicon oxide film (SiO ₂ ) or a silicon nitride film (Si ₃ N ₄ ), and may be formed in a single layer or a multilayer.

When the gate insulating layer is formed, the gate electrode 345 is formed by sequentially depositing a conductor material and performing a patterning process.

The gate electrode 345 may be formed of a known metal selected from the group consisting of Al, Ta, Cr, Mo, MoTa, ITO, an alloy, and any alloy formed therefrom.

The deposition of the gate electrode may be formed by selecting an appropriate method from among various deposition methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and sputtering or vacuum deposition.

4. Source / Drain Formation

After the process of forming the gate electrode is completed, the implanted impurity ions are implanted using the formed gate electrode as a mask, or a diffusion process is performed to carry out a diffusion region, or the rest of the gate electrode except for the channel region. Can be made high, thereby forming high concentration source / drain regions.

As described above, since the impurity concentration of the source / drain regions is higher than that of the channel region, ohmic contact of the TFT can be facilitated.

5. Interlayer insulating film formation

An interlayer insulating film 350 is formed by forming a silicon oxide film or a silicon nitride film on the entire surface of the substrate on which the above series of processes are performed.

In this case, the interlayer insulating film may be formed in a single layer or in multiple layers.

6. Contact hole formation and source / drain electrode formation

After the interlayer insulating film forming process, the contact hole 355 for opening the predetermined region of the single crystal silicon nanowire is formed by etching the interlayer insulating film and the gate insulating film corresponding to the source / drain regions.

The source / drain electrode 360 is formed by depositing a metal material in the formed contact hole, thereby completing the manufacturing process of the top gate TFT using single crystal silicon nanowires.

Second Embodiment

A second embodiment of the present invention relates to a bottom-gate TFT using a single crystal silicon nanowire and a method of manufacturing the same.

The second embodiment of the present invention will be described in more detail as follows.

1. Single Crystal Silicon Nanowire Formation

Single crystal silicon nanowires are formed in the same manner as in the first embodiment of the present invention.

2. Preparing the Substrate for TFT Formation

On the other hand, a gate electrode and a gate insulating film are formed on a substrate to be manufactured as a display, that is, a substrate on which a TFT is to be formed. In this case, the gate insulating layer may be formed of a single layer or a plurality of layers, and the gate electrode may be formed of the same material and the same method as that of the first embodiment.

3. Transfer of Nanowires

The single crystal silicon nanowires are transferred on the substrate on which the TFT is to be formed.

In this case, the transferred single crystal silicon nanowires are formed on the region where the gate electrode is formed, so that the gate electrode is positioned at the center of the single crystal silicon nanowires.

The process in which the transfer is performed can be formed by the same process as in the first embodiment.

4. Insulation layer formation

After the single crystal silicon nanowires are transferred on the substrate on which the TFT is to be formed, an insulating film is formed on the entire surface of the substrate, and then patterned to form an insulating layer on the channel region of the single crystal silicon nanowires.

5. Source / Drain Formation

When the process of forming the insulating layer is completed, the lower region of the gate electrode, that is, the channel region, can be made high by performing a process of implanting impurity ions using the formed insulating layer as a mask or by performing a diffusion process. This results in the formation of high concentration source / drain regions.

As described above, since the impurity concentration of the source / drain regions is higher than that of the channel region, ohmic contact of the TFT can be facilitated.

Subsequently, after the conductive metal is deposited on the entire surface of the substrate, the conductive metal is patterned using a photoresist pattern and an insulating layer, thereby forming a source / drain electrode.

As a result, the bottom-gate TFT manufacturing process using the single crystal silicon nanowire according to the second embodiment of the present invention can be completed.

Therefore, by applying the single crystal silicon nanowires having excellent characteristics as described in the first or second embodiment of the present invention to the TFT, the performance of the TFT can be increased, which is advantageous in integration.

In addition, as described in the first or second embodiment of the present invention, the process is very simple compared to the prior art, and by manufacturing the TFT in a low temperature process at room temperature or 350 ° C. or lower, a low temperature process such as a flexible display can be achieved. There is an advantage that can be easily applied to the required substrate is required, there is also an advantage in mass production.

Third Embodiment

In the third embodiment of the present invention, the TFT element is formed by changing the process sequence for forming the source / drain of the TFT. More specifically, the ion implantation process is performed in the process of manufacturing single crystal silicon nanowires.

In the third embodiment of the present invention, as in the first embodiment or the second embodiment, a single crystal silicon nanowire is manufactured.

3B, a high concentration impurity implantation region is formed in a specific region of the semiconductor substrate in advance by performing a process of implanting impurity ions or performing a diffusion process before forming the column structure. That is, after forming the source / drain in advance, single crystal silicon nanowires are produced.

A series of processes subsequently performed for TFT formation, including an etching process for forming a column structure, may be performed in the same manner as in the first or second embodiment.

Fourth Embodiment

In the fourth embodiment of the present invention, the TFT elements are formed by changing the process order for forming the source / drain of the TFT. More specifically, unlike the third embodiment, a source / drain formation process is performed during the process of manufacturing single crystal silicon nanowires.

This will be described in more detail as follows.

In the fourth embodiment of the present invention, a single crystal silicon nanowire fabrication process is performed as in the first or second embodiment.

After forming the nanowires as shown in FIG. 3C, the first thermal oxide layer remaining on the nanowires is partially removed to expose only the region where the source / drain is to be formed.

Subsequently, a high concentration of impurity implantation regions are formed at both ends of the single crystal nanowire structure (the region where the source / drain is to be formed) by performing a process of implanting impurity ions or performing a diffusion process.

The substrate is thermally oxidized to form a second thermal oxide film. Thereafter, a series of processes performed to manufacture the released single crystal nanowires and the TFT using the same may be performed in the same manner as in the first or second embodiment.

The source / drain formation process according to the fourth embodiment of the present invention has an advantage that a separate annealing process does not need to be performed due to a thermal oxidation process for forming a second thermal oxide film formed after the formation of a high concentration impurity implantation region. .

[Example 5]

In the fifth embodiment of the present invention, the TFT element is formed by changing the process sequence for forming the source / drain of the TFT. More specifically, unlike the third embodiment, a source / drain formation process is performed during the process of manufacturing single crystal silicon nanowires.

This will be described in more detail as follows.

In the fifth embodiment of the present invention, a single crystal silicon nanowire manufacturing process is performed as in the first or second embodiment.

After forming the second thermal oxide film as shown in FIG. 3D, only an insulating film existing on the single crystal silicon nanowire structure is removed and a photolithography process is performed to expose only the region where the source / drain is to be formed.

Subsequently, a high concentration of impurity implantation regions are formed at both ends of the single crystal nanowire structure (the region where the source / drain is to be formed) by performing a process of implanting impurity ions or performing a diffusion process.

The remaining second thermal oxide film is removed by isotropic dry etching or etching using hydrofluoric acid vapor to produce released single crystal silicon nanowires.

This is illustrated in FIG. 4.

As shown in FIG. 4, it can be seen that a high concentration of impurity implantation regions 410 are formed at both ends of the single crystal silicon nanowire 400.

A series of processes which are subsequently performed to manufacture the TFT can be performed in the same manner as in the first or second embodiment.

The terms or words used in this specification and claims are not to be construed as being limited to their usual or dictionary meanings, and the inventors may appropriately define the concept of terms in order to best describe their invention. It should be interpreted as meaning and concept corresponding to the technical idea of the present invention based on the principle that the present invention.

Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

The present invention can improve the driving characteristics of a TFT by manufacturing a TFT using single crystal silicon nanowires, and has the effect of realizing a system large-scale integration (LSI).

The present invention can easily manufacture the TFT in a low temperature (350 ℃ or less) process there is another effect that is easy to apply to a flexible display that a low temperature process is required.

The present invention has another effect of forming TFTs on various transparent substrates such as glass and polymers.

Claims (13)

A thin film transistor is formed on an insulating substrate, which is one of glass, flexible polymer, plastic, quartz, quartz, and silicon, A channel and a source / drain of the thin film transistor are thin film transistors using single crystal silicon nanowires formed in single crystal silicon nanowires having a triangular columnar cross section. The method of claim 1, The channel is a thin film transistor using a single crystal silicon nanowire formed on at least one single crystal silicon nanowire. delete Forming a single crystal silicon nanowire having a triangular columnar cross section; Transferring the nanowires to a substrate on which a thin film transistor is to be formed; Forming a gate insulating film on the substrate; Forming a gate electrode on the gate insulating film; Forming a source / drain by performing an ion implantation process or a diffusion process using the gate electrode as a mask; Forming an interlayer insulating film on the entire surface of the substrate; Forming a contact hole by etching the interlayer insulating layer on the source / drain; And Depositing a metal material in the contact hole to form a source / drain electrode Thin film transistor manufacturing method using a single crystal silicon nanowire comprising a. Forming a single crystal silicon nanowire comprising a source / drain; Transferring the nanowires to a substrate on which a thin film transistor is to be formed; Forming a gate insulating film on the substrate; Forming a gate electrode on the gate insulating film; Forming an interlayer insulating film on the entire surface of the substrate; Forming a contact hole by etching the interlayer insulating layer on the source / drain; And Depositing a metal material in the contact hole to form a source / drain electrode Thin film transistor manufacturing method using a single crystal silicon nanowire comprising a. Forming a single crystal silicon nanowire having a triangular columnar cross section; Forming a gate electrode on the substrate on which the thin film transistor is to be formed; Forming a gate insulating film on the gate electrode; Transferring the nanowires onto the gate insulating film; Forming an insulating layer on the transferred nanowires and patterning the insulating layer; Forming a source / drain by performing an ion implantation process or a diffusion process using the insulating layer as a mask; And Depositing a metal material on the entire surface of the substrate and then patterning to form a source / drain electrode Thin film transistor manufacturing method using a single crystal silicon nanowire comprising a. Forming a single crystal silicon nanowire comprising a source / drain; Forming a gate electrode on the substrate on which the thin film transistor is to be formed; Forming a gate insulating film on the gate electrode; Transferring the nanowires onto the gate insulating film; Forming an insulating layer on the transferred nanowires and patterning the insulating layer; And Depositing a metal material on the entire surface of the substrate and then patterning to form a source / drain electrode Thin film transistor manufacturing method using a single crystal silicon nanowire comprising a. The method according to claim 4 or 6, The step of forming a single crystal silicon nanowire having a triangular pillar structure, Thermally oxidizing the single crystal silicon substrate to form a first thermal oxide film; Etching the first thermal oxide film to form an oxide film pattern; Etching the silicon substrate to form a column structure; Anisotropically etching the column structure to form nanowires having a triangular columnar cross section; Thermally oxidizing the substrate to form a second thermal oxide film; And Removing the second thermal oxide film to form the released nanowires Thin film transistor manufacturing method using a single crystal silicon nanowire comprising a. The method according to claim 5 or 7, Forming single crystal silicon nanowires comprising source / drain, Performing an ion implantation process or a diffusion process on the source / drain regions of the single crystal silicon substrate; Thermally oxidizing the single crystal silicon substrate to form a first thermal oxide film; Etching the first thermal oxide film to form an oxide film pattern; Etching the silicon substrate to form a column structure; Anisotropically etching the column structure to form nanowires; Thermally oxidizing the substrate to form a second thermal oxide film; And Removing the second thermal oxide film to form the released nanowires Thin film transistor manufacturing method using a single crystal silicon nanowire comprising a. The method according to claim 5 or 7, Forming single crystal silicon nanowires comprising source / drain, Thermally oxidizing the single crystal silicon substrate to form a first thermal oxide film; Etching the first thermal oxide film to form an oxide film pattern; Etching the silicon substrate to form a column structure; Anisotropically etching the column structure to form nanowires; Patterning the first thermal oxide layer on the nanowires to expose only the source / drain regions; Forming a source / drain by performing an ion implantation process or a diffusion process on the exposed source / drain regions; Thermally oxidizing the substrate to form a second thermal oxide film; And Removing the second thermal oxide film to form the released nanowires Thin film transistor manufacturing method using a single crystal silicon nanowire comprising a. The method according to claim 5 or 7, Forming single crystal silicon nanowires comprising source / drain, Thermally oxidizing the single crystal silicon substrate to form a first thermal oxide film; Etching the first thermal oxide film to form an oxide film pattern; Etching the silicon substrate to form a column structure; Anisotropically etching the column structure to form nanowires; Thermally oxidizing the substrate to form a second thermal oxide film; Removing the second thermal oxide film on the nanowire; Exposing only source / drain regions of the nanowires through a pattern forming process; Forming a source / drain by performing an ion implantation process or a diffusion process on the exposed source / drain regions; And Removing the second thermal oxide film to form the released nanowires Thin film transistor manufacturing method using a single crystal silicon nanowire comprising a. The method according to any one of claims 4 to 7, The substrate on which the thin film transistor is to be formed is a thin film transistor using single crystal silicon nanowires, which is any one of glass, flexible polymer, plastic, quartz, quartz and silicon. The method of claim 12, The transfer method of manufacturing a thin film transistor using single crystal silicon nanowires sequentially transfer from one end to the other end of the substrate on which the thin film transistor is to be formed.

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