CN107230681B - Array substrate, preparation method thereof and display device - Google Patents
Array substrate, preparation method thereof and display device Download PDFInfo
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- CN107230681B CN107230681B CN201710313865.7A CN201710313865A CN107230681B CN 107230681 B CN107230681 B CN 107230681B CN 201710313865 A CN201710313865 A CN 201710313865A CN 107230681 B CN107230681 B CN 107230681B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Abstract
The invention provides an array substrate, a preparation method thereof and a display device. The array substrate comprises a switching thin film transistor and a driving thin film transistor, wherein a first active layer of the switching thin film transistor is formed by a doped semiconductor material, and a second active layer of the driving thin film transistor is formed by an undoped semiconductor material. Therefore, the array substrate can not only ensure the switching characteristics of the switching tube, but also improve the carrier mobility of the switching thin film transistor and reduce Vth offset, and simultaneously can reduce the length of the active layer of the driving thin film transistor on the premise of ensuring that the driving thin film transistor has ideal carrier mobility, thereby realizing the design requirement of high resolution.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a preparation method thereof.
Background
With the development of TFT-LCD technology, high carrier mobility, low power consumption, high resolution, etc. have become hot spots of concern.
In the field of flat panel display technology, a Low Temperature Poly-silicon Thin Film Transistor (LTPS TFT) display has the advantages of high response speed, high aperture ratio, high brightness, and the like, and becomes the technology with the fastest market growth speed of the current flat panel display. But it can also be used on flexible displays and organic light emitting diode displays known as next generation display technology. The active layer of the low-temperature polycrystalline silicon thin film transistor is low-temperature polycrystalline silicon (p-Si) which needs to be subjected to ion doping in order to increase the carrier mobility, such as B3+To improve the switching characteristics of the transistor. However, the driving thin film transistor (driving TFT) does not require too high a carrier mobility as compared to the switching thin film transistor (switching TFT). In order to guarantee the requirement on the value of on-state current (Ion) in the conventional design, for a high carrier mobility active layer, the length of the active layer can only be increased to realize the design requirement. But an increase in the length value limits further improvement in resolution.
Therefore, research on the thin film transistor is still in depth.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. To this end, an object of the present invention is to provide an array substrate that reduces a channel length or implements a high resolution technology.
In one aspect of the present invention, an array substrate is provided. According to an embodiment of the present invention, the array substrate includes a switching thin film transistor and a driving thin film transistor, wherein a first active layer of the switching thin film transistor is formed of a doped semiconductor material, and a second active layer of the driving thin film transistor is formed of an undoped semiconductor material. Therefore, the array substrate can not only ensure the switching characteristics of the switching thin film transistor, but also improve the carrier mobility of the switching thin film transistor and reduce the threshold voltage (Vth) offset, and simultaneously can reduce the length of the active layer of the driving thin film transistor on the premise of ensuring the ideal carrier mobility of the driving thin film transistor, thereby realizing the design requirement of high resolution.
According to an embodiment of the present invention, the first active layer is formed of doped low temperature polysilicon and the second active layer is formed of undoped low temperature polysilicon.
According to the embodiment of the present invention, the width-to-length ratio of the second active layer is not less than 3: 30.
In another aspect of the present invention, a display device is provided. According to an embodiment of the present invention, the display device includes the array substrate as described above. Therefore, the display device has higher resolution, low energy consumption and high display quality.
In still another aspect of the present invention, the present invention provides a method of manufacturing an array substrate. According to an embodiment of the present invention, the array substrate includes a switching thin film transistor and a driving thin film transistor, and in the step of forming the active layer, a first active layer of the switching thin film transistor is formed of a doped semiconductor material and a second active layer of the driving thin film transistor is formed of an undoped semiconductor material. The array substrate can be quickly and effectively prepared by the method, the operation is simple, the cost is reduced, the industrial production is easy, the prepared array substrate can not only ensure the switching characteristic of the switching tube, but also improve the carrier mobility of the switching thin film transistor and reduce the Vth offset, and meanwhile, the length of the active layer of the driving thin film transistor can be reduced on the premise of ensuring the driving thin film transistor to have proper carrier mobility, so that the design requirement of high resolution is met.
According to an embodiment of the present invention, the first active layer is formed of doped low temperature polysilicon and the second active layer is formed of undoped low temperature polysilicon.
According to the embodiment of the present invention, the width-to-length ratio of the second active layer is not less than 3: 30.
According to an embodiment of the present invention, the step of forming the active layer is performed by a one-time halftone mask.
According to an embodiment of the present invention, the forming of the active layer includes: forming a semiconductor layer on a substrate; the semiconductor layer is patterned using a half-tone mask to form a first active layer and a second active layer, and the first active layer is doped.
Drawings
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of an array substrate according to another embodiment of the present invention.
Fig. 3 is a schematic flow chart illustrating a process of manufacturing an array substrate according to another embodiment of the present invention.
Fig. 4a to 4e are schematic views illustrating a process for preparing an array substrate according to another embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a product obtained in step S100 according to another embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a product obtained in step S100 according to another embodiment of the present invention.
Detailed Description
The following describes embodiments of the present invention in detail. The following examples are illustrative only and are not to be construed as limiting the invention. The examples, where specific techniques or conditions are not indicated, are to be construed according to the techniques or conditions described in the literature in the art or according to the product specifications. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products commercially available.
In one aspect of the present invention, an array substrate is provided. According to an embodiment of the present invention, referring to fig. 1, the array substrate includes a switching thin film transistor 1 and a driving thin film transistor 2, wherein a first active layer 100 of the switching thin film transistor 1 is formed of a doped semiconductor material, and a second active layer 200 of the driving thin film transistor 2 is formed of an undoped semiconductor material. Therefore, the array substrate can not only ensure the switching characteristics of the switching thin film transistor, but also improve the carrier mobility of the switching thin film transistor and reduce the Vth offset, and simultaneously can reduce the length of the active layer of the driving thin film transistor on the premise of ensuring that the driving thin film transistor has ideal carrier mobility, thereby realizing the design requirement of high resolution.
It will be understood by those skilled in the art that the switching thin film transistor and the driving thin film transistor described above may have necessary structures of a conventional thin film transistor, such as a conventional bottom gate thin film transistor structure or a top gate thin film transistor structure, in addition to the first active layer and the second active layer described above, and the bottom gate thin film transistor structure will be described below as an example, referring to fig. 1, the first active layer 100 and the second active layer 200 are disposed on the substrate 500, the gate insulating layer 800 covers the first active layer 100 and the second active layer 200, the first gate electrode 900 and the second gate electrode 1000 are formed on the side of the gate insulating layer away from the substrate 500, and a projection of the first gate electrode 900 on the substrate 500 falls within a region of a projection of the first active layer 100 on the substrate 500, a projection of the second gate electrode 1000 on the substrate 500 falls within a region of a projection of the second active layer 100 on the substrate, an interlayer insulating layer 1200 is formed on a layer of the gate insulating layer 800 away from the substrate 500, a first drain electrode 1300, a first source electrode 1400, a second drain electrode 1500, and a second source electrode 1600 are disposed on a side of the interlayer insulating layer 1200 away from the substrate 500, the first drain electrode 1300 and the first source electrode 1400 are electrically connected to the first active layer 100 through a via hole, and the second drain electrode 1500 and the second source electrode 1600 are electrically connected to the second active layer 200 through a via hole.
According to an embodiment of the present invention, in order to meet the use requirement of the flexible display device, the substrate 500 in the above array substrate may be a flexible substrate, such as a polymer substrate, including but not limited to a Polyimide (PI), a flexible substrate formed of polyester, and the like. Therefore, the thin film transistor has ideal flexibility while providing good supporting effect for the thin film transistor, and can be applied to a flexible display device. According to the embodiment of the invention, because the flexible substrate has certain flexibility, in the preparation process, a deposited flexible film, such as a polyimide film and/or a polyester film, can be formed on a base with a good supporting function in advance, then a thin film transistor structure and an electrode structure of an array substrate are formed on the flexible film, and finally the base is peeled off, so that the flexible substrate is formed by the flexible film.
According to an embodiment of the present invention, in order to further improve the bonding force between the thin film transistor structure and the substrate and form a thin film transistor structure with better performance, referring to fig. 2, the array substrate may further include a buffer layer 300, and the buffer layer 300 is disposed between the substrate 500 and the active layer. Therefore, the strength between the thin film transistor and the substrate can be improved, and meanwhile, the use performance of the thin film transistor is improved.
The material and method for forming the buffer layer according to the embodiment of the present invention are not particularly limited, and those skilled in the art can flexibly select the material and method according to actual situations. According to some embodiments of the invention, the buffer layer is formed of a material including, but not limited to, SiN and SiO2At least one of (1). Moreover, the buffer layer may be a single-layer structure or a multi-layer structure, and the thickness of the buffer layer has no special requirement, and those skilled in the art can flexibly select the thickness, for example, the thickness may be 50 to 650 nm. According to some embodiments of the present invention, the buffer layer may be a 50-150 nm SiN layer and 100-500 nm SiO2A bilayer structure of layers. The method for forming the buffer layer can be flexibly selected by those skilled in the art according to actual requirements, and examples include but are not limited to physical vapor deposition methods, chemical vapor deposition methods, such as plasma enhanced chemical vapor deposition.
According to the embodiment of the present invention, there is no particular requirement for the materials forming the first active layer and the second active layer, and those skilled in the art can flexibly select the materials according to actual situations. According to some embodiments of the invention, the first active layer is formed of doped low temperature polysilicon and the second active layer is formed of undoped low temperature polysilicon. Therefore, the first active layer carrier can achieve high mobility, meanwhile, the second active layer carrier can be guaranteed not to have high mobility, the energy consumption of the thin film transistor is lower, and the stability is higher.
According to the embodiment of the present invention, there is no particular requirement for a method of forming the first active layer and the second active layer, and those skilled in the art can flexibly select the method according to actual situations. According to some embodiments of the present invention, the method of forming the active layer may include, but is not limited to, physical vapor deposition, chemical vapor deposition such as plasma enhanced chemical vapor deposition, and the like. According to still other embodiments of the present invention, a layer of amorphous silicon (a-Si) is deposited by a plasma enhanced chemical vapor deposition method to a certain thickness on a side of the buffer layer away from the substrate, then a low temperature polysilicon is formed by an excimer laser crystallization process, then the low temperature polysilicon is patterned to form a first active layer and a second active layer, and finally ions to be doped are implanted into the first active layer, thereby obtaining a first active layer formed by doped low temperature polysilicon and a second active layer formed by undoped low temperature polysilicon. Therefore, the preparation method is mature, the operation is simple, and the industrial production is easy to realize.
According to an embodiment of the present invention, the thickness of the amorphous silicon formed as described above is not particularly limited, and may be flexibly selected by those skilled in the art as needed. In some embodiments of the invention, the thickness of the amorphous silicon may be 30-100 nm. Thus, an active layer having an appropriate thickness and better performance can be formed.
According to the embodiment of the present invention, there is no particular requirement for the ion species to be doped into the first active layer as long as the requirement for improving the carrier mobility thereof can be achieved. According to some embodiments of the invention, the ions doping the first active layer may include, but are not limited to, B3+、Al3+And so on. Therefore, the first active layer can have higher carrier mobility。
According to the embodiment of the invention, the array substrate can ensure that the second active layer in the driving thin film transistor has a shorter length on the premise of ensuring the service performance of the driving thin film transistor. According to some embodiments of the present invention, the aspect ratio of the second active layer may be not less than 3: 30. According to further embodiments of the present invention, the aspect ratio of the active layer may be 3:30 to 3: 26. According to other embodiments of the present invention, the aspect ratio of the active layer may also be less than 3:26, such as may be 3: 25. 3: 24. 3: 23. 3: 22. 3: 21. 3: 20, etc. Therefore, the low carrier mobility of the driving thin film transistor is ensured, the length of the active layer can be effectively reduced, high resolution is realized, and the display quality of the display device is improved.
In another aspect of the present invention, a display device is provided. According to an embodiment of the present invention, the display device includes the array substrate as described above. The display device has higher resolution and ideal display effect. And those skilled in the art will understand that the display device includes all the features and advantages of the above-mentioned array substrate, and thus the detailed description thereof is omitted here.
According to the embodiment of the present invention, the specific type of the display device is not particularly limited, and may be any device or apparatus having a display function in the art, for example, including but not limited to a mobile phone, a tablet computer, a computer monitor, a game machine, a television, a display screen, a wearable apparatus, and other life or household appliances having a display function.
Of course, it can be understood by those skilled in the art that the display device of the present invention may include necessary structures and components of a conventional display device in addition to the array substrate, and a mobile phone is taken as an example for illustration.
In still another aspect of the present invention, the present invention provides a method of manufacturing an array substrate. According to an embodiment of the present invention, the array substrate includes a switching thin film transistor and a driving thin film transistor, and in the step of forming the active layer, a first active layer of the switching thin film transistor is formed of a doped semiconductor material and a second active layer of the driving thin film transistor is formed of an undoped semiconductor material. The method can be used for quickly and effectively preparing the array substrate, is simple to operate, reduces the cost and is easy for industrial production. The array substrate prepared by the method can ensure the switching characteristics of the switching tube, improve the carrier mobility of the switching thin film transistor, reduce Vth offset, reduce the length of the active layer of the driving thin film transistor on the premise of ensuring the ideal carrier mobility of the driving thin film transistor, and meet the design requirement of high resolution.
Those skilled in the art will appreciate that the method may further include the step of forming a gate insulating layer, a gate electrode, an interlayer insulating layer, a source/drain electrode, and other structures, which may be performed according to conventional operations.
According to the embodiment of the present invention, there is no particular requirement for the materials forming the first active layer and the second active layer, and those skilled in the art can flexibly select the materials according to actual situations. According to some embodiments of the invention, the first active layer is formed of doped low temperature polysilicon and the second active layer is formed of undoped low temperature polysilicon. Therefore, the first active layer carrier can achieve high mobility, meanwhile, the second active layer carrier can be guaranteed not to have high mobility, the energy consumption of the thin film transistor is lower, and the stability is higher.
According to an embodiment of the present invention, the step of forming the active layer is performed by a one-time halftone mask. According to some embodiments of the present invention, referring to fig. 3, the step of forming the active layer includes:
s100: a semiconductor layer is formed on a substrate, and the structure schematic diagram refers to fig. 4 a.
According to the embodiment of the present invention, the method for forming the semiconductor layer 600 has no special requirement, and those skilled in the art can flexibly select the method according to the actual situation. According to some embodiments of the present invention, the method of forming the semiconductor layer 600 may include, but is not limited to, physical vapor deposition, chemical vapor deposition such as plasma enhanced chemical vapor deposition. Referring to fig. 4a, a layer of amorphous silicon (a-Si) with a certain thickness is deposited on one side of a substrate by a plasma enhanced chemical vapor deposition method, and then low temperature polysilicon (P-Si) is formed by an excimer laser crystallization process, thereby obtaining a semiconductor layer 600. Therefore, the preparation method is mature, the operation is simple, and the industrial production is easy to realize.
According to an embodiment of the present invention, the thickness of the amorphous silicon formed as described above is not particularly limited, and may be flexibly selected by those skilled in the art as needed. In some embodiments of the invention, the thickness of the amorphous silicon may be 30-100 nm. Thus, an active layer having an appropriate thickness and better performance can be formed.
S200: the semiconductor layer is patterned using a half-tone mask to form a first active layer and a second active layer.
According to an embodiment of the present invention, referring to fig. 4b and 4c, in this step, a photoresist layer 700 is first formed on the semiconductor layer 600, then the photoresist layer is exposed and developed by using the halftone mask 10, then the exposed semiconductor layer 600 is etched to form the first active layer 100 and the second active layer 200, and the product structure after etching is schematically illustrated in fig. 4 c. Specifically, the half-tone mask 10 is the half-transparent region 12 at a position corresponding to the first active layer 100, the shielding region 11 at a position corresponding to the second active layer 200, and the full-transparent region 13 at the rest positions, so that after the development, the photoresist corresponding to the full-transparent region is completely removed, a portion of the photoresist corresponding to the half-transparent region is removed, and the photoresist corresponding to the shielding region remains as it is.
According to the embodiment of the invention, the array substrate can ensure that the second active layer in the driving thin film transistor has a shorter length on the premise of ensuring the service performance of the driving thin film transistor. According to some embodiments of the present invention, the aspect ratio of the second active layer may be not less than 3: 30. According to further embodiments of the present invention, the aspect ratio of the active layer may be 3:30 to 3: 26. According to other embodiments of the present invention, the aspect ratio of the active layer may also be less than 3:26, such as may be 3: 25. 3: 24. 3: 23. 3: 22. 3: 21. 3: 20, etc. Therefore, the low carrier mobility of the driving thin film transistor is ensured, the length of the active layer can be effectively reduced, high resolution is realized, and the display quality of the display device is improved.
S300: and carrying out doping treatment on the first active layer.
In step S200, referring to fig. 4d and 4e, the photoresist layer is exposed and developed again using the halftone mask 10, after the development, the photoresist corresponding to the first active layer 100 is completely removed, the photoresist corresponding to the second active layer 200 remains, then, the first active layer is ion-implanted to obtain the first active layer 100 formed of the doped semiconductor material, and finally, the photoresist corresponding to the second active layer 200 is removed, thereby obtaining the first active layer 100 formed of the doped semiconductor material and the second active layer 200 formed of the undoped semiconductor material.
According to the embodiment of the present invention, there is no particular requirement for the ion species to be doped into the first active layer as long as the requirement for improving the carrier mobility thereof can be achieved. According to some embodiments of the invention, the ions doping the first active layer may include, but are not limited to, B3+、Al3+And so on.
According to the embodiments of the present invention, as described above, the method may further include a step of forming other structures such as a gate insulating layer, a gate electrode, an interlayer insulating layer, a source drain electrode, and the like, and therefore, in some embodiments of the present invention, on the basis of step S300, the following steps may be further included: referring to fig. 1, a gate insulating layer 800 is coated on the surface of an active layer, a first gate electrode 900 and a second gate electrode 1000 are formed on the side of the gate insulating layer away from a substrate, the projection of the first gate electrode 900 on the substrate falls within the region of the projection of the first active layer 100 on the substrate 500, the projection of the second gate electrode 1000 on the glass substrate 500 falls within the region of the projection of the second active layer 100 on the substrate, an interlayer insulating layer 1200 is formed on the layer of the gate insulating layer 800 away from the substrate 500, a first drain electrode 1300, a first source electrode 1400, a second drain electrode 1500 and a second source electrode 1600 are formed on the side of the interlayer insulating layer 1200 away from the substrate 500, and the first drain electrode 1300 and the first source electrode 1400 are connected to the first active layer 100 through a via hole, and the second drain electrode 1500 and the second source electrode 1600 are connected to the second active layer 200 through a. Of course, it can be understood by those skilled in the art that fig. 1 is a schematic structural diagram of the switching thin film transistor and the driving thin film transistor both having the top gate structure, which is only an exemplary illustration of the structure of the array substrate of the present application, and should not be understood as a limitation to the present invention, and reasonable changes and substitutions made on the basis of the present invention are within the protection scope of the present invention as long as they do not depart from the inventive concept of the present invention.
According to other embodiments of the present invention, referring to fig. 5, before forming the semiconductor layer 600, the buffer layer 300 may be formed on the substrate 500 in advance, and then the above steps are performed, and the structure diagram of the obtained product is shown in fig. 2. Therefore, the bonding strength between the substrate and structures such as a semiconductor layer 600 formed later can be improved, and the use performance of the array substrate can be improved. The specific method for forming the buffer layer 300 is not particularly limited, and those skilled in the art can flexibly select the method according to actual needs, such as physical vapor deposition, chemical vapor deposition, and the like.
According to an embodiment of the present invention, referring to fig. 6, when the substrate 500 is a flexible substrate, before forming the semiconductor layer 600, the flexible substrate 500 needs to be formed on the base 400 with good supporting function in advance, then the semiconductor layer 600 is formed on the flexible substrate 500, and then the base 400 needs to be peeled off, so as to obtain the flexible array substrate with the structure shown in fig. 2.
In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (5)
1. The array substrate is characterized by comprising a switching thin film transistor and a driving thin film transistor, wherein a first active layer of the switching thin film transistor is formed by doped low-temperature polycrystalline silicon, a second active layer of the driving thin film transistor is formed by undoped low-temperature polycrystalline silicon, and the width-to-length ratio of the second active layer is not less than 3: 30.
2. A display device comprising the array substrate according to claim 1.
3. The method for preparing the array substrate is characterized in that the array substrate comprises a switching thin film transistor and a driving thin film transistor, in the step of forming active layers, a first active layer of the switching thin film transistor is formed by doped low-temperature polycrystalline silicon, a second active layer of the driving thin film transistor is formed by undoped low-temperature polycrystalline silicon, and the width-to-length ratio of the second active layer is not less than 3: 30.
4. The method of claim 3, wherein the step of forming the active layer is performed by a one-time half-tone mask.
5. The method of claim 4, wherein the step of forming the active layer comprises:
forming a semiconductor layer on a substrate;
patterning the semiconductor layer using the halftone mask to form the first active layer and the second active layer, and performing doping treatment on the first active layer.
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