KR100783643B1 - Method of manufacturing semiconductor device - Google Patents

Abstract

A method for fabricating a semiconductor device is provided to reduce an area occupied by a capacitor in a peripheral region by forming the capacitor in a cell region and the peripheral region in the same shape. When a landing plug(203a) is formed on a cell region of a semiconductor substrate(200), a landing plug(203b) is simultaneously formed on a peripheral region of the substrate in the same shape as the landing plug formed in the cell region. When a storage node contact plug(205a) is formed on the cell region, a storage contact plug(205b) is simultaneously formed on the peripheral region in the same shape as the storage node plug formed on the cell region. When a capacitor(210a) is formed on the cell region, a capacitor(210b) is formed on the peripheral region in the same shape.

Description

Method of manufacturing semiconductor device

1 is a cross-sectional view showing a semiconductor device including a capacitor in a conventional peripheral region.

 2A to 2C are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

200: semiconductor substrate 201: device isolation film

202: gates 203a and 203b: landing plugs

204a, 204b: bitline contacts 205a, 205b: bitline

206a, 206b: Contact Plugs for Storage Nodes

207a and 207b storage nodes 208a and 208b dielectric films

209a and 209b plate nodes 210a and 210b capacitors

211a, 211b: Metal contact plug 212a, 212b: Metal wiring

291: first insulating film 292: second insulating film

293: third insulating film 294: fourth insulating film

295: fifth insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of forming a capacitor of high capacity in a narrow area in a peripheral area.

As the productivity of DRAM (DRAM) and the technology (Tech) evolve, the design rules of semiconductor devices are gradually getting smaller, and the circuit configuration method in the peripheral area is becoming more important.

In general, circuits in the peripheral region require many capacitors such as a pumping capacitor or a reservoir capacitor for the purpose of charge pumping or stabilization of voltage level.

In the technology under development up to now, as shown in FIG. 1, a large-sized transistor (Tr) is fabricated in a peripheral region, and a gate oxide film (Gate Oxide) of the transistor is used as a capacitor to pump a capacitor, or In other words, it constitutes a Reservior Capacitor, and occupies a large area corresponding to ˜30% of the area in the peripheral area.

In FIG. 1, reference numeral G denotes a gate, BLC denotes a bit line contact, BL denotes a bit line, M1C denotes a first contact plug, and M1 denotes a first metal wiring.

On the other hand, as the design rule of the device is gradually smaller, correspondingly smaller peripheral area is also correspondingly smaller due to the capacitor occupying a large area is inevitable a lot of losses in terms of the area of the peripheral area.

In other words, a large number of capacitors are required in the peripheral area. As the capacitor occupies a large part of the total area of the peripheral area, this is a situation that is a big obstacle in terms of area, and the pressure level is decreasing. Considering this, it will be a bigger problem in the future.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of forming a capacitor of high capacity while having a narrow area, and a method of manufacturing the same.

In order to achieve the above object, the present invention comprises the steps of forming a transistor consisting of a gate and a source / drain region in the cell region of the semiconductor substrate divided into a cell region and a peripheral region; Forming a landing plug on the source / drain regions of the cell region; Forming a bit line contact on a landing plug formed in the drain region of the cell region; Forming a bit line on a bit line contact of the cell area; Forming a contact plug for a storage node on a landing plug formed in the source region of the cell region; And forming a capacitor comprising a storage node, a dielectric layer, and a plate node on a contact plug for a storage node in the cell region.

When the landing plug of the cell region is formed, the landing plug is simultaneously formed on the substrate of the peripheral region in the same form, and when the contact plug for the storage node of the cell region is formed, the landing plug of the peripheral region is simultaneously formed with the same shape. The present invention provides a method of manufacturing a semiconductor device in which a contact plug for a storage node is formed, and when the capacitor is formed in the cell region, a capacitor is simultaneously formed on the storage node contact plug in the peripheral region.

Here, when the bit line contacts are formed in the cell region, the method may include simultaneously forming bit line contacts on the substrate of the peripheral region in the same form.

Forming a bit line contact on the bit line contact of the peripheral region when forming the bit line of the cell region.

 After forming a capacitor comprising a storage node, a dielectric layer, and a plate node on the contact plug for the storage node in the cell region, forming a metal contact plug on the capacitor in the cell region; And forming a metal wire on the metal contact plug.

When the metal contact plug and the metal wiring are formed in the cell region, the metal contact plug and the metal wiring may be simultaneously formed in the same shape on the capacitor of the peripheral region.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2C.

Referring to FIG. 2A, the gate region 202 and the source / drain region S / D are formed in the cell region of the semiconductor substrate 200, which is divided into a cell region and a peripheral region and whose active region is defined by the device isolation layer 201. After forming the transistor, the first contact hole H211 for landing plug exposing the source / drain regions S / D of the cell region by performing a deposition and etching process of the first insulating layer 291 on the transistor. And a second contact hole H212 for landing plug that exposes the substrate portion of the peripheral area.

Thereafter, a process of depositing and etching the first conductive layer on the first insulating layer 291 is performed to form the first landing plug 203a in the first contact hole H211 for the landing plug of the cell region. A second landing plug 203b is formed in the first contact hole H212 for the landing plug in the peripheral area in the same manner as the first landing plug 203a.

Next, a process of depositing and etching the second insulating layer 292 on the first insulating layer 291 including the first landing plug 203a and the second landing plug 203b is performed. The second contact hole H222 for the bit line contact that exposes the substrate portion of the peripheral area while forming the first contact hole H221 for exposing the first landing plug 203a formed in D). After the formation, the deposition process and the etching process of the second conductive film on the second insulating film 292 is performed to form the first bit line contact 204a in the first contact hole H221 for the bit line contact in the cell region. At the same time, a second bit line contact 204b is formed in the second contact hole H222 of the peripheral area in the same form as the first bit line contact 204a.

Subsequently, a process of depositing and etching a third conductive film on the second insulating layer 292 including the first bit line contact 204a and the second bit line contact 204b may be performed to form the first bit line contact ( The second bit line 205b is formed on the second bit line contact 204b of the peripheral area in the same form as the first bit line 205a while forming the first bit line 205a on the 204a. Form.

Referring to FIG. 2B, a process of depositing and etching a third insulating layer 293 on the second insulating layer 292 including the first bit line 205a and the second bit line 205b may be performed to form the cell region. A storage node agent which exposes the second landing plug 203b of the peripheral area while forming a first contact hole H231 for the storage node that exposes the first landing plug 203a formed in the source region S. After the second contact hole H232 is formed, a process of depositing and etching a fourth conductive layer on the third insulating layer 293 is performed to form a first storage node in the first contact hole H231 for the storage node in the cell region. The second storage node contact plug 206b is formed in the same form as the first storage node contact plug 206a in the second contact hole H232 for the storage node in the peripheral area while forming the contact plug 206a. do.

Thereafter, a process of depositing and etching the fourth insulating layer 294 on the third insulating layer 293 including the first storage node contact plug 206a and the second storage node contact plug 206b is performed. After forming the first hole (H241) for exposing the first storage node contact plug 206a of the second and the second hole (H242) for exposing the second storage node contact plug (206b) of the peripheral area, The first capacitor 210a is formed by sequentially forming the storage node 207a, the dielectric layer 208a, and the plate node 209a on the fourth insulating layer 294 including the first hole H241 in the cell region. At the same time, the storage node 207b, the dielectric film 208b, and the plate node are formed on the fourth insulating layer 294 including the second storage node contact plug 206b in the peripheral area in the same form as the first capacitor 210a. A second capacitor 210b formed of 209b is formed.

Referring to FIG. 2C, a portion of the plate node 209a of the first capacitor of the cell region may be formed by performing a deposition and etching process of a fifth insulating layer 295 on the first capacitor 2310a and the second capacitor 210b. Forming a first contact hole H251 for exposing the metal contact plug and forming a second contact hole H252 for the metal contact plug exposing the portion of the plate node 209b of the second capacitor in the peripheral region. Thereafter, a process of depositing and etching a fifth conductive layer on the fifth insulating layer 295 to form a first metal contact plug 211a in the first contact hole H251 for the metal contact plug in the cell region. At the same time, the second metal contact plug 211b is formed in the second contact hole H252 for the metal contact plug H252 in the peripheral area in the same manner as the first metal contact plug 211a.

Thereafter, a process of depositing and etching a sixth conductive layer on the fifth insulating layer 255 including the first metal contact plug 211a and the second metal contact plug 211b is performed to form a first metal contact in the cell region. The first metal wiring 212a is formed on the plug 211a and the second metal wiring 212b has the same shape as the first metal wiring 212a on the second metal contact plug 211b of the peripheral region. To form.

As described above, when the capacitor is formed in the cell region, the capacitor is simultaneously formed in the peripheral region in the same form, thereby forming a capacitor having a high capacitance while having a narrow area in the peripheral region.

That is, according to the present invention, a capacitor having the same type as a capacitor formed in a cell region is formed in a peripheral region, so that a pumping capacitor, which is an object for charge pumping or stabilization of a voltage level in the peripheral region, Alternatively, the reservoir capacitor can be formed in a narrow area, thereby reducing the area occupied by the capacitor in the peripheral area.

Therefore, the present invention can have a large area reduction effect in terms of the area of the peripheral area.

As described above, the embodiments of the present invention have been described above, but the present invention is not limited thereto, and those skilled in the art may make many modifications and variations without departing from the spirit of the present invention. Will understand.

As described above, according to the present invention, by forming the same capacitor in the peripheral area as the capacitor of the cell area, the area occupied by the capacitor in the peripheral area can be reduced, so that a large area reduction effect can be expected in terms of the area of the peripheral area. Can be.

As described above, the present invention can achieve a reduction effect between semiconductor chips due to the area saving effect of the peripheral area.

Claims (5)

Forming a transistor comprising a gate and a source / drain region in a cell region of the semiconductor substrate divided into a cell region and a peripheral region; Forming a landing plug on the source / drain regions of the cell region; Forming a bit line contact on a landing plug formed in the drain region of the cell region; Forming a bit line on a bit line contact of the cell area; Forming a contact plug for a storage node on a landing plug formed in the source region of the cell region; And forming a capacitor comprising a storage node, a dielectric layer, and a plate node on a contact plug for a storage node in the cell region. When the landing plug of the cell region is formed, the landing plug is simultaneously formed on the substrate of the peripheral region in the same shape, When forming the contact plug for the storage node in the cell region, simultaneously forming the contact plug for the storage node in the same form on the landing plug of the peripheral region, And forming capacitors on the storage node contact plugs of the peripheral region at the same time when the capacitors are formed in the cell region. The method of claim 1, Forming bit line contacts in the cell region at the same time on the substrate of the peripheral region in the same manner. The method of claim 1, And forming bit line contacts simultaneously on the bit line contacts of the peripheral region when forming the bit lines of the cell region. The method of claim 1,  After forming a capacitor including a storage node, a dielectric layer, and a plate node on the contact plug for the storage node in the cell region, Forming a metal contact plug on the capacitor in the cell region; And Forming a metal wiring on the metal contact plug; manufacturing method of a semiconductor device further comprising. The method of claim 4, wherein When the metal contact plug and the metal wiring in the cell region, forming a metal contact plug and a metal wiring at the same time on the capacitor of the peripheral region, characterized in that for forming a semiconductor device.

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