KR100761072B1 - Flat panel display and fabricating method of the same - Google Patents

Abstract

The present invention relates to a flat panel display device and a manufacturing method thereof, and more particularly, to a flat panel display device having a patterned double buffer structure and a method of manufacturing the same. A substrate having a light emitting area and a non-light emitting area; A first buffer layer pattern exposing the emission area and formed of an amorphous silicon film; A second buffer layer positioned on the first buffer layer pattern; A semiconductor layer on the second buffer layer; And a gate electrode on the semiconductor layer.

Double buffer layer, amorphous silicon (a-Si: H)

Description

Flat panel display and fabricating method of the same

1A to 1C are cross-sectional views illustrating a manufacturing method for a flat panel display according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

100: substrate, 105: first buffer layer

110: second buffer layer, 115: semiconductor layer

120: gate insulating film, 125: gate electrode

130: interlayer insulating film, 135a, 135b: source electrode, drain electrode

       145: pixel electrode, 155: light emitting layer

       160: counter electrode

The present invention relates to a flat panel display and a manufacturing method thereof, and more particularly, to a flat panel display having a patterned double buffer structure.

In general, a flat panel display is divided into a passive matrix method and an active matrix method according to a driving method, and the active driving method includes circuits using thin film transistors (TFTs). Such circuits are typically used in flat panel display devices such as liquid crystal displays (LCDs) and organic electroluminescence displays (OLEDs).

Among the thin film transistors, polycrystalline silicon thin film transistors can be manufactured at a low temperature similar to that of amorphous silicon thin film transistors due to the development of crystallization technology. In addition, the mobility of electrons and holes is higher than that of amorphous silicon thin film transistors, and it is possible to implement a complementary metal-oxide semiconductor (CMOS) thin film transistor so that a thin film transistor for driving circuit and a thin film transistor for pixel driving can be simultaneously formed on a substrate. It became. A method of forming a polycrystalline silicon film used as an active layer of the thin film transistor typically uses a method of depositing an amorphous silicon film on an insulating substrate and then crystallizing at a predetermined temperature to form a polycrystalline silicon film.

However, impurities present in the substrate during the crystallization process are diffused from the substrate to the semiconductor layer, resulting in a problem of deterioration of device characteristics of the thin film transistor. In addition, a large number of crystal defects occur in the polycrystalline silicon film after the crystallization process. In order to solve such a problem, that is, in order to prevent diffusion of substrate impurities into the semiconductor layer, a method of forming a buffer layer on a substrate has been conventionally used, and a method of passivation to reduce crystal defects in a polycrystalline silicon film has been used. I have used

In addition, the conductive films formed in the thin film transistor of the flat panel display may cause diffuse reflection of external light, which may make it difficult to realize a perfect black color. In addition, the diffuse reflection causes a user to feel glare. This problem has been solved by forming a layer called black matrix that serves to prevent diffuse reflection.

However, although the buffer layer, the passivation process and the black matrix all serve to solve the above problems, there are manufacturing problems in which the process is complicated by being formed through different processes, thereby increasing the process variables and increasing the defect factor. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a flat panel display device in which a buffer layer and a black matrix are simultaneously formed by including a thin film transistor using a patterned amorphous silicon film as a buffer layer.

Another object of the present invention is to provide a thin film transistor having an effect of passivation by using a hydrogenated patterned amorphous silicon film buffer layer and a flat panel display device including the same.

The present invention to achieve the above object is a substrate having a light emitting area and a non-light emitting area; A first buffer layer pattern exposing the emission area and formed of an amorphous silicon film; A second buffer layer positioned on the first buffer layer pattern; A semiconductor layer on the second buffer layer; And a gate electrode on the semiconductor layer.

The second buffer layer may be a silicon oxide film (SiO 2) or a silicon nitride film (SiN x).

The thickness of the second buffer layer may be 1000 to 3000 kPa.

The first buffer layer may contain hydrogen.

The thickness of the first buffer layer may be 500 to 1000 microns.

The semiconductor layer may be formed by crystallizing an amorphous silicon film.

The crystallization may be to use one method selected from the group consisting of ELA, SLS, MIC and MILC.

The flat panel display may be an organic light emitting display or a liquid crystal display.

Preparing a substrate having a light emitting area and a non-light emitting area;

Forming a first buffer layer by forming an amorphous silicon film on the substrate;

In addition, to achieve the above object, the present invention comprises the steps of exposing the light emitting region by patterning the first buffer layer; Forming a second buffer layer on the patterned first buffer layer; Forming a thin film transistor on the second buffer layer; And forming a pixel electrode electrically connected to the thin film transistor on the thin film transistor.

The second buffer layer may be a silicon oxide film (SiO 2) or a silicon nitride film (SiN x).

The thickness of the second buffer layer may be 1000 to 3000 kPa.

The first buffer layer may contain hydrogen by forming using the CVD method.

The thickness of the first buffer layer may be 500 to 1000 microns.

Forming the semiconductor layer on the second buffer layer; And forming a gate electrode, a source electrode, and a drain electrode.

The semiconductor layer may be formed by forming and crystallizing an amorphous silicon film.

The crystallization may be performed using one method selected from the group consisting of ELA, SLS, MIC and MILC.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, lengths, thicknesses, and the like of layers and regions may be exaggerated for convenience. Like numbers refer to like elements throughout.

1C is a cross-sectional view of a flat panel display device according to an exemplary embodiment of the present invention.

Referring to the drawings, a first buffer layer 105 formed of an amorphous silicon film is positioned on a substrate 100 having a light emitting area B and a non-light emitting area A. Referring to FIG. The first buffer layer 105 may be located only in the non-light emitting area A to further increase the transmittance of emitted light, and may contain hydrogen.

 Hydrogen contained in the first buffer layer may passivate dangling bonds present in the semiconductor layer in a subsequent heat treatment process, thereby mitigating defects in the semiconductor layer. However, when the first buffer layer has a thickness of 1000 GPa or more, since hydrogen is excessively introduced into the semiconductor layer during passivation and the semiconductor characteristics are degraded, the thickness of the first buffer layer is preferably 500 to 1000 GPa. In addition, the amorphous silicon film of the first buffer layer may block external light due to the low transmittance of the film, and may act as a black matrix to solve the problem of light reflected by the thin film transistor and the wiring in the flat panel display device. .

The second buffer layer 110 is positioned on the first buffer layer 105. The second buffer layer 110 may be a silicon oxide film (SiO 2) or a silicon nitride film (SiN x), and the thickness of the second buffer layer may be 1000 to 3000 μm. The second buffer layer 110 is preferably 1000 GPa or more, and more preferably formed of a silicon oxide film (SiO 2) for efficient blocking of impurities generated from the substrate.

The semiconductor layer 115 is positioned on the second buffer layer 110, and the semiconductor layer 115 may be formed by forming an amorphous silicon film on the second buffer layer and crystallizing it. The crystallization may use one method selected from the group consisting of ELA, SLS, MIC and MILC.

The gate insulating layer 120 and the gate electrode 125 are positioned on the substrate on which the semiconductor layer 115 is formed, and the interlayer insulating layer 130 is positioned on the substrate. In addition, a source electrode 135a or a drain electrode 135b which is in contact with the semiconductor layer 115 is disposed on the interlayer insulating layer 130.

The passivation layer 140 is disposed on the source electrode 135a or the drain electrode 135b over the entire surface of the substrate. A via hole exposing the source electrode or the drain electrode of the thin film transistor is formed in the passivation layer 140, and the source electrode 135a or the drain electrode 135b and the pixel electrode 150 are contacted through the via hole.

A pixel definition layer PDL 160 is positioned on the pixel electrode 150, and the pixel electrode 150 is exposed along the pixel opening region defined by the pixel definition layer. The emission layer 160 is positioned on the exposed pixel electrode 150, and the opposite electrode 180 is formed on the emission layer 160 to form a flat panel display device. The flat panel display may be an organic light emitting display or a liquid crystal display.

When the flat panel display is an organic electroluminescent display, one or more organic layers may be further formed on the light emitting layer 160 in the group consisting of a hole injection layer, a hole transport layer, a hole suppression layer, and an electron injection layer. have. In addition, the counter electrode 180 becomes a cathode or an anode of the organic light emitting diode, and serves as an electrode of the organic light emitting display device together with the pixel electrode 150.

1A to 1C are cross-sectional views illustrating a method of manufacturing a flat panel display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, an amorphous silicon film as a first buffer layer is formed on a substrate 100 having a light emitting area B and a non-light emitting area A. Referring to FIG. The amorphous silicon film is preferably formed by chemical vapor deposition (CVD). The chemical vapor deposition method may use one method selected from the group consisting of low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD) and plasma chemical vapor deposition (PECVD). In the chemical vapor deposition method, a gas of SiH ₄ is used, and the first buffer layer may be formed to contain hydrogen. In addition, the thickness of the first buffer layer may be 500 to 1000 kPa.

The deposited amorphous silicon film is patterned. At this time, in order to further increase the transmittance of the emitted light, the amorphous silicon film is removed in the emission area B. FIG.

The amorphous silicon layer, which is the first buffer layer, may block external light due to a low transmittance, and may block a contrast reduction problem by blocking light that is incident on the flat panel display and reflected outside by the films formed therein. Therefore, no additional process for forming the black matrix is required, which leads to a simplification of the process.

The second buffer layer 110 is formed on the patterned first buffer layer 105. The second buffer layer 110 may be formed by chemical vapor deposition (CVD). The chemical vapor deposition method may use one method selected from the group consisting of low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), and plasma chemical vapor deposition (PECVD).

The second buffer layer 110 may be a silicon oxide film (SiO 2) or a silicon nitride film (SiN x), and the thickness of the second buffer layer may be 1000 to 3000 μm. The second buffer layer 110 is preferably 1000 GPa or more, and more preferably formed of a silicon oxide film (SiO 2) for efficient blocking of alkali-based impurities generated from a substrate and diffused into the semiconductor layer.

An amorphous silicon film is formed on the second buffer layer. The amorphous silicon film may be formed by chemical vapor deposition (CVD). The chemical vapor deposition method may use one method selected from the group consisting of low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), and plasma chemical vapor deposition (PECVD).

The amorphous silicon film is crystallized. The method of crystallization can be carried out using one method selected from the group consisting of ELA, SLS, MIC and MILC. After the crystallization process, the crystalline silicon film is patterned to form the semiconductor layer 115.

In addition, the semiconductor layer 115 may be formed by forming an amorphous silicon film and performing crystallization after patterning the amorphous silicon film.

Referring to FIG. 1B, a gate insulating layer 120 is formed over the entire surface of the semiconductor layer 115. The gate insulating layer 120 may be formed using a conventional material, for example, a silicon oxide film (SiO 2) or a silicon nitride film (SiN x).

A gate electrode 125 is formed on the gate insulating layer 120. The gate electrode 125 may be formed by forming a film using a conductive film and then patterning the film. The conductive film may be performed using one material selected from the group consisting of a metal film, a crystalline silicon film, and a transparent conductive film.

After the gate electrode 125 is formed, ions are implanted into the semiconductor layer 115 using the gate electrode 125 as a mask. Due to the ion implantation, a source region and a drain region are formed in the semiconductor layer. As a result, the semiconductor layer 115 includes a source region, a drain region, and a channel region.

An interlayer insulating layer 130 is formed on the substrate on which the gate electrode 125 is formed. The interlayer insulating film may be formed using a conventional insulating material, for example, a silicon oxide film (SiO 2) or a silicon nitride film (SiN x).

A contact hole is formed in the interlayer insulating layer 130 to expose source and drain regions of the semiconductor layer 115, respectively. A conductive film is stacked and patterned on the interlayer insulating layer 130 to form a source electrode 135a and a drain electrode 135b in contact with the exposed source and drain regions, respectively. The conductive film may be performed using one material selected from the group consisting of a metal film, a crystalline silicon film, and a transparent conductive film.

Referring to FIG. 1C, one of the source electrode 135a and the drain electrode 135b of the thin film transistor is selected to connect the pixel electrode 145.

The insulating layer 140 is formed on the substrate on which the layers are formed and subjected to a heat treatment process. At this time, hydrogen present in the amorphous silicon film 105 which is the first buffer layer passes through the second buffer layer, thereby forming a crystalline layer. It moves inside the silicon. Thus, defects formed inside the crystalline silicon after the crystallization process are passivated by hydrogens, and the defects are mitigated. When the first buffer layer has a thickness of 1000 GPa or more, since hydrogen is excessively introduced into the semiconductor layer during passivation and the semiconductor characteristics are deteriorated, the thickness of the first buffer layer is preferably 500 to 1000 GPa. By such a process, problems such as instability of the threshold voltage due to crystal defects in the semiconductor layer and a decrease in mobility may be improved, and a semiconductor layer having stable electrical characteristics may be provided.

After the via hole is formed in the passivation layer 140, the pixel electrode 145 is formed. Thus, the lower source electrode 135a or drain electrode 135b and the pixel electrode 145 are in contact with each other.

An insulating layer is formed on the pixel electrode 145. The insulating layer is patterned along the pixel opening region to form the pixel defining layer PDL 150. Therefore, the pixel electrode 145 is exposed below the pixel opening region.

The emission layer 155 is formed on the exposed pixel electrode 145, and the opposite electrode 160 is formed on the emission layer to form a flat panel display device. The flat panel display may be an organic light emitting display or a liquid crystal display.

When the flat panel display is an organic light emitting display, one or more organic layers may be further formed on the light emitting layer 155 in the group consisting of a hole injection layer, a hole transport layer, a hole suppression layer, and an electron injection layer. have. In addition, the counter electrode 160 becomes a cathode or an anode of the organic light emitting diode, and serves as an electrode of the organic light emitting diode together with the pixel electrode 145.

According to the present invention, a thin film transistor, a method for manufacturing the same, and a flat panel display device including the thin film transistor form a double buffer layer including an amorphous silicon film, whereby the amorphous silicon film blocks external light, thereby preventing reflection by the layers inside the flat panel display device. There is a feature to improve the contrast by preventing.

 In addition, during the heat treatment process of the source electrode and the drain electrode contact, hydrogen present in the amorphous silicon film 105 as the buffer layer is moved into the crystalline silicon to mitigate defects in the crystalline silicon. That is, even without a separate hydrogenation process used in the general LTPS process, the hydrogenation effect can be obtained due to the hydrogen present in the amorphous silicon formed in the buffer layer.

In addition, by using the amorphous silicon film as the buffer layer as described above, the black matrix forming step is not necessary, so that the process is simplified. As a result, it is possible to induce a decrease in the manufacturing cost, there is an advantage that the productivity is improved.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (16)

A substrate having a light emitting area and a non-light emitting area; A first buffer layer pattern exposing the light emitting region and formed of an amorphous silicon film and containing hydrogen; A second buffer layer positioned on the first buffer layer pattern; A semiconductor layer on the second buffer layer; And And a gate electrode on the semiconductor layer. The method of claim 1, The second buffer layer is formed of a silicon oxide film (SiO 2) or a silicon nitride film (SiN x). The method of claim 1, And a thickness of the second buffer layer is 1000 to 3000 GPa. delete The method of claim 1, The first buffer layer pattern has a thickness of 500 to 1000Å. The method of claim 1, And the semiconductor layer is formed by crystallizing an amorphous silicon film. The method of claim 1, The crystallization is a flat panel display using one method selected from the group consisting of ELA, SLS, MIC and MILC. The method of claim 1, The flat panel display device is an organic light emitting display device or a liquid crystal display device. Preparing a substrate having a light emitting area and a non-light emitting area; Forming an amorphous silicon film on the substrate to form a first buffer layer containing hydrogen; Patterning the first buffer layer to expose the light emitting region; Forming a second buffer layer on the patterned first buffer layer; Forming a thin film transistor on the second buffer layer; And And forming a pixel electrode electrically connected to the thin film transistor on the thin film transistor. The method of claim 9, The second buffer layer is formed of a silicon oxide film (SiO 2) or a silicon nitride film (SiN x). The method of claim 9, And a thickness of the second buffer layer is 1000 to 3000 GPa. The method of claim 9, And the first buffer layer is formed using a CVD method to contain hydrogen. The method of claim 9, The thickness of the first buffer layer is a manufacturing method of a flat panel display device of 500 to 1000Å. The method of claim 9, Forming the semiconductor layer on the second buffer layer; And And forming a gate electrode, a source electrode, and a drain electrode. The method of claim 14, The forming of the semiconductor layer is performed by forming and crystallizing an amorphous silicon film. The method of claim 15, Wherein the crystallization is performed using one method selected from the group consisting of ELA, SLS, MIC and MILC.

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