KR100745951B1 - Method for Forming Metal Gate - Google Patents
Method for Forming Metal Gate Download PDFInfo
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- KR100745951B1 KR100745951B1 KR1020010038027A KR20010038027A KR100745951B1 KR 100745951 B1 KR100745951 B1 KR 100745951B1 KR 1020010038027 A KR1020010038027 A KR 1020010038027A KR 20010038027 A KR20010038027 A KR 20010038027A KR 100745951 B1 KR100745951 B1 KR 100745951B1
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 41
- 239000002184 metal Substances 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 40
- 150000004767 nitrides Chemical class 0.000 claims abstract description 34
- 239000011229 interlayer Substances 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000005498 polishing Methods 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 239000010410 layer Substances 0.000 claims description 9
- 239000002002 slurry Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- -1 Ta 2 O 5 Inorganic materials 0.000 claims description 3
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims description 3
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
- H01L29/4958—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo with a multiple layer structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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Abstract
본 발명은 배리어 질화막 CMP 공정을 이용하여 길이가 0.1㎛ 이하인 게이트를 형성하는 방법에 관한 것으로 층간 절연막을 이중으로 형성함으로써 층간 절연막의 높이를 게이트의 높이만큼 높일 수 있으며, 반도체 기판 전면에 걸쳐 높은 균일도의 층간 절연막 디싱이 없는 질화막을 생성할 수 있고, 또한 후속 공정인 SAC와 호환되는 다마신 금속 게이트를 형성할 수 있는 효과가 있다.The present invention relates to a method of forming a gate having a length of 0.1 μm or less by using a barrier nitride film CMP process. By forming a double interlayer insulating film, the height of the interlayer insulating film can be increased by the height of the gate, and high uniformity is applied to the entire surface of the semiconductor substrate. It is possible to produce a nitride film without dishing of an interlayer insulating film, and to form a damascene metal gate compatible with SAC, which is a subsequent process.
다마신, 금속 게이트, 층간 절연막, 질화막 CMPDamascene, metal gate, interlayer insulating film, nitride film CMP
Description
도 1a 내지 도 1g는 종래의 다마신 금속 게이트 제조공정에 의해 제조된 반도체 소자의 단면도.1A to 1G are cross-sectional views of a semiconductor device manufactured by a conventional damascene metal gate manufacturing process.
도 2a 내지 도 22는 본 발명에 따른 금속 게이트 제조 방법에 의해 제조된 반도체 소자의 단면도.2A to 22 are cross-sectional views of a semiconductor device manufactured by a metal gate manufacturing method according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
1 : 반도체 기판 2 : 게이트 산화막1 semiconductor substrate 2 gate oxide film
3 : 폴리실리콘막 4 : 측벽 스페이서3: polysilicon film 4: sidewall spacer
5 : 소오스/드레인 영역 6 : 제1 층간 절연막5 source / drain
7 : 게이트 절연막 8 : 금속층7: gate insulating film 8: metal layer
8-1 : 게이트 금속 9 : 배리어 질화막8-1: gate metal 9: barrier nitride film
60 : 제2 층간 절연막 90 : 질화막60: second interlayer insulating film 90: nitride film
본 발명은 반도체 소자의 금속 게이트를 형성하는 방법에 관한 것으로서, 특히 배리어 질화막 CMP 공정을 이용하여 길이가 0.1㎛ 이하인 게이트를 형성하는 방 법에 관한 것이다.The present invention relates to a method of forming a metal gate of a semiconductor device, and more particularly, to a method of forming a gate having a length of 0.1 μm or less using a barrier nitride film CMP process.
종래의 반도체 소자에는 폴리실리콘 전극이나 폴리 실리사이드 게이트 전극이 이용되어 왔으나, 길이가 0.1㎛이하인 게이트 전극을 가지는 반도체 소자에서는 폴리실리콘 전극 등으로는 저저항값을 구현할 수 없다는 문제점이 있었다. 이러한 문제로 인하여 최근에는 금속 게이트 전극이 사용되고 있는데 금속 게이트 전극을 패터닝한 후 소오스/드레인 영역을 형성하는 종래의 공정은 금속 게이트 전극 식각의 어려움, 식각 및 이온 주입 과정에서의 플라즈마 손상, 소오스/드레인 형성을 위한 후속 열공정에 의한 열적 손상 등의 문제점이 있다. 이러한 문제점을 해결하기 위해 새로운 구조의 금속 전극 제조공정인 다마신 금속 게이트 제조 방법이 제안되었는데, 이러한 다마신 금속 게이트 제조공정에 의해 제조된 반도체 소자의 단면도를 도시한 도 1a 내지 도 1g를 참조하여 설명한다.Although a polysilicon electrode or a polysilicide gate electrode has been used in a conventional semiconductor device, there has been a problem in that a low resistance value cannot be realized using a polysilicon electrode in a semiconductor device having a gate electrode having a length of 0.1 μm or less. Due to these problems, metal gate electrodes have recently been used. Conventional processes for forming the source / drain regions after patterning the metal gate electrodes include difficulty in etching metal gate electrodes, plasma damage during etching and ion implantation, and source / drain. There is a problem such as thermal damage by the subsequent thermal process for formation. In order to solve this problem, a method of manufacturing a damascene metal gate, which is a metal electrode manufacturing process having a new structure, has been proposed. Referring to FIGS. Explain.
도 1a 내지 도 1g를 참조하면, 반도체 기판(1) 상에 게이트 산화막(2)을 형성한 후, 폴리실리콘막(3)을 증착하여 패터닝한다. 게이트 산화막(2)은 SiO2, Al2O3, Ta2O5, ZrO2 및 이들의 조합 중 선택된 어느 하나로 형성하는 것이 바람직하다. 그 다음에 LDD 구조의 트랜지스터를 형성하기 위해 이온 주입 공정과 측벽 스페이서(4)형성 공정 및 소오스/드레인 영역(5)의 도펀트를 활성화시키기 위해 열공정을 수행한 후 제1 층간 절연막(6)을 형성한다(도 1a 참조). 제1 층간 절연막(6)을 CMP 공정에 의해 연마하여 폴리실리콘막(3)의 표면을 노출시킨 후 선택적 식각공정에 의해 폴리실리콘막(3) 및 실리콘산화막(2)을 제거한다(도 1b 및 도 1c 참조). 다음에는, 게이트 절연막(7) 및 금속층(8)을 순차적으로 형성(도 1d 참조)하고 제1 층간 절연막(6) 상부에 존재하는 게이트 절연막(7) 및 금속층(8)을 CMP 공정에 의해 제거한다(도 1e 참조). 금속층(8)은 텅스텐으로 형성하는 것이 바람직하며 게이트 절연막(7)은 SiO2, Al2O3, Ta2O5, ZrO2 및 이들의 조합 중 선택된 어느 하나로 형성하는 것이 바람직하다. 게이트 금속(8-1)을 부분적으로 식각(도 1f 참조)하여 질화막을 증착하고 CMP 공정 처리하여 후속 SAC 공정에 대한 배리어 질화막(9)을 형성한다(도 1g 참조).1A to 1G, after forming the gate oxide film 2 on the semiconductor substrate 1, the polysilicon film 3 is deposited and patterned. The gate oxide film 2 is preferably formed of any one selected from SiO 2 , Al 2 O 3 , Ta 2 O 5 , ZrO 2, and a combination thereof. Then, the first
금속 게이트 형성 후에 후속 공정인 SAC 공정을 위해 배리어 질화막이 필수적인데, 다마신 금속 게이트 제조공정에서 질화막을 CMP 처리하는 경우 통상의 슬러리를 가지고 행하게 되면, 산화물의 디싱(dishing)이 발생하게 되는데, 이러한 ILD 손실은 후속하는 포토 또는 식각공정에 좋지 않은 영향을 주게되어 CMP 공정을 이용한 배리어 질화막 형성이 거의 불가능하다는 문제점이 있었다.The barrier nitride film is essential for the SAC process, which is a subsequent process after the metal gate is formed. When the CMP process of the nitride film is performed in the damascene metal gate manufacturing process, when a conventional slurry is performed with a conventional slurry, the dishing of the oxide occurs. ILD loss has a bad effect on the subsequent photo or etching process has a problem that it is almost impossible to form a barrier nitride film using the CMP process.
본 발명은 상기 문제점을 해결하기 위해 통상의 슬러리로 CMP공정을 수행하여 ILD 상의 질화막을 모두 제거하고 새로운 ILD를 추가적으로 증착한 후 질화막에 대해 높은 선택비를 갖는 STI용 고선택비 슬러리를 수행함으로써 층간 절연막의 높이를 게이트의 높이만큼 높일 수 있으며, 반도체 기판 전면에 걸쳐 높은 균일도의 층간 절연막 디싱이 없는 질화막을 생성하는 것을 그 목적으로 한다.The present invention is to solve the above problems by performing a CMP process with a conventional slurry to remove all of the nitride film on the ILD and additional deposition of a new ILD after performing a high selectivity slurry for STI having a high selectivity for the interlayer by interlayer The height of the insulating film can be increased by the height of the gate, and an object thereof is to produce a nitride film having no uniform interlayer insulating film dishing over the entire semiconductor substrate.
본 발명에 따른 금속 게이트 제조 방법은 반도체 기판 상에 제1 게이트 절연 막 및 폴리실리콘막의 적층 구조로 된 게이트 전극을 형성하는 단계와, 상기 게이트 전극의 측벽에 절연막 스페이서를 형성하는 단계와, 상기 게이트 전극의 양측의 반도체 기판에 소오스/드레인 영역을 형성하는 단계와, 상기 반도체 기판 전면에 제1 층간 절연막을 형성하는 단계와, 상기 폴리실리콘막의 표면이 노출되도록 상기 제1 층간 절연막을 연마하는 단계와, 상기 폴리실리콘막 및 제1 게이트 절연막을 제거하는 단계와, 상기 반도체 기판 전면에 균일한 두께의 제2 게이트 절연막을 형성하는 단계와, 상기 반도체 기판 전면에 금속층을 형성하는 단계와, 상기 제1 층간 절연막이 노출되도록 상기 제2 게이트 절연막 및 금속층을 연마하여 게이트 금속을 형성하는 단계와, 상기 제1 게이트 절연막 및 게이트 금속을 소정의 깊이만큼 식각하는 단계와, 반도체 기판 전면에 질화막을 형성하는 단계와, 상기 질화막 및 제1 층간 절연막을 연마하는 단계와, 상기 반도체 기판 전면에 제2 층간 절연막을 형성하는 단계 및 상기 질화막이 노출되도록 상기 제2 층간 절연막을 연마하는 단계를 포함하는 것을 그 특징으로 한다.The metal gate manufacturing method according to the present invention comprises the steps of forming a gate electrode having a laminated structure of a first gate insulating film and a polysilicon film on a semiconductor substrate, forming an insulating film spacer on the sidewall of the gate electrode, Forming a source / drain region in the semiconductor substrate on both sides of the electrode, forming a first interlayer insulating film on the entire surface of the semiconductor substrate, and polishing the first interlayer insulating film to expose the surface of the polysilicon film; Removing the polysilicon film and the first gate insulating film, forming a second gate insulating film having a uniform thickness on the entire surface of the semiconductor substrate, forming a metal layer on the entire surface of the semiconductor substrate, and Polishing the second gate insulating film and the metal layer to expose the interlayer insulating film to form a gate metal; Etching the first gate insulating film and the gate metal to a predetermined depth, forming a nitride film on the entire surface of the semiconductor substrate, polishing the nitride film and the first interlayer insulating film, and forming a second interlayer on the entire surface of the semiconductor substrate. And forming an insulating film and polishing the second interlayer insulating film so that the nitride film is exposed.
이하에서는 본 발명의 실시예를 첨부한 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.
도 2a 내지 도 2e는 본 발명에 따른 다마신 금속 게이트 형성 방법에 의해 제조된 반도체 소자를 도시한 단면도이다. 도 2a 내지 도 2e를 참조하면, 도 1a 내지 도 1f의 공정을 수행한 후(도 2a 참조)에 질화막(90)을 증착한다(도 2b 참조). 여기서 게이트 금속(8-1)은 약 500 내지 1200Å 정도 식각하는 것이 바람직하며 질화막(90)은 약 1500 내지 3000Å의 두께로 형성하는 것이 바람직하다. 또한 질화막(90)은 열 CVD(thermal CVD)법 또는 플라즈마 인핸스드 CVD(plasma enhanced CVD)법을 이용하여 증착할 수 있다. 그 다음에 통상의 슬러리를 이용하여 질화막(90)을 연마한다(도 2c 참조). 연마 속도는 약 1000 내지 2000Å으로 하는 것이 바람직하다. 이 때 산화물의 연마 속도가 질화막의 연마 속도보다 빠르므로 층간 절연막 산화물 디싱이 발생하게 된다. 다음에는, 바람직하게는 1000 내지 3500Å의 두께로 제2 층간 절연막(60)을 증착(도 2d 참조)하고 질화막에 대해 선택비를 갖는 고선택비 슬러리를 이용하여 질화막 정지 CMP(nitride stop CMP)를 수행한다(도 2e 참조). 이 경우 층간 절연막과 질화막의 연마 선택비는 20 이상인 것이 바람직하며, 슬러리는 pH 3 내지 11의 세리아를 포함하는 것이 바람직하다.2A through 2E are cross-sectional views illustrating semiconductor devices manufactured by the damascene metal gate forming method according to the present invention. 2A to 2E, the
이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 금속 게이트 제조 방법은 층간 절연막의 높이를 게이트의 높이만큼 높일 수 있으며, 반도체 기판 전면에 걸쳐 높은 균일도의 층간 절연막 디싱이 없는 질화막을 생성할 수 있으며, 또한 후속 공정인 SAC와 호환되는 다마신 금속 게이트를 형성할 수 있다는 이점이 있다.As described above, the metal gate manufacturing method of the semiconductor device according to the present invention can increase the height of the interlayer insulating film by the height of the gate, and can produce a nitride film having no uniform interlayer insulating film dishing over the entire semiconductor substrate. In addition, there is an advantage in that it is possible to form a damascene metal gate compatible with the SAC, which is a subsequent process.
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US9337293B2 (en) | 2013-02-22 | 2016-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having electrode and manufacturing method thereof |
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