KR100444301B1 - Damascene Metal Gate formation Process using Nitride CMP - Google Patents
Damascene Metal Gate formation Process using Nitride CMP Download PDFInfo
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- KR100444301B1 KR100444301B1 KR10-2001-0088185A KR20010088185A KR100444301B1 KR 100444301 B1 KR100444301 B1 KR 100444301B1 KR 20010088185 A KR20010088185 A KR 20010088185A KR 100444301 B1 KR100444301 B1 KR 100444301B1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
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- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/3105—After-treatment
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
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- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
Abstract
본 발명은 질화막 화학적 물리적 연마 (Chemical Mechanical Polishing; 이하“CMP”라 칭함) 공정을 이용하여 다마신 금속 게이트를 형성하는 방법에 관한 것으로, 보다 상세하게는 식각 방지막인 질화막에 대하여 CMP를 실시할 때, CMP용 슬러리의 pH를 산화막에 대하여 선택비를 가지도록 변화시켜, 층간 절연막 (Inter Layer Dielectrics)의 손실 없이 질화막을 식각하는 다마신 금속 게이트 형성 방법에 관한 것이다.The present invention relates to a method of forming a damascene metal gate using a chemical mechanical polishing (hereinafter referred to as "CMP") process, and more particularly, when CMP is performed on a nitride film that is an etch stopper. The present invention relates to a method for forming a damascene metal gate in which a pH of a slurry for CMP is changed to have a selectivity with respect to an oxide film, and the nitride film is etched without loss of inter layer dielectrics.
본 발명의 질화막용 CMP를 이용한 다마신 금속 게이트 형성방법에 따르면, 후속 SAC (Self Aligns Contact) 공정을 위한 다마신 금속 게이트 제조를 위한 식각 방지막을 적절하게 형성할 수 있을 뿐만 아니라, 실제 소자 공정에 다마신 금속 게이트를 도입하여 게이트 길이가 0.1㎛ 이하인 고성능의 트랜지스터를 제조할 수 있다.According to the method for forming a damascene metal gate using the CMP for the nitride film of the present invention, it is possible not only to properly form an etch stop layer for manufacturing the damascene metal gate for a subsequent self alignment contacts, but also to the actual device process. By introducing a damascene metal gate, a high-performance transistor having a gate length of 0.1 μm or less can be manufactured.
Description
본 발명은 질화막 화학적 물리적 연마 (Chemical Mechanical Polishing; 이하“CMP”라 칭함) 공정을 이용하여 다마신 금속 게이트를 형성하는 방법에 관한 것으로, 보다 상세하게는 식각 방지막인 질화막에 대하여 CMP를 실시할 때, CMP용 슬러리의 pH를 산화막에 대하여 선택비를 가지도록 변화시켜, 층간 절연막 (Inter Layer Dielectrics)의 손실 없이 질화막을 식각하는 다마신 금속 게이트 형성 방법에 관한 것이다.The present invention relates to a method of forming a damascene metal gate using a chemical mechanical polishing (hereinafter referred to as "CMP") process, and more particularly, when CMP is performed on a nitride film that is an etch stopper. The present invention relates to a method for forming a damascene metal gate in which a pH of a slurry for CMP is changed to have a selectivity with respect to an oxide film, and the nitride film is etched without loss of inter layer dielectrics.
종래 게이트 길이가 0.10㎛인 반도체 소자에서는 기존의 폴리 실리콘 (Si) 게이트 전극이나, 폴리 실리사이드 (Metal-Six) 게이트 전극으로는 미세 선폭 상에서 낮은 저항값을 얻을 수 없으므로, 이를 대체할 수 있는 새로운 물질과 새로운 구조를 가지는 금속 게이트 전극의 개발이 적극적으로 추진되고 있다.In the semiconductor device having a gate length of 0.10 μm, a low resistance value on a fine line width cannot be obtained with a conventional polysilicon (Si) gate electrode or a polysilicide (Metal-Si x ) gate electrode. The development of metal gate electrodes with materials and new structures is being actively promoted.
그러나, 종래 방법으로 트랜지스터를 제조하는 과정, 즉, 금속 게이트 전극을 패터닝 한 후 소오스 (Source) / 드레인 (Drain)을 형성하는 과정은 공정 과정과 소자의 특성으로 인해 많은 문제점들이 발생된다. 이러한 문제점들을 예를 들면 i) 금속 게이트 전극을 식각하는 것이 어렵고, ii) 식각 및 이온 주입 공정에서 플라즈마에 의하여 손상을 받으며, iii) 소오스/드레인을 형성하기 위한 후속 열 공정에서 열적 손상을 입는다는 것이다.However, a process of manufacturing a transistor by a conventional method, that is, a process of forming a source / drain after patterning a metal gate electrode, causes many problems due to the process and characteristics of the device. These problems are for example i) difficult to etch metal gate electrodes, ii) damaged by plasma in etching and ion implantation processes, and iii) thermally damaged in subsequent thermal processes to form sources / drains. will be.
이러한 문제점을 해결하는 위하여 제시된 것이 새로운 구조의 금속 전극을 제조할 수 있는 다마신 금속 게이트 제조공정이다.In order to solve this problem, a damascene metal gate manufacturing process capable of manufacturing a metal electrode having a new structure is proposed.
상기 다마신 금속 게이트 제조공정은 게이트 길이가 0.1㎛ 이하에서 고성능의 트랜지스터를 제조하기 위한 것으로 희생막을 (Dummy Poly-Silicon gate)을 형성하여 트랜지스터를 제조하고, 다시 희생막을 제거한 후 금속 게이트 전극을 형성하는 것이다.The damascene metal gate manufacturing process is for manufacturing a high performance transistor having a gate length of 0.1 μm or less, forming a sacrificial film (Dummy Poly-Silicon gate) to form a transistor, and then removing the sacrificial film to form a metal gate electrode. It is.
상기 공정을 구체적으로 설명하면The process is described in detail
실리콘 기판 (1)에 게이트 절연막으로 버퍼층 (SiO2)(5)을 형성한 후, 희생막 (7)을 증착하여 패터닝한다. 그 후 엘디디 (Lightly Doped Drain; 이하“LDD”라 칭함) 구조의 트랜지스터를 형성하기 위해 이온 주입 공정과 측벽 질화막 스페이서 (Spacer) (9) 형성 공정 및 소오스/드레인 (3)의 불순물 (Dopant)을 활성화 시키기 위한 열공정을 수행한 후 산화막인 층간 절연막 (11)을 증착한다 (도 1a참조).After the buffer layer (SiO 2 ) 5 is formed on the silicon substrate 1 with the gate insulating film, the sacrificial film 7 is deposited and patterned. Thereafter, an ion implantation process, a sidewall nitride film spacer (9) forming process, and a source / drain (3) dopant are formed to form a transistor having a lightly doped drain (LDD) structure. After performing a thermal process for activating the film, an interlayer insulating film 11 which is an oxide film is deposited (see FIG. 1A).
그리고, CMP로 층간 절연막 (11)을 연마하여 희생막 (7) 표면을 노출시키고 (도 1b참조), 선택적 식각 방식으로 희생막 (7)과 버퍼층 (5)을 제거한 다음 (도 1c참조), 게이트 절연막 (13)과 금속 게이트 (15)인 텅스텐 (W)을 증착한다 (도 1d참조). 그 다음에, 층간 절연막 (11) 상부에 존재하는 텅스텐 (15)과 게이트 절연막 (13)을 CMP 처리하여 다마신 금속 게이트 전극을 형성한 후 (도 1e참조), 후속 SAC (Self Aligns Contact) 공정에 대한 절연막 층을 형성하기 위하여 텅스텐 (15)을 부분 산화시켜 텅스텐 산화막 (WO3) (17)을 형성하거나 (도 1f참조), 텅스텐 (15)을 부분 식각하여 질화막을 증착하고 CMP 처리하여 질화막 층 (19)을 형성한다 (도 1g참조).Then, the interlayer insulating film 11 is polished with CMP to expose the surface of the sacrificial film 7 (see FIG. 1B), and the sacrificial film 7 and the buffer layer 5 are removed by a selective etching method (see FIG. 1C). Tungsten (W), which is the gate insulating film 13 and the metal gate 15, is deposited (see FIG. 1D). Then, the tungsten 15 and the gate insulating film 13 present on the interlayer insulating film 11 are CMP-treated to form a damascene metal gate electrode (see FIG. 1E), followed by a subsequent Self Aligns Contact (SAC) process. Tungsten 15 is partially oxidized to form a tungsten oxide film (WO 3 ) 17 (see FIG. 1F) in order to form an insulating film layer for the insulating film (see FIG. 1F), or the nitride film is deposited by partially etching tungsten 15 and a CMP process is performed to form a nitride film. Form layer 19 (see FIG. 1G).
그러나, 상기와 같은 다마신 금속 게이트 제조 공정은 텅스텐 산화막을 형성하는 경우 열적 손상과 측벽의 질화막 스페이서 (9)가 함께 산화될 뿐만 아니라, 텅스텐 산화막이 후속 SAC 공정에서 절연막 층으로 작용하는 것이 거의 불가능한 단점이 있다.However, the damascene metal gate fabrication process as described above not only oxidizes the thermal damage and the nitride spacer 9 of the sidewall together when forming the tungsten oxide film, but also makes it almost impossible for the tungsten oxide film to act as an insulating film layer in a subsequent SAC process. There are disadvantages.
또한, 층간 절연막 (11)이 산화막으로 패터닝 된 상태에서 절연막으로 질화막 (19)을 형성하여 부분 식각, CMP 하는 경우에 마스크/식각 단계가 추가되어 복잡해질 뿐만 아니라, 종래의 슬러리로는 산화막이 질화막 보다 빨리 연마되므로, 도 1h에 도시한 바와 같이 산화막의 디싱 (Dishing) 현상 (21)이 심하게 발생되어 후속 현상 공정이나 식각 공정 및 SAC 공정에 좋지 않은 영향을 준다.In addition, in the case where the interlayer insulating film 11 is patterned with an oxide film, the nitride film 19 is formed with an insulating film, and in the case of partial etching and CMP, a mask / etching step is added, and the oxide film is a nitride film. Since it is polished faster, the dishing phenomenon 21 of the oxide film is severely generated as shown in FIG. 1H, which adversely affects the subsequent developing process, etching process and SAC process.
이에 본 발명자들은 상기와 같은 층간 절연막인 산화막이 디싱되는 단점을 극복하기 위한 연구를 하던 중 층간 절연막의 손상 없이 질화막을 식각 할 수 있는 방법을 개발하여 본 발명을 완성하였다.Accordingly, the present inventors have completed the present invention by developing a method for etching the nitride film without damaging the interlayer insulating film while researching to overcome the disadvantage of dishing the oxide film as the interlayer insulating film as described above.
본 발명의 목적은 다마신 금속 게이트 제조 공정에 있어서, 층간 절연막의 손실 없이 질화막을 식각하여, 후속 플러그 콘택 식각 (Plug Contact Etch) 제조 공정에서 적절한 다마신 금속 게이트를 형성하는 것을 목적으로 한다.An object of the present invention is to form a damascene metal gate in a process for producing a damascene metal by etching a nitride film without loss of an interlayer insulating film in a subsequent process of manufacturing a plug contact etch.
도 1a 내지 1h는 종래 금속 다마신 게이트를 제조하는 공정 개요도.1A-1H are schematic views of a process for fabricating a conventional metal damascene gate.
도 2a 내지 2g는 본 발명의 금속 다마신 게이트를 제조하는 공정 개요도.2A-2G are schematic views of the process for making the metal damascene gate of the present invention.
도 3은 본 발명으로 제조한 SAC 공정에 적절한 다마신 금속 게이트를 형성한 사진.Figure 3 is a photograph of the damascene metal gate formed suitable for the SAC process prepared by the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
1, 101 : 실리콘 기판 3, 103 : 소오스/드레인1, 101: silicon substrate 3, 103: source / drain
5, 105 : 버퍼층 7, 107 : 희생막5, 105: buffer layer 7, 107: sacrificial film
9, 109 : 스페이서 11, 111 : 층간 절연막9, 109: spacer 11, 111: interlayer insulating film
13, 113 : 게이트 절연막 15, 115 : 금속 게이트 전극13, 113: gate insulating film 15, 115: metal gate electrode
17, 117 : 금속 (텅스텐) 산화막 (WO3) 19, 119 : 질화막17, 117: metal (tungsten) oxide film (WO 3 ) 19, 119: nitride film
21 : 디싱21: dishing
상기 목적을 달성하기 위하여 본 발명에서는 슬러리가 산화막에 대하여 선택비를 가지도록 슬러리의 pH를 변화시킨 질화막 CMP용 슬러리와 이를 이용한 다마신 금속 게이트 형성 방법을 제공한다.In order to achieve the above object, the present invention provides a slurry for nitride film CMP in which the pH of the slurry is changed so that the slurry has a selectivity with respect to the oxide film, and a method for forming a damascene metal gate using the same.
이하 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail.
본 발명은The present invention
실리콘 기판에 버퍼층을 형성하는 단계;Forming a buffer layer on the silicon substrate;
상기 버퍼층 상부의 게이트 전극이 될 부분에 희생막 패턴을 형성하는 단계;Forming a sacrificial layer pattern on a portion of the buffer layer to be a gate electrode;
희생막 측벽에 스페이서를 형성하는 단계;Forming a spacer on the sacrificial layer sidewalls;
상기 구조의 전 표면에 층간 절연막을 증착하는 단계;Depositing an interlayer insulating film over the entire surface of the structure;
CMP로 상기 층간 절연막을 연마하여 희생막을 노출시키는 단계;Polishing the interlayer insulating film with CMP to expose the sacrificial film;
노출된 희생막과 게이트 산화막을 제거하는 단계;Removing the exposed sacrificial film and the gate oxide film;
상기 구조의 전 표면에 게이트 절연막과 금속층을 증착하는 단계;Depositing a gate insulating film and a metal layer on the entire surface of the structure;
상기 게이트 절연막과 금속층을 평탄화 식각하여 층간 절연막 상부를 노출시키는 단계;Planarization etching the gate insulating film and the metal layer to expose an upper portion of the interlayer insulating film;
상기 층간 절연막을 식각 정지층으로 금속층을 과도 식각하여 리세스 시키는 단계;Over-etching and recessing the metal layer using the interlayer insulating layer as an etch stop layer;
상기 구조의 전 표면에 질화막을 증착하는 단계;Depositing a nitride film on the entire surface of the structure;
(질화막/산화막)>1의 식각 선택비를 갖는 슬러리를 이용하여 상기 질화막을 CMP 공정으로 연마하는 단계를 포함하는 다마신 금속 게이트 형성방법을 제공한다.It provides a damascene metal gate forming method comprising polishing the nitride film by a CMP process using a slurry having an etching selectivity of (nitride film / oxide film)> 1.
본 발명의 단계를 상세히 설명하면 우선, 실리콘 기판 (101)에 게이트 절연막으로 버퍼층 (SiO2) (105)을 형성한 후, 그 상부에 희생막 (107)을 형성한 후, LDD 구조의 트랜지스터를 형성하기 위해 이온 주입 공정과 희생막 (107)의 측벽에스페이서 (109)를 형성한다. 이 후 소오스/드레인 (103)의 불순물을 열공정으로 활성화 시킨 다음, 산화막인 층간 절연막 (111)을 증착한다 (도 2a참조).Referring to the steps of the present invention in detail, first, after forming a buffer layer (SiO 2 ) 105 on the silicon substrate 101 as a gate insulating film, and then forming a sacrificial film 107 on top of the transistor, the transistor of the LDD structure The spacer 109 is formed on the sidewall of the ion implantation process and the sacrificial film 107 to form. Thereafter, the impurities of the source / drain 103 are activated by a thermal process, and then an interlayer insulating film 111 that is an oxide film is deposited (see FIG. 2A).
또한, CMP로 상기 층간 절연막 (111)을 연마하여 희생막 (107)을 노출시킨 후 (도 2b참조), 노출된 희생막과 버퍼층 (105)을 제거한다 (도 2c참조).Further, after the interlayer insulating film 111 is polished with CMP to expose the sacrificial film 107 (see FIG. 2B), the exposed sacrificial film and the buffer layer 105 are removed (see FIG. 2C).
또한, 상기 구조의 전 표면에 게이트 절연막 (113)과 금속층 (115)을 증착한다 (도 2d참조). 이때 금속층은 텅스텐 (W), 티타늄나이트라이드 (TiN), 몰리부덴 (Mo) 및 코발트 (Co)를 사용하여 증착한다.Further, a gate insulating film 113 and a metal layer 115 are deposited on the entire surface of the structure (see FIG. 2D). The metal layer is deposited using tungsten (W), titanium nitride (TiN), molybdenum (Mo) and cobalt (Co).
그 후, 게이트 절연막 (113)과 금속층 (115)을 평탄화 식각한 후, 층간 절연막 (111)을 식각 방지막으로 하여 상기 게이트 절연막 (113)과 금속층 (115)을 CMP 공정으로 과도 식각하여 리세스 시키고 (도 2e참조), 상기 구조의 전 표면에 질화막 (119)을 1500∼3000Å의 두께로 화학기상 증착법 (chemical vapor deposition) 또는 피이-화학기상 증착법 (plasma enhanced chemical vapor deposition)을 이용하여 증착한다 (도 2f참조). 이때, 질화막은 실리콘질화막 (SiN) 및 산화질화막 (SiON) 중에서 사용하는 것이 바람직하다.After the planar etching of the gate insulating film 113 and the metal layer 115, the gate insulating film 113 and the metal layer 115 are excessively etched and recessed by the CMP process using the interlayer insulating film 111 as an etch stop layer. (See FIG. 2E), the nitride film 119 is deposited on the entire surface of the structure by chemical vapor deposition or plasma enhanced chemical vapor deposition at a thickness of 1500 to 3000 mm 3 ( 2f). At this time, the nitride film is preferably used in the silicon nitride film (SiN) and oxynitride film (SiON).
그 후, 산화막에 대한 질화막의 식각 선택비가 우수한 역 선택비를 갖는 슬러리를 사용하여, 연마속도 1000∼2000Å/s으로 CMP 공정을 실시하면, 산화막이 식각되는 것은 방지되고, 질화막 (119)만 연마되어 평탄화가 이루어지므로 (도 2g참조) SAC에 적절한 다마신 금속 게이트가 형성된다 (도 3 참조).Subsequently, when the CMP process is performed at a polishing rate of 1000 to 2000 Pa / s using a slurry having an inverse selectivity of the nitride film to the oxide film, the oxide film is prevented from being etched, and only the nitride film 119 is polished. And planarization is performed (see FIG. 2G), so that a suitable damascene metal gate is formed in the SAC (see FIG. 3).
이때, 질화막용 슬러리의 연마 선택비는 2∼20인 것이 바람직하고, 상기 슬러리는 연마제 및 인산을 포함한 것을 사용한다.At this time, it is preferable that the polishing selectivity of the slurry for nitride films is 2-20, and the slurry uses the thing containing an abrasive and phosphoric acid.
또한, 상기 슬러리는 산화막에 비해 질화막이 빠른 식각 속도를 갖도록 하기 위하여 내부에 질산 (HNO3) 및 불산 (HF), 바람직하게는 인산 (H2PO4)을 첨가하여 pH가 1∼5가 되도록 하는데, 이때, pH는 히드록실기(-OH)를 갖는 완충 용액을 사용하여 조절할 수 있다.In addition, the slurry is added with nitric acid (HNO 3 ) and hydrofluoric acid (HF), preferably phosphoric acid (H 2 PO 4 ) in order to have a faster etching rate than the oxide film so that the pH is 1 to 5 In this case, the pH can be adjusted using a buffer solution having a hydroxyl group (-OH).
또한, 슬러리에 첨가되는 연마제는 산화 산화 세슘 연마제 (Ceria Abrasive; CeO2)가 첨가된 것이나, 산화망간 (MnO2), 지르코니아 (ZrO2), 알루미나 (Al2O3) 또는 실리카 (SiO2) 등을 포함하는 것이면 어느 것이나 사용 가능하며, 질화막의 종류에 따라 적절하게 선택할 수 있다.In addition, the abrasive added to the slurry is a cesium oxide abrasive (Ceria Abrasive; CeO 2 ) added, but manganese oxide (MnO 2 ), zirconia (ZrO 2 ), alumina (Al 2 O 3 ) or silica (SiO 2 ) Any of these may be used as long as it contains a material, and the like can be appropriately selected depending on the type of nitride film.
상기 연마제의 입자 크기는 일반적으로 100nm∼500nm의 크기이고, 슬러리 총 중량에 대해 0.1∼20 wt%를 포함하며, 콜로이드 (Colloidal) 형태 또는 퓸드 (Fumed) 형태로 제조 하는 것이 바람직하다.The particle size of the abrasive is generally 100nm to 500nm, 0.1 to 20% by weight based on the total weight of the slurry, it is preferable to prepare in the colloidal (Colloidal) form or fumed (Fumed) form.
이상에서 살펴본 바와 같이, 본 발명은 질화막 CMP를 이용한 다마신 금속 게이트 형성방법을 제공하여, 후속 SAC 공정을 위한 다마신 금속 게이트 제조 시에 문제가 되던 질화막 층을 층간 절연막의 손실 없이 형성할 수 있을 뿐만 아니라, 실제 소자 공정에 다마신 금속 게이트를 도입하여, 게이트 길이가 0.1㎛ 이하인 고성능의 트랜지스터를 제조할 수 있다.As described above, the present invention provides a method for forming a damascene metal gate using a nitride film CMP, so that a nitride layer, which is a problem in manufacturing a damascene metal gate for a subsequent SAC process, can be formed without loss of an interlayer insulating film. In addition, a damascene metal gate may be introduced into an actual device process to manufacture a high performance transistor having a gate length of 0.1 μm or less.
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| KR19990007474A (en) * | 1997-06-30 | 1999-01-25 | 니시무로 다이조 | Semiconductor device and manufacturing method thereof |
| US6251786B1 (en) * | 1999-09-07 | 2001-06-26 | Chartered Semiconductor Manufacturing Ltd. | Method to create a copper dual damascene structure with less dishing and erosion |
| KR20010088287A (en) * | 2000-03-09 | 2001-09-26 | 윤종용 | Method of forming a self-aligned contact pad in a damascene gate process |
| KR20010105866A (en) * | 2000-05-19 | 2001-11-29 | 박종섭 | Method for forming gate of semiconductor device by using polishing selectivity difference between polymer and oxide layer |
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| KR19990007474A (en) * | 1997-06-30 | 1999-01-25 | 니시무로 다이조 | Semiconductor device and manufacturing method thereof |
| US6251786B1 (en) * | 1999-09-07 | 2001-06-26 | Chartered Semiconductor Manufacturing Ltd. | Method to create a copper dual damascene structure with less dishing and erosion |
| KR20010088287A (en) * | 2000-03-09 | 2001-09-26 | 윤종용 | Method of forming a self-aligned contact pad in a damascene gate process |
| KR20010105866A (en) * | 2000-05-19 | 2001-11-29 | 박종섭 | Method for forming gate of semiconductor device by using polishing selectivity difference between polymer and oxide layer |
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| US9941283B2 (en) | 2015-06-18 | 2018-04-10 | Samsung Electronics Co., Ltd. | Semiconductor device having fin-type pattern |
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