KR100739049B1 - Plasma display panel device - Google Patents

Abstract

The present invention relates to a plasma display panel device. According to the present invention, a ground voltage is applied to the address electrode through a switch connected to the ground terminal of the chassis base in a section other than the address section. In this way, a stable ground voltage can be supplied and the ground switch of the address selection circuit is turned off in a section other than the address section, so that the IC is not damaged even if the driving switch of the address selection circuit is turned on due to noise. You can prevent it.

PDP, address, ground voltage, integrated circuit

Description

Plasma Display Panel Device {PLASMA DISPLAY PANEL DEVICE}

1 is a partial perspective view of an AC plasma display panel.

2 shows an electrode arrangement diagram of the plasma display panel.

3 is a diagram illustrating a path of a current in which a ground voltage is applied to an address electrode in a section other than an address section in a conventional address driving circuit.

4 is an exploded perspective view of a plasma display panel according to an embodiment of the present invention.

5 is a schematic plan view of a chassis base according to an embodiment of the present invention.

6 is a diagram illustrating an address driving circuit according to an exemplary embodiment of the present invention.

7 is a diagram illustrating a path of a current in which a ground voltage is applied to an address electrode in a section other than an address section in an address driving circuit according to an exemplary embodiment of the present invention.

The present invention relates to a plasma display panel (PDP), and more particularly to an address driving circuit for applying an addressing voltage.

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.

In the DC plasma display panel, the discharge space of the electrode is exposed without being insulated, so that the current flows in the discharge space while the voltage is applied, and there is a disadvantage in that a resistor for limiting the current must be inserted. On the other hand, an AC plasma display panel has an advantage that the current is limited by the formation of a capacitance component because the dielectric layer covers the electrode, and the service life is longer than that of the direct current type because the electrode is protected from the impact of ions during discharge.

1 is a partial perspective view of an AC plasma display panel.

As shown in FIG. 1, a scan electrode 4 and a sustain electrode 5 covered with a dielectric layer 2 and a protective film 3 are arranged in parallel on the glass substrate 1 (the lower side in FIG. 1). do. On the glass substrate 6, a plurality of address electrodes 8 covered with the insulator layer 7 are provided. The partition 9 is formed on the insulator layer 7 between the adjacent address electrodes 8 in parallel with the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both side surfaces of the partition wall 9. The glass substrates 1 and 6 are disposed to face the discharge electrode 11 so that the address electrode 8 is orthogonal to the scan electrode 4 and the sustain electrode 5. The discharge space at the intersection of the scan electrode 4 and the sustain electrode 5 paired with the address electrode 8 forms the discharge cell 12.

2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 2, the electrodes of the plasma display panel have a matrix form of n × m. Specifically, the address electrodes A ₁ to A _m extend in the column direction and the scan electrode Y in the row direction. _{1 to} Y _n and the sustain electrodes X _{1 to} X _n extend. The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG.

In general, the driving method of the AC plasma display panel includes a reset period, an addressing period, a sustain period, and an erase period.

The reset period is a period of initializing the state of each cell in order to perform an addressing operation smoothly on the cell, and the addressing period is a wall charge on a cell (addressed cell) that is turned on to distinguish cells that are turned on and cells that are not turned on. This is the period during which the stacking operation is performed. The sustain period is a period in which a discharge for actually displaying an image is performed on the addressed cell by applying a sustain discharge voltage pulse, and the erasing period is a period in which the sustain discharge is terminated by reducing the wall charge of the cell.

When performing each of these operations, the discharge space between the scan electrode and the sustain electrode, the surface on which the address electrode is formed, and the surface on which the scan and sustain electrode are formed, etc. act as a capacitive load (hereinafter referred to as a "panel capacitor"). There is capacitance in the panel. Therefore, in order to apply the waveform for addressing, there is a large amount of reactive power for charge injection that generates a predetermined voltage in capacitance in addition to the power for address discharge. When the power consumption is high, the load of the driving IC of the address electrode is increased and heat generation can be increased, thereby destroying the driving IC. Thus, a power recovery circuit for recovering and reusing reactive power is generally used for the address driving IC. As such a power recovery circuit, L.F. There is a circuit proposed by Weber (US Pat. Nos. 4,866,349 and 5,081,400).

3 shows a general address driving circuit.

As shown in FIG. 3, the address driving circuit includes a power recovery circuit including a capacitor Ca, switches Ar, Af, Aa, Ag, diodes D1 and D2, and an inductor L, and a driving switch, respectively. And a plurality of address selection circuits (A _H ) and a grounding switch (A _L ) (only one address selection circuit is shown in FIG. 3), each of which is connected to a plurality of address electrodes, respectively. do.

The conventional address driving circuit selectively applies the address voltage Va and the ground voltage 0V to the address electrode through the driving switch A _H and the ground switch A _L of the address selection circuit in the address section. In the sections other than the address section, the ground switches A _L of all the address selection circuits are turned on to apply the ground voltage to the address electrode through the current path shown in FIG. 3.

On the other hand, the address selection circuit is made of an integrated circuit (IC), a tape carrier package (TCP), a flexible printed circuit (FPC) or a film (bonded to the address electrode and electrically connected) ) May be mounted in the form of a chip or the like (hereinafter, referred to collectively as a flexible connecting member). Therefore, there is no power supply for supplying a separate voltage in the address selection circuit, and the voltage is supplied to the address selection circuit by connecting to the power supply terminal of the PDP chassis base in the form of a pattern or the like.

However, as described above, when the ground voltage is supplied to the address electrode in a section other than the address, the ground voltage is supplied through the grounding switch A _{L in the} address selection circuit, so that the voltage is not stable and noise and heat generation problems occur. . In addition, the IC may be damaged if the driving switch A _H of the address selection circuit is turned on due to noise while the ground switch A _L is turned on.

It is an object of the present invention to provide an address driving circuit capable of supplying a stable voltage.

According to an aspect of the present invention, a plasma display panel device includes a plurality of first electrodes extending in a first direction and a plurality of second electrodes extending in a second direction crossing the first electrode. panel; A first driving circuit sequentially applying a first voltage to the plurality of first electrodes; A plurality of selection circuits electrically connected to the plurality of second electrodes, respectively, for selecting a second electrode to which a second voltage is applied from among the plurality of second electrodes; And a first transistor and a second transistor connected in series between a first power supply for supplying the second voltage and a second power supply for supplying a third voltage, and having a contact electrically connected to first ends of the plurality of selection circuits. And a second driving circuit configured to apply the second voltage to a second electrode selected by the selection circuit.

In some sections other than the address section, a third voltage is applied to the plurality of second electrodes through the selection circuit and the second transistor.

In this case, the third voltage is a ground voltage, and the fourth transistor is turned off while the second transistor is turned on in some of the sections other than the address section.

In addition, the selection circuit may be configured to be connected in series between a contact point of the first and second transistors and a third power supply supplying a voltage substantially equal to the third voltage, the contact point being electrically connected to the second electrode. A third transistor and a fourth transistor,

The third transistor includes a body diode, and the third voltage is applied to the second electrode through a body diode of the third transistor and the second transistor in some sections other than the address period.

According to another aspect of the present invention, a plasma display panel device includes: a panel including a plurality of first electrodes extending in a first direction and a plurality of second electrodes extending in a second direction crossing the first electrode; A chassis base including a driving circuit to apply a first voltage to the plurality of second electrodes; A plurality of selection circuits electrically connected to the plurality of second electrodes, respectively, for selecting a second electrode to which the first voltage is applied, the second electrode and the second circuit; A flexible connection member for electrically connecting the drive circuit,

The driving circuit may include a first transistor connected in series between a first power supply for supplying the first voltage and a second power supply for supplying a second voltage, and having a contact electrically connected to a first end of the plurality of selection circuits; A second transistor,

In some sections other than the address section, the second transistor is turned on to apply the second voltage to the plurality of second electrodes.

In this case, the second voltage is preferably a ground voltage.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. When a part is connected to another part, this includes not only a direct connection but also an indirect connection between other elements in between.

4 is an exploded perspective view of a plasma display panel according to an exemplary embodiment of the present invention, and FIG. 5 is a schematic plan view of a chassis base according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the plasma display panel includes a plasma panel 10, a chassis base 20, a front case 30, and a rear case 40. The chassis base 20 is disposed on the opposite side of the surface on which the image is displayed on the plasma panel 10 and is coupled to the plasma panel 10. The front and rear cases 30 and 40 are disposed on the front and rear surfaces of the chassis base 20, respectively, and are combined with the plasma panel 10 and the chassis base 20 to form a plasma display panel. .

As shown in FIG. 5, boards 100-600 necessary for driving the plasma panel 10 are formed in the chassis base 20. The address buffer board 100 is formed on the upper and lower portions of the chassis base 20, respectively. The address buffer board 100 may be formed of a single board or a plurality of boards. The address buffer board 100 receives an address driving control signal from an image processing and logic board 500 and applies a voltage to each address electrode for selecting a discharge cell to be displayed.

The scan and sustain drive boards 200 and 300 are disposed on the left and right sides of the chassis base 20, respectively, and the scan board 200 is electrically connected to the scan electrodes via the scan buffer board 400. The scan buffer board 400 performs an operation necessary for scanning the scan electrodes, and is divided into upper and lower sides to facilitate dual driving of the PDP and easy fabrication and assembly of the board (400a and 400b). The scan and sustain drive boards 200 and 300 receive sustain discharge signals from the image processing and logic board 500 and alternately input sustain discharge pulses to the scan and sustain electrodes. Then, sustain discharge occurs in the discharge cell selected by the input sustain discharge pulse.

The image processing and logic board 500 receives an image signal from the outside, generates an address driving control signal and a sustain discharge signal, and applies them to the address buffer board 100 and the scan and sustain driving boards 200 and 300, respectively. The power board 600 supplies power for driving the plasma display panel. The image processing and logic board 500 and the power board 600 are disposed at the center of the chassis base 20.

In general, a plasma display panel is driven by dividing one frame into a plurality of subfields, and a discharge cell to be discharged is selected among the plurality of discharge cells in an address period of each subfield. At this time, in order to select the discharge cells, in the address period, the scan voltage is sequentially applied to the scan electrodes, and the scan electrodes to which the scan voltage is not applied are biased with a positive voltage. An address (hereinafter referred to as an "address voltage") is applied to an address electrode passing through the discharge cell to be selected from among the plurality of discharge cells formed by the scan electrode to which the scan voltage is applied, and the address is not selected. The ground voltage is applied to the electrode. In general, the address voltage uses a positive voltage and the scan voltage uses a ground voltage or a negative voltage, so that discharge occurs at an address electrode to which the address voltage is applied and a scan electrode to which the scan voltage is applied, thereby selecting the corresponding discharge cell.

Hereinafter, an address driver circuit included in the address driver 200 will be described with reference to FIG. 6.

6 is a diagram illustrating an address driving circuit according to an exemplary embodiment of the present invention.

As shown in FIG. 6, the address driving circuit according to the embodiment of the present invention includes a power recovery circuit 210 and a plurality of address selection circuits 220 _{1 to} 220 _m . The address selection circuits 220 _{1 to} 220 _{m are} connected to the plurality of address electrodes A _{1 to} A _m , respectively, and include two switches A _H and A _L for driving and grounding, respectively. For the switches A _H and A _L , a field effect transistor having a body diode may be used, or may be composed of other switches having the same or similar functions.

The first terminal is a power recovery circuit 210 of the driving switch (A _H), a second terminal is connected to the address electrodes (A ₁ ~A _m) of the panel capacitor (Cp), a driving switch (A _H) is turned on When an address voltage (V _a) is supplied from the power recovery circuit 210 is transmitted to the address electrodes (a ₁ ~A _m). The ground switch A _{L is} connected between the address electrodes A ₁ -A _m and the ground voltage (ground voltage in FIG. 6). When the ground switch A _L is turned on, the ground voltage A ₁ -A m is turned on. A _m ). In principle, since the driving switch A _H and the ground switch A _L are not turned on at the same time, it can be generally considered as a switching switch.

As described above, both switches A _H and A _{L of the} address selection circuits 220 _{1 to} 220 _m respectively connected to the address electrodes A _{1 to} A _m are turned on or turned off by the control signal, thereby causing the address electrodes A to be turned off. ₁ ~A _m) an address voltage (Va) or a ground voltage is applied to. That is, in the address period, the address electrode to which the driving switch A _H is turned on and the address voltage Va is applied is selected, and the address electrode to which the ground voltage is applied is not selected because the ground switch A _L is turned on. Do not.

The power recovery circuit 210 includes switches Ar, Af, Aa, Ag, inductors L, diodes D1 and D2, and capacitors Ca. The switches Ar, Af, Aa, and Ag may be made of field effect transistors having body diodes, or may be made of other switches having the same or similar functions. The switches Aa and Ag are connected in series between a power supply (or a power supply line) supplying an address voltage Va and a power supply supplying a ground voltage, and the contacts of the switches Aa and Ag are connected to an address selection circuit 220 _1. It is connected to the 1st terminal of the drive switch _{AH of} (-220 _m ), and the 1st end of the inductor L. The switches Ar and Af are connected between the capacitor Ca and the second end of the inductor L to form a charge path and a discharge path, respectively. Diodes D1 and D2 are respectively connected on the charge path and the discharge path to prevent current from flowing back.

Although Figure 6 is shown as a single power recovery circuit 210 connected to the address selection circuit (220 ₁ ~220 _m), address selection circuit for each group by dividing the (220 ₁ ~220 _m) into groups The power recovery circuit 210 may be connected.

And although shown as being a single power recovery circuit 210 connected to Fig. 6 in the address selecting circuit (220 ₁ ~220 _m), the address selecting circuits each group by dividing the (220 ₁ ~220 _m) into groups Each power recovery circuit 210 may be connected.

Next, the operation of the address driving circuit according to the embodiment of the present invention will be described with reference to FIG.

In order to supply the address voltage to the address electrode in the address period, the address driving circuit operates in the following four modes.

After completion of the reset period, the power recovery capacitor Ca is precharged with a voltage Va / 2 equal to 1/2 of the externally applied voltage Va so that an inrush current does not occur at the start of the address discharge. In this state, the operation of mode 1 starts when the switch Ar and the drive switch A _H of the address selection circuit are turned on.

In the operation section of Mode 1, the LC resonant circuit is driven by the path of the power recovery capacitor Ca, the switch Ar, the diode D1, the inductor L, the driving switch A _H and the plasma panel capacitor Cp. The current flows through the inductor L and the output voltage of the panel increases.

When mode 1 is completed, mode 2 begins, with switch Aa on and switch Ar off. In the operation period of the mode 2, the externally applied voltage Va flows directly to the panel capacitor Cp through the switch Aa so that the output voltage of the panel maintains the voltage Va.

When mode 2 is completed, mode 3 begins, with switch Af on and switch Aa off. In the operation section of the mode 3, a path opposite to that of the mode 1, that is, the plasma panel capacitor Cp, the driving switch A _H , the inductor L, the diode D2, the switch Af, and the power recovery capacitor ( Due to the path of Ca), an LC resonant circuit is formed so that current flows through the inductor L and the output voltage of the panel decreases.

Thereafter, in the operation period of the mode 4, the switch Ag is turned on and the switch Af is turned off to maintain the panel output voltage at 0V. In this state, when the switch Ar is turned on again, the operation returns to the mode 1 operation and the above mode is repeated.

Since the ground switch A _L of the address selection circuit connected to the address electrode of the non-selected cell is turned on during the above mode 1 to mode 4 period, the voltage of the address electrode is maintained at the ground voltage through the path of FIG. 4.

When the address period ends, all the address electrodes remain at the ground voltage until the next address period starts (at the end of the sustain period of the current subfield to the end of the reset period of the next subfield).

7 illustrates a path of a current in which a ground voltage is applied to an address electrode in a section other than an address section in an address driving circuit according to an exemplary embodiment of the present invention.

In the embodiment of the present invention, after the address period ends, the switch Ag of the power recovery circuit is turned on instead of turning on the driving switch A _L of the address selection circuit connected to each address electrode. Then, as shown in FIG. 7, the ground voltage is applied to the address electrode through the current path of the body diode switch Ag of the panel capacitor Cp-drive switch A _H.

If a ground voltage is applied to the address electrode in a section other than the address section through such a current path, the switch Ag is connected to the ground terminal of the chassis base, and thus an address selection circuit from the power supply terminal of the PDP chassis base in the form of a pattern or the like. It is possible to supply a more stable voltage than when applying the ground voltage through the ground switch (A _L ) of. In addition, since the ground switch A _L of the address selection circuit is turned off in a section other than the address period, the IC can be prevented from being damaged even if the driving switch A _H of the address selection circuit is turned on due to noise. have.

On the other hand, in the embodiment of the present invention has been described to apply the ground voltage to the address electrode by turning on the switch (Ag) over all sections other than the address section, but only in some sections other than the address section such as the reset section and the sustain section The present invention can also be applied.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, a stable voltage can be supplied by applying a ground voltage to the address electrode through a switch connected to the ground terminal of the chassis base in a section other than the address section. In addition, since the ground switch of the address selection circuit is turned off in a section other than the address section, the IC may be prevented from being damaged even if the driving switch of the address selection circuit is turned on due to noise.

Claims (7)

A panel comprising a plurality of first electrodes extending in a first direction and a plurality of second electrodes extending in a second direction crossing the first electrode, A first driving circuit which sequentially applies a first voltage to the plurality of first electrodes, A plurality of selection circuits electrically connected to the plurality of second electrodes, respectively, for selecting a second electrode of the plurality of second electrodes to which a second voltage is to be applied; A first transistor electrically connected between a first power supply for supplying the second voltage and a first end of the plurality of selection circuits, and a second power supply for supplying a third voltage and a first end of the plurality of selection circuits A second driving circuit comprising a second transistor electrically connected to the second transistor; The selection circuit may include a third transistor electrically connected between the first end and the second electrode and having a body diode and a fourth transistor electrically connected between the second electrode and the second power source and having a body diode. Include, During some of the sections other than the address section, A plasma display panel device configured to apply the third voltage to the plurality of second electrodes through the body diode of the third transistor and the second transistor while the fourth transistor is turned off and the second transistor is turned on . The method of claim 1, And the third voltage is a ground voltage. delete delete delete A panel comprising a plurality of first electrodes extending in a first direction and a plurality of second electrodes extending in a second direction crossing the first electrode, A chassis base including a driving circuit for applying a first voltage to the plurality of second electrodes, and A plurality of selection circuits electrically connected to the plurality of second electrodes, respectively, for selecting a second electrode to which the first voltage is applied, and wherein the second electrode and the plurality of second electrodes are selected through the selection circuit. A flexible connection member for electrically connecting the drive circuit, The driving circuit may include a first transistor electrically connected between a first power supply for supplying the first voltage and a first terminal of the plurality of selection circuits, and a second power supply for supplying a second voltage and the plurality of selection circuits. A second transistor electrically connected between the first end of the The selection circuit may include a third transistor electrically connected between the first end and the second electrode and having a body diode and a fourth transistor electrically connected between the second electrode and the second power source and having a body diode. Include, During some of the sections other than the address section, A plasma display panel device configured to apply the third voltage to the plurality of second electrodes through the body diode of the third transistor and the second transistor while the fourth transistor is turned off and the second transistor is turned on . The method of claim 6, And the second voltage is a ground voltage.

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