KR100731371B1 - 구성가능 기능 유닛을 포함하는 프로세서를 사용해서 컴퓨터 프로그램을 실행하는 방법, 프로세서 및 컴퓨터 판독가능 기록 매체 - Google Patents
구성가능 기능 유닛을 포함하는 프로세서를 사용해서 컴퓨터 프로그램을 실행하는 방법, 프로세서 및 컴퓨터 판독가능 기록 매체 Download PDFInfo
- Publication number
- KR100731371B1 KR100731371B1 KR1020007011394A KR20007011394A KR100731371B1 KR 100731371 B1 KR100731371 B1 KR 100731371B1 KR 1020007011394 A KR1020007011394 A KR 1020007011394A KR 20007011394 A KR20007011394 A KR 20007011394A KR 100731371 B1 KR100731371 B1 KR 100731371B1
- Authority
- KR
- South Korea
- Prior art keywords
- configurable
- instructions
- combination
- program
- functional unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
- G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
- G06F9/3897—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Logic Circuits (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP99200431 | 1999-02-15 | ||
| EP99200431.7 | 1999-02-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010042690A KR20010042690A (ko) | 2001-05-25 |
| KR100731371B1 true KR100731371B1 (ko) | 2007-06-21 |
Family
ID=8239894
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020007011394A Expired - Lifetime KR100731371B1 (ko) | 1999-02-15 | 2000-01-26 | 구성가능 기능 유닛을 포함하는 프로세서를 사용해서 컴퓨터 프로그램을 실행하는 방법, 프로세서 및 컴퓨터 판독가능 기록 매체 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6721884B1 (https=) |
| EP (1) | EP1073951A1 (https=) |
| JP (1) | JP5148029B2 (https=) |
| KR (1) | KR100731371B1 (https=) |
| WO (1) | WO2000049496A1 (https=) |
Families Citing this family (76)
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| DE19651075A1 (de) | 1996-12-09 | 1998-06-10 | Pact Inf Tech Gmbh | Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen |
| US6542998B1 (en) | 1997-02-08 | 2003-04-01 | Pact Gmbh | Method of self-synchronization of configurable elements of a programmable module |
| US6076152A (en) * | 1997-12-17 | 2000-06-13 | Src Computers, Inc. | Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem |
| US7565461B2 (en) | 1997-12-17 | 2009-07-21 | Src Computers, Inc. | Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers |
| US7373440B2 (en) | 1997-12-17 | 2008-05-13 | Src Computers, Inc. | Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format |
| JP2004506261A (ja) | 2000-06-13 | 2004-02-26 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | パイプラインctプロトコルおよびct通信 |
| AU2002220600A1 (en) | 2000-10-06 | 2002-04-15 | Pact Informationstechnologie Gmbh | Cell system with segmented intermediate cell structure |
| US8058899B2 (en) | 2000-10-06 | 2011-11-15 | Martin Vorbach | Logic cell array and bus system |
| ATE498158T1 (de) * | 2000-11-06 | 2011-02-15 | Broadcom Corp | Umkonfigurierbares verarbeitungssystem und - verfahren |
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| JP3636986B2 (ja) | 2000-12-06 | 2005-04-06 | 松下電器産業株式会社 | 半導体集積回路 |
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| US9037807B2 (en) | 2001-03-05 | 2015-05-19 | Pact Xpp Technologies Ag | Processor arrangement on a chip including data processing, memory, and interface elements |
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| US7996827B2 (en) | 2001-08-16 | 2011-08-09 | Martin Vorbach | Method for the translation of programs for reconfigurable architectures |
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| KR101581882B1 (ko) | 2009-04-20 | 2015-12-31 | 삼성전자주식회사 | 재구성 가능한 프로세서 및 그 재구성 방법 |
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| US4763242A (en) * | 1985-10-23 | 1988-08-09 | Hewlett-Packard Company | Computer providing flexible processor extension, flexible instruction set extension, and implicit emulation for upward software compatibility |
| US5684980A (en) * | 1992-07-29 | 1997-11-04 | Virtual Computer Corporation | FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions |
| EP0825540A1 (de) * | 1996-08-23 | 1998-02-25 | Siemens Aktiengesellschaft | Prozessor mit Pipelining-Aufbau |
| US5748979A (en) * | 1995-04-05 | 1998-05-05 | Xilinx Inc | Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table |
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-
2000
- 2000-01-26 WO PCT/EP2000/000590 patent/WO2000049496A1/en not_active Ceased
- 2000-01-26 JP JP2000600174A patent/JP5148029B2/ja not_active Expired - Lifetime
- 2000-01-26 KR KR1020007011394A patent/KR100731371B1/ko not_active Expired - Lifetime
- 2000-01-26 EP EP00903638A patent/EP1073951A1/en not_active Withdrawn
- 2000-02-11 US US09/501,642 patent/US6721884B1/en not_active Expired - Lifetime
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| US4763242A (en) * | 1985-10-23 | 1988-08-09 | Hewlett-Packard Company | Computer providing flexible processor extension, flexible instruction set extension, and implicit emulation for upward software compatibility |
| US5684980A (en) * | 1992-07-29 | 1997-11-04 | Virtual Computer Corporation | FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions |
| US5748979A (en) * | 1995-04-05 | 1998-05-05 | Xilinx Inc | Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table |
| EP0825540A1 (de) * | 1996-08-23 | 1998-02-25 | Siemens Aktiengesellschaft | Prozessor mit Pipelining-Aufbau |
| JPH10105402A (ja) * | 1996-08-23 | 1998-04-24 | Siemens Ag | パイプライン方式のプロセッサ |
| KR19980018874A (ko) * | 1996-08-23 | 1998-06-05 | 로더리히 네테부쉬, 롤프 옴케 | 파이프라인 방식 프로세서 (processor with pipelining-structure) |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5148029B2 (ja) | 2013-02-20 |
| US6721884B1 (en) | 2004-04-13 |
| EP1073951A1 (en) | 2001-02-07 |
| JP2002537599A (ja) | 2002-11-05 |
| WO2000049496A1 (en) | 2000-08-24 |
| KR20010042690A (ko) | 2001-05-25 |
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