KR100728995B1 - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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KR100728995B1
KR100728995B1 KR1020060081271A KR20060081271A KR100728995B1 KR 100728995 B1 KR100728995 B1 KR 100728995B1 KR 1020060081271 A KR1020060081271 A KR 1020060081271A KR 20060081271 A KR20060081271 A KR 20060081271A KR 100728995 B1 KR100728995 B1 KR 100728995B1
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insulating film
film
gate
buffer oxide
bpsg
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KR1020060081271A
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Korean (ko)
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김재범
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

A method of manufacturing a semiconductor device is provided to control the variation of a threshold voltage in a PMOS portion of a peripheral region by preventing the boron of a BPSG insulating layer from penetrating into an unwanted portion using sequentially a heat treatment and an As ion implantation on a buffer oxide layer. A gate is formed on a semiconductor substrate(21) defined with a cell region and a peripheral region. A gate spacer insulating layer(25) is formed at both sidewalls of the gate. A buffer oxide layer(26) is formed on the entire surface of the resultant structure. A heat treatment is performed on the buffer oxide layer of the peripheral region. An As ion implantation is performed on the resultant buffer oxide layer. A cell spacer insulating layer(27) is formed on the buffer oxide layer. A BPSG insulating layer(28) is formed on the cell spacer insulating layer.

Description

반도체 소자의 제조방법{Method of manufacturing semiconductor device}Method of manufacturing semiconductor device

도 1은 종래기술의 따른 주변지역 PMOS 영역의 문턱전압 열화를 나타내는 그래프.1 is a graph showing the threshold voltage degradation of the peripheral PMOS region according to the prior art.

도 2는 종래기술의 따른 주변지역 NMOS/PMOS 영역의 문턱전압 열화를 나타내는 그래프.Figure 2 is a graph showing the threshold voltage degradation of the peripheral area NMOS / PMOS region according to the prior art.

3a 내지 도 3d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.3A to 3D are cross-sectional views of processes for describing a method of manufacturing a semiconductor device, according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

21: 반도체 기판 22: 게이트 절연막21: semiconductor substrate 22: gate insulating film

23: 게이트 도전막 24: 게이트 하드마스크막23: gate conductive film 24: gate hard mask film

25: 게이트 스페이서용 절연막 26: 버퍼 산화막25 insulating film for gate spacer 26 buffer oxide film

27: 셀 스페이서용 절연막 28: BPSG 절연막27: insulating film for cell spacer 28: BPSG insulating film

G: 게이트G: gate

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 층간절 연막 물질인 BPSG 절연막 형성시 발생하는 문제점을 해결할 수 있는 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method that can solve the problems caused when forming a BPSG insulating film which is an interlayer insulation film material.

반도체 소자의 고집적화에 따라, 고단차의 좁은 간격의 패턴 사이를 공공없이 매립하기 위하여 매립(gap-fill) 및 평탄화 특성이 양호한 BPSG(Boron Phosphorous Silicate Glass)막을 층간절연막으로 사용되고 있다. BACKGROUND ART With high integration of semiconductor devices, a BPSG (Boron Phosphorous Silicate Glass) film having good gap-fill and planarization characteristics is used as an interlayer insulating film in order to fill gaps between patterns having a high gap with no gaps.

이하에서는, 일반적으로 BPSG 절연막을 층간절연막으로 사용하는 반도체 소자의 제조방법을 간략히 설명하도록 한다.Hereinafter, a method of manufacturing a semiconductor device using a BPSG insulating film as an interlayer insulating film will be briefly described.

먼저, 셀지역 및 주변지역으로 구획되며, 상기 주변지역이 PMOS 및 NMOS 형성 영역이 정의된 반도체기판 상에 게이트절연막과 게이트도전막 및 게이트하드마스크막의 적층 구조를 갖는 게이트를 형성한 후, 상기 게이트를 포함한 기판 전면 상에 게이트 스페이서용 질화막과 버퍼 산화막 및 셀 스페이서용 질화막을 차례로 형성한다.First, a gate having a stacked structure of a gate insulating film, a gate conductive film, and a gate hard mask film is formed on a semiconductor substrate, which is divided into a cell region and a peripheral region, wherein the peripheral region has a PMOS and an NMOS formation region. The nitride film for the gate spacer, the buffer oxide film, and the nitride film for the cell spacer are sequentially formed on the entire surface of the substrate including the substrate.

그런다음, 상기 셀 스페이서용 질화막을 포함한 상기 게이트의 양측 기판 표면 내에 소오스/드레인 영역을 형성하여 트렌지스터를 형성한다.Then, a transistor is formed by forming a source / drain region in both substrate surfaces of the gate including the nitride film for the cell spacer.

다음으로, 상기 게이트를 덮도록 상기 게이트를 포함한 기판 전면 상에 층간절연막으로 BPSG 절연막을 형성한 후, 상기 게이트가 노출될 때까지 상기 BPSG 절연막을 CMP하여 평탄화시킨다. Next, after forming a BPSG insulating film as an interlayer insulating film on the entire surface of the substrate including the gate to cover the gate, CMP planarization by CMP the BPSG insulating film until the gate is exposed.

그러나, 상기와 같이, BPSG 절연막을 층간절연막으로 사용하는 경우, BPSG 절연막의 불순물(B,P)에 의한 침투(penetration)가 발생하게 되면서 트랜지스터의 특성에 많은 변동폭을 가져오고 있다.However, as described above, when the BPSG insulating film is used as the interlayer insulating film, penetration due to impurities (B, P) of the BPSG insulating film is generated, which brings about a large variation in the characteristics of the transistor.

자세하게는, 상기 BPSG 절연막의 불순물인 보론(Boron)의 경우 기판의 주변지역에 형성된 상기 버퍼 산화막과 셀 스페이서용 질화막의 계면에 침투하여 주변지역 PMOS 영역의 문턱전압(Vt)을 열화시키는 것으로 알려져 있다.In detail, in the case of boron, which is an impurity of the BPSG insulating film, it is known that the threshold voltage Vt of the peripheral PMOS region is degraded by penetrating into the interface between the buffer oxide film formed in the peripheral region of the substrate and the nitride film for the cell spacer. .

한편, 상기와 같이 주변지역 PMOS 영역의 문턱전압 열화를 억제하기 위한 방법으로, 상기 셀 스페이서용 질화막의 두께를 증가시켜 상기 BPSG 절연막의 불순물 이동을 막는 방법을 사용하고 있으나, 이는, 상기 주변지역의 셀 스페이서용 질화막의 두께 증가시, 상기 셀지역의 셀 스페이서용 질화막의 두께 역시 두꺼워지게 되어, 이로 인해, 랜딩플러그콘택(Landing Plug Contact, 이하, LPC)의 식각 마진(margin)을 감소시키는 문제점을 가져오게 된다.On the other hand, as a method for suppressing the deterioration of the threshold voltage of the PMOS region of the peripheral area as described above, a method of preventing impurity migration of the BPSG insulating film by increasing the thickness of the nitride film for the cell spacer, but this is, When the thickness of the nitride film for the cell spacer increases, the thickness of the nitride film for the cell spacer in the cell region also becomes thick, thereby reducing the etching margin of the landing plug contact (hereinafter referred to as LPC). Will be imported.

이처럼, 상기와 같은 LPC 식각 마진의 감소는, 상기 LPC을 형성하기 위한 상기 층간절연막 식각시, 상기 층간절연막이 완전히 식각되지 않는 현상, 즉, LPC 낫 오픈(not open) 현상을 유발시키게 되면서, 결과적으로, 소자의 전기적 특성을 저하시키게 된다.As such, the reduction of the LPC etching margin causes a phenomenon in which the interlayer insulating layer is not fully etched, that is, an LPC not open phenomenon, when the interlayer insulating layer is etched to form the LPC. This lowers the electrical characteristics of the device.

도 1은 셀 스페이서용 질화막의 두께에 따른 주변지역 PMOS 영역에서의 문턱전압 열화를 보여주는 그래프로서, 도시된 바와 같이, 셀 스페이서용 질화막의 두께에 따라 BPSG 절연막의 불순물(B,P)에 의한 침투(penetration)가 발생하는 경우, 주변지역 PMOS 영역에서는 문턱전압가 열화되는 것을 볼 수 있다.1 is a graph showing the degradation of the threshold voltage in the peripheral region PMOS region according to the thickness of the nitride film for the cell spacer, as shown, infiltration by impurities (B, P) of the BPSG insulating film according to the thickness of the nitride film for the cell spacer When (penetration) occurs, it can be seen that the threshold voltage is degraded in the peripheral PMOS region.

따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, BPSG 절연막의 불순물 요인에 의한 침투 발생을 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다. Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing penetration caused by impurities in the BPSG insulating film.

또한, 본 발명은 층간절연막 식각시 랜딩플러그콘택 낫 오픈 현상을 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 다른 목적이 있다.Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing the landing plug contact sickle opening phenomenon during the interlayer insulating layer etching.

상기와 같은 목적을 달성하기 위하여, 본 발명은, 셀지역 및 주변지역으로 구획된 반도체 기판 상에 게이트를 형성하는 단계; 상기 게이트 양측벽에 게이트 스페이서용 절연막을 형성하는 단계; 상기 게이트 스페이서용 절연막이 형성된 게이트를 포함한 기판 전면 상에 버퍼 산화막을 형성하는 단계; 상기 주변지역의 버퍼 산화막에 대해 열처리를 수행하는 단계; 상기 열처리된 버퍼 산화막 내에 불순물을 주입시키는 단계; 상기 불순물이 주입된 버퍼 산화막 상에 셀 스페이서용 절연막을 형성하는 단계; 및 상기 게이트를 덮도록 상기 셀 스페이서용 절연막 상에 층간절연막용 BPSG 절연막을 형성하는 단계;를 포함하는 반도체 소자의 제조방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of forming a gate on a semiconductor substrate divided into a cell region and a peripheral region; Forming an insulating film for a gate spacer on both sidewalls of the gate; Forming a buffer oxide film on the entire surface of the substrate including the gate on which the insulating film for the gate spacer is formed; Performing heat treatment on the buffer oxide film in the peripheral region; Implanting impurities into the heat-treated buffer oxide film; Forming an insulating film for a cell spacer on the buffer oxide film implanted with the impurities; And forming a BPSG insulating film for an interlayer insulating film on the insulating film for cell spacers to cover the gate.

여기서, 상기 게이트 스페이서용 절연막과 셀 스페이서용 절연막은 질화막 계열의 막으로 형성하는 것을 특징으로 한다.The gate spacer insulating film and the cell spacer insulating film may be formed of a nitride film-based film.

상기 버퍼 산화막은 90∼100Å 두께로 형성하는 것을 특징으로 한다.The buffer oxide film is formed to a thickness of 90 ~ 100Å.

상기 열처리는 500∼1000℃의 온도에서 수행하는 것을 특징으로 한다.The heat treatment is characterized in that performed at a temperature of 500 ~ 1000 ℃.

상기 불순물은 N-type의 불순물인 것을 특징으로 한다.The impurity is characterized in that the N-type impurities.

상기 N-type의 불순물은 As인 것을 특징으로 한다.The N-type impurity is characterized in that As.

상기 셀 스페이서용 절연막은 690∼720℃의 온도에서 120∼140Å 두께로 형성하는 것을 특징으로 한다.The cell spacer insulating film is formed to a thickness of 120 to 140 占 에서 at a temperature of 690 to 720 占 폚.

상기 층간절연막용 BPSG 절연막을 형성하는 단계 후, 상기 BPSG 절연막을 습 식 어닐링하는 단계;를 더 포함하는 것을 특징으로 한다.And after forming the BPSG insulating film for the interlayer insulating film, wet annealing the BPSG insulating film.

상기 BPSG 절연막의 습식 어닐링은 810∼830℃의 온도에서 25∼35분 동안 수행하는 것을 특징으로 한다.Wet annealing of the BPSG insulating film is characterized in that it is carried out for 25 to 35 minutes at a temperature of 810 ~ 830 ℃.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

먼저, 본 발명의 기술적 원리를 설명하면, 본 발명은 BPSG 절연막으로 층간절연막을 형성하는 반도체 소자의 제조방법에 있어서, BPSG 절연막으로 층간절연막을 형성하기 전에, 셀 스페이서용 절연막과 게이트 스페이서용 절연막의 완충역할을 하는 버퍼 산화막을 열처리한 후, 열처리된 버퍼 산화막 내에 불순물, 바람직하게는 N-type의 As을 주입시킨다. 그리고 나서, 상기 불순물이 주입된 버퍼 산화막 상에 셀 스페이서용 절연막을 형성한 후, 상기 셀 스페이서용 절연막 상에 BPSG 절연막을 사용하여 층간절연막(ILD)을 형성한다.First, the technical principle of the present invention will be described. In the method of manufacturing a semiconductor device for forming an interlayer insulating film with a BPSG insulating film, before the interlayer insulating film is formed with the BPSG insulating film, the insulating film for the cell spacer and the insulating film for the gate spacer are described. After the heat treatment of the buffer oxide film serving as a buffer, impurities, preferably N-type As, are injected into the heat-treated buffer oxide film. Then, an insulating film for cell spacers is formed on the buffer oxide film into which the impurities are injected, and then an interlayer insulating film ILD is formed on the cell spacer insulating film using a BPSG insulating film.

이렇게 하면, 상기 버퍼 산화막 내에 불순물이 주입됨에 따라, 상기 BPSG 절연막으로 층간절연막 형성시, 상기 버퍼 산화막과 셀 스페이서용 절연막의 계면 사이에 상기 BPSG 절연막의 불순물인 보론(B)의 침투를 억제할 수 있다.In this case, as impurities are injected into the buffer oxide film, penetration of boron (B) which is an impurity of the BPSG insulating film between the buffer oxide film and the interface between the insulating film for the cell spacer when the interlayer insulating film is formed with the BPSG insulating film can be suppressed. have.

이처럼, 상기 BPSG 절연막 내의 보론이 상기 버퍼 산화막과 셀 스페이서용 절연막의 계면 사이로 침투되는 것을 억제할 수 있으므로, 상기 보론 침투로 인해 발생된 문제, 즉, 문턱전압의 열화를 해결할 수 있다.As described above, since the boron in the BPSG insulating film can be prevented from penetrating between the interface between the buffer oxide film and the insulating film for the cell spacer, the problem caused by the boron penetration, that is, the degradation of the threshold voltage, can be solved.

그리고, 본 발명에서는 셀 스페이서용 절연막의 두께를 증가시키지 않고도 보론 침투를 억제할 수 있으므로, 상기 셀 스페이서용 절연막의 두꺼운 두께로 인해 야기되었던 랜딩플러그콘택의 낫 오픈 현상을 방지할 수 있다.In the present invention, since boron penetration can be suppressed without increasing the thickness of the insulating film for the cell spacer, the sickle opening phenomenon of the landing plug contact caused by the thick thickness of the insulating film for the cell spacer can be prevented.

자세하게는, 도 3a 내지 도 3d를 참조하여 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기로 한다.In detail, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 3A to 3D.

한편, 본 발명의 바람직한 실시예에서는 주변지역(PMOS 영역과 NMOS 영역 포함)에 대해 도시하고 설명하도록 한다.Meanwhile, in the preferred embodiment of the present invention, the peripheral region (including the PMOS region and the NMOS region) will be illustrated and described.

도 3a를 참조하면, 반도체 기판 상(21)에 게이트 절연막(22)과 게이트 도전막(23) 및 게이트 하드마스크막(24)의 순서로 적층된 게이트(G)를 형성한다.Referring to FIG. 3A, a gate G stacked on the semiconductor substrate 21 in the order of the gate insulating film 22, the gate conductive film 23, and the gate hard mask film 24 is formed.

여기서, 상기 게이트 절연막(22)은 실리콘 산화막 등의 통상적인 산화막 계열의 물질막을 이용하며, 상기 게이트 도전막(23)은 폴리실리콘막, 금속막과 금속-질화막 및 금속-실리사이드막등의 금속계막의 단독 또는 이들의 조합된 형태를 이용하여 형성하도록 한다.Here, the gate insulating film 22 uses a conventional oxide film-based material film such as a silicon oxide film, and the gate conductive film 23 is formed of a metal film such as a polysilicon film, a metal film and a metal-nitride film, and a metal-silicide film. It may be formed using a single form or a combination thereof.

그런다음, 상기 게이트(G)를 포함한 기판 전면 상에 질화막 계열의 막을 사용하여 게이트 스페이서용 절연막(25)을 증착한 후, 이를 전면 식각하여 상기 게이트(G) 양측벽에 형성한다.Thereafter, an insulating film 25 for a gate spacer is deposited on the entire surface of the substrate including the gate G by using a nitride film-based layer, and then the entire surface is etched to be formed on both sidewalls of the gate G.

도 3b를 참조하면, 상기 게이트 스페이서용 절연막(25)이 형성된 게이트(G)를 포함한 기판 전면 상에 90∼100Å 두께로 상기 게이트 스페이서용 절연막(25)과 후속의 셀 스페이서용 절연막의 완충역할을 위한 버퍼(buffer)산화막(26)을 형성한다. 여기서, 상기 버퍼 산화막(26)은 LP-TEOS(Low Pressure-Tetra Ethyl Ortho Silicate)막을 사용하여 형성하도록 한다.Referring to FIG. 3B, a buffering role between the gate spacer insulating film 25 and the subsequent cell spacer insulating film is 90 to 100 占 thick on the entire surface of the substrate including the gate G on which the gate spacer insulating film 25 is formed. A buffer oxide film 26 is formed. The buffer oxide layer 26 may be formed using a low pressure-tetra ethyl ortho silicate (LP-TEOS) layer.

그런다음, 상기 주변지역의 버퍼 산화막(26)에 대해 500∼1000℃의 온도에서 급속 열처리(RTP:Rapid Thermal Process) 방식으로 열처리를 수행한다.Then, heat treatment is performed on the buffer oxide film 26 in the surrounding area at a rapid thermal process (RTP) at a temperature of 500 to 1000 ° C.

다음으로, 상기 열처리된 버퍼 산화막(26) 내에 N-type의 불순물, 바람직하게는, As(Arsenic)을 주입시킨다.Next, an N-type impurity, preferably As (Arsenic), is injected into the heat-treated buffer oxide layer 26.

여기서, 본 발명은 상기 버퍼 산화막(26)을 급속열처리하고, 상기 열처리된 버퍼 산화막(26) 내에 N-type의 불순물, 바람직하게는. As을 주입시킴으로서, 후속 공정으로 BPSG(Boron Phosphorous Silicate Glass)막을 사용한 층간절연막(ILD) 형성시, 상기 버퍼 산화막과 후속의 셀 스페이서용 절연막의 계면 사이로 상기 BPSG 절연막의 불순물인 보론(Boron) 침투(penetration)를 억제할 수 있다. Herein, the present invention performs rapid thermal treatment of the buffer oxide film (26), and N-type impurities in the heat-treated buffer oxide film (26), preferably. By injecting As, when forming an interlayer insulating film (ILD) using a BPSG (Boron Phosphorous Silicate Glass) film in a subsequent process, boron (Iron) impurity of the BPSG insulating film is interposed between the buffer oxide film and the subsequent insulating film for cell spacers. penetration) can be suppressed.

도 3c를 참조하면, 상기 불순물이 주입된 버퍼 산화막(26) 상에 질화막 계열의 막을 사용하여 셀 스페이서(cell spacer)용 절연막(27)을 증착한다.Referring to FIG. 3C, an insulating film 27 for a cell spacer is deposited on the buffer oxide layer 26 into which the impurities are injected using a nitride film.

여기서, 상기 셀 스페이서용 절연막(27)은 690∼720℃의 온도에서 120∼140Å 두께로 형성하도록 한다. 바람직하게는, 710℃의 온도에서 130Å 두께로 형성하도록 한다. The cell spacer insulating film 27 is formed to have a thickness of 120 to 140 占 에서 at a temperature of 690 to 720 占 폚. Preferably, it is formed to a thickness of 130 kPa at a temperature of 710 ℃.

도 3d를 참조하면, 상기 게이트(G)를 덮도록 상기 셀 스페이서용 절연막(27) 상에 층간절연막용 BPSG 절연막(28)을 증착한다.Referring to FIG. 3D, a BPSG insulating film 28 for an interlayer insulating film is deposited on the insulating film 27 for cell spacers to cover the gate G. Referring to FIG.

그런다음, 상기 BPSP막의 갭-필(Gap-Fill) 특성을 향상시키기 위해, 상기 BPSG 절연막(28)을 810∼830℃의 온도에서 25∼35분 동안 습식 어닐링(wet annealing)을 수행한다.Then, in order to improve the gap-fill characteristics of the BPSP film, wet annealing of the BPSG insulating film 28 is performed for 25 to 35 minutes at a temperature of 810 to 830 ° C.

전술한 바와 같이, 본 발명은 상기 버퍼 산화막(26)에 대해 열처리를 수행하고, 상기 열처리된 버퍼 산화막 내에 N-type의 불순물, 바람직하게는, As을 주입시킴으로서, BPSG 절연막으로 층간절연막 형성시, 상기 BPSG 절연막의 불순물인 보론(Boron)이 상기 버퍼 산화막(26)과 셀 스페이서용 절연막(27)의 계면 사이에 침투되는 것을 방지할 수 있다.As described above, the present invention performs heat treatment on the buffer oxide film 26 and injects an N-type impurity, preferably As, into the heat-treated buffer oxide film to form an interlayer dielectric film with a BPSG insulating film. It is possible to prevent boron, which is an impurity of the BPSG insulating film, from penetrating between the interface between the buffer oxide film 26 and the insulating film 27 for cell spacers.

만약, 보론이 셀 스페이서용 절연막을 통해 침투된다 하더라도, 상기 버퍼 산화막에 주입된 As(P-type의 반대인 N-type의 불순물)에 의해 카운트 도핑(count doping)되는 효과를 이용할 수 있어 문턱전압의 변동, 자세하게는, 주변지역 PMOS 에서의 문턱전압 변동을 억제할 수 있다.Even if boron is penetrated through the insulating film for the cell spacer, it is possible to take advantage of the effect of counting doping by As (N-type impurity opposite to P-type) injected into the buffer oxide film. Can be suppressed, in detail, the threshold voltage fluctuations in the surrounding area PMOS.

도 2는, 보론 침투 발생시 주변지역 PMOS 영역 및 NMOS 영역에서의 문턱전압의 열화를 나타내는 그래프로서, 주변지역의 NMOS 영역에서는 문턱전압의 변동이 조금 발생하기는 하나 크게 변화하지는 않고, PMOS 영역에서는 문턱전압이 열화되는 것을 볼 수 있으므로, 보론 침투 발생시, 상기 주변지역의 PMOS 영역에서 문턱전압의 변동이 더 심하게 발생되는 것을 알 수 있다.FIG. 2 is a graph showing deterioration of threshold voltages in the PMOS region and the NMOS region in the case of boron infiltration. The threshold voltage fluctuates slightly in the NMOS region of the peripheral region, but does not significantly change, but the threshold in the PMOS region. As it can be seen that the voltage is deteriorated, it can be seen that when boron penetration occurs, the threshold voltage fluctuation occurs more severely in the PMOS region of the surrounding area.

그러므로, 본 발명은 상기 버퍼 산화막을 열처리하고 나서, 상기 열처리된 버퍼 산화막 내에 As를 주입시킴으로서, 상기 BPSG 절연막 형성시, 상기 버퍼 산화막과 셀 스페이서용 절연막의 계면 사이에 보론의 침투를 억제할 수 있어, 주변지역 PMOS 영역에서의 문턱전압 변동을 억제할 수 있다.Therefore, according to the present invention, by injecting As into the heat-treated buffer oxide film after heat-treating the buffer oxide film, it is possible to suppress the penetration of boron between the interface between the buffer oxide film and the insulating film for cell spacer when the BPSG insulating film is formed. Therefore, it is possible to suppress threshold voltage fluctuations in the PMOS region of the surrounding area.

또한, 본 발명은 셀 스페이서용 절연막의 두께를 증가시키지 않고도, 보론 침투를 억제할 수 있으므로, 후속 공정으로 랜딩플러그콘택(Landing Plug Contact) 형성을 위한 상기 층간절연막 식각 공정시 식각 마진(etch margin)을 확보할 수 있게 되어 랜딩플러그콘택의 낫 오픈(not open) 현상을 방지할 수 있다.In addition, the present invention can suppress boron penetration without increasing the thickness of the insulating film for a cell spacer, and thus an etching margin during the interlayer insulating film etching process for forming a landing plug contact in a subsequent process. It can be secured to prevent the not open phenomenon of the landing plug contact.

이후, 도시하지는 않았으나, 공지된 일련의 후속 공정을 차례로 진행하여 본 발명의 실시예에 따른 반도체 소자를 제조한다.Subsequently, although not shown, a series of successive known processes are sequentially performed to manufacture a semiconductor device according to an embodiment of the present invention.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서와 같이, 본 발명은 버퍼 산화막을 열처리하고 나서, 상기 열처리된 버퍼 산화막 내에 As를 주입시킴으로서, BPSG 절연막으로 층간절연막 형성시, 상기 BPSG 절연막의 불순물인 보론(Boron) 침투를 억제할 수 있어, 주변지역 PMOS 영역에서의 문턱전압 변동을 제어할 수 있다.As described above, the present invention can suppress the penetration of boron, which is an impurity of the BPSG insulating film, when the interlayer insulating film is formed of the BPSG insulating film by injecting As into the heat-treated buffer oxide film after the heat treatment of the buffer oxide film. In addition, it is possible to control the threshold voltage variation in the PMOS region of the surrounding area.

또한, 본 발명은 셀 스페이서용 절연막의 두께를 증가시키지 않고도, BPSG 절연막의 불순물인 보론 침투를 방지할 수 있으므로, 랜딩플러그콘택의 형성을 위한 상기 BPSG 절연막 식각시 식각 마진을 확보할 수 있게 되어, 랜딩플러그콘택의 낫 오픈 현상을 방지할 수 있다.In addition, the present invention can prevent the penetration of boron, which is an impurity of the BPSG insulating film, without increasing the thickness of the insulating film for cell spacers, thereby securing an etching margin when etching the BPSG insulating film for forming a landing plug contact. The sickle opening phenomenon of the landing plug contact can be prevented.

Claims (9)

셀지역 및 주변지역으로 구획된 반도체 기판 상에 게이트를 형성하는 단계;Forming a gate on the semiconductor substrate divided into a cell region and a peripheral region; 상기 게이트 양측벽에 게이트 스페이서용 절연막을 형성하는 단계;Forming an insulating film for a gate spacer on both sidewalls of the gate; 상기 게이트 스페이서용 절연막이 형성된 게이트를 포함한 기판 전면 상에 버퍼 산화막을 형성하는 단계;Forming a buffer oxide film on the entire surface of the substrate including the gate on which the insulating film for the gate spacer is formed; 상기 주변지역의 버퍼 산화막을 열처리하는 단계;Heat-treating the buffer oxide film in the peripheral region; 상기 열처리된 버퍼 산화막 내에 불순물을 주입시키는 단계;Implanting impurities into the heat-treated buffer oxide film; 상기 불순물이 주입된 버퍼 산화막 상에 셀 스페이서용 절연막을 형성하는 단계; 및Forming an insulating film for a cell spacer on the buffer oxide film implanted with the impurities; And 상기 게이트를 덮도록 상기 셀 스페이서용 절연막 상에 층간절연막용 BPSG 절연막을 형성하는 단계;Forming a BPSG insulating film for an interlayer insulating film on the insulating film for cell spacers so as to cover the gate; 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 게이트 스페이서용 절연막과 셀 스페이서용 절연막은 질화막 계열의 막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.And the insulating film for the gate spacer and the insulating film for the cell spacer are formed of a nitride film-based film. 제 1 항에 있어서,The method of claim 1, 상기 버퍼 산화막은 90∼100Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The buffer oxide film is a method of manufacturing a semiconductor device, characterized in that formed to a thickness of 90 ~ 100Å. 제 1 항에 있어서,The method of claim 1, 상기 열처리는 500∼1000℃의 온도에서 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The heat treatment is a method of manufacturing a semiconductor device, characterized in that performed at a temperature of 500 ~ 1000 ℃. 제 1 항에 있어서,The method of claim 1, 상기 불순물은 N-type의 불순물인 것을 특징으로 하는 반도체 소자의 제조방법.The impurity is a manufacturing method of a semiconductor device, characterized in that the N-type impurities. 제 5 항에 있어서,The method of claim 5, 상기 N-type의 불순물은 As인 것을 특징으로 하는 반도체 소자의 제조방법.The N-type impurity is a method of manufacturing a semiconductor device, characterized in that. 제 1 항에 있어서,The method of claim 1, 상기 셀 스페이서용 절연막은 690∼720℃의 온도에서 120∼140Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The cell spacer insulating film is formed at a thickness of 120 to 140 에서 at a temperature of 690 to 720 占 폚. 제 1 항에 있어서,The method of claim 1, 상기 층간절연막용 BPSG 절연막을 형성하는 단계 후, 상기 BPSG 절연막을 습식 어닐링하는 단계;를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.And after the step of forming the BPSG insulating film for the interlayer insulating film, wet annealing the BPSG insulating film. 제 8 항에 있어서,The method of claim 8, 상기 BPSG 절연막의 습식 어닐링은 810∼830℃의 온도에서 25∼35분 동안 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The wet annealing of the BPSG insulating film is performed for 25 to 35 minutes at a temperature of 810 ~ 830 ℃.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10116899A (en) 1996-10-09 1998-05-06 Nec Corp Method for manufacturing semiconductor device
KR20050052579A (en) * 2003-11-28 2005-06-03 주식회사 하이닉스반도체 Manufacturing method for semiconductor device
KR20050096626A (en) * 2004-03-31 2005-10-06 주식회사 하이닉스반도체 Forming method of semiconductor device
KR20060038245A (en) * 2004-10-29 2006-05-03 주식회사 하이닉스반도체 Method for fabricating semiconductor device with gate spacer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10116899A (en) 1996-10-09 1998-05-06 Nec Corp Method for manufacturing semiconductor device
KR20050052579A (en) * 2003-11-28 2005-06-03 주식회사 하이닉스반도체 Manufacturing method for semiconductor device
KR20050096626A (en) * 2004-03-31 2005-10-06 주식회사 하이닉스반도체 Forming method of semiconductor device
KR20060038245A (en) * 2004-10-29 2006-05-03 주식회사 하이닉스반도체 Method for fabricating semiconductor device with gate spacer

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