KR100934815B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and to define an active region in order to prevent attack of a passing gate in a high concentration ion implantation process and a high temperature annealing process that are performed when forming a dual poly gate in a recess gate structure. Forming a hard mask layer pattern on the semiconductor substrate including the device isolation layer to expose a gate predetermined region; forming a recess by etching the semiconductor substrate using the hard mask layer pattern as a mask; Forming a gate polysilicon layer, removing a gate polysilicon layer on the device isolation layer, forming a gate electrode layer and a gate hard mask layer on the gate predetermined region, and removing the hard mask layer pattern. High concentration ion implantation process and high temperature A technique in passing the gate may be prevented from receiving an attack on the carbonyl process.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1A to 1L are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a gate of a semiconductor device.

As the semiconductor devices become highly integrated, the conventional planar gate wiring forming method for forming the gate over the planar active region becomes smaller as the gate channel length becomes smaller and the ion implantation doping concentration increases. As a result, an increase in electric filed causes junction leakage, which makes it difficult to secure refresh characteristics of the device.

In order to improve this, a recess gate process is performed in which an active region substrate is etched into a recess pattern and a gate is formed using a gate wiring forming method.

In addition, as the gate forming method for improving the device characteristics, the same polysilicon is not used when forming the PMOS gate and the NMOS gate, and the PMOS uses P-type polysilicon and the NMOS uses N-type polysilicon to realize device operation speed and low power operation. The dual poly gate method has been introduced.

In particular, in order to have the above device characteristics in a device having a small pattern size, a dual poly gate structure in a recess gate structure of a cell region should be used simultaneously. The dual poly gate is formed by depositing undoped poly silicon on the front surface of the wafer, and then using an N + and P + photoresist, using an N-type ion implantation process such as phosphorous in the N + region and a P + region in the P + region. P-type ion implantation processes such as boron are selectively performed to form N-type polysilicon and P-type polysilicon.

However, after forming the gate polysilicon layer to uniformly inject impurities into the recess gate during the ion implantation process, a high concentration ion implantation process and a high temperature annealing process are performed on the entire surface. Doing.

In this case, there is a problem in that the gate polysilicon layer of the gate (hereinafter, referred to as a passing gate) passing through the device isolation film receives an attack.

In addition, the height of the gate electrode layer, for example, the tungsten silicide (WSix) layer is increased to decrease the gate resistance Rs as the gate resistance Rs increases, but in this case, there is a problem in that voids are caused in a subsequent interlayer insulating film forming process.

In addition, since a mask for forming a recess and a mask for forming a gate are separately used when forming the recess gate, misalignment may occur between the recess and the gate, and in this case, left and right sides of the gate in a subsequent ion implantation process. Since the impurity is not uniformly injected, the cell threshold voltage (Vt) is different, there is a problem that the refresh characteristics deteriorate.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing attack of a passing gate in a high concentration ion implantation process and a high temperature annealing process that are performed when forming a dual poly gate in a recess gate structure.

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing voids during a subsequent interlayer dielectric film forming process while reducing gate resistance (Rs).

Another object of the present invention is to provide a method of manufacturing a semiconductor device having a uniform cell threshold voltage Vt by preventing misalignment between a recess and a gate.

Method for manufacturing a semiconductor device according to the invention,

Forming a hard mask layer pattern exposing a gate predetermined region on the semiconductor substrate having an isolation layer defining an active region;

Etching the semiconductor substrate using the hard mask layer pattern as a mask to form a recess;

Forming a gate polysilicon layer on the gate predetermined region;

Forming a gate electrode layer and a gate hard mask layer on the gate predetermined region;

Removing the hard mask layer pattern

Characterized in that it comprises a.

In the present invention, the hard mask film pattern is to form a nitride film with a thickness of 6000 ~ 10000Å,

Performing an ion implantation process for forming a well in the active region and forming a cell channel threshold voltage control layer after the recess forming step;

The ion implantation process for forming the cell channel threshold voltage control layer is characterized in that the BF2 ions are implanted using an energy of 10 keV to 100 keV with an implantation amount of 1e12 to 1e15.

And, in the present invention, the gate polysilicon layer forming step

Forming the gate polysilicon layer over the entire surface;

Planarizing the gate polysilicon layer until the hard mask layer pattern is exposed;

Removing a predetermined thickness of the gate polysilicon layer by a wet etching method;

The removing of the gate polysilicon layer may be performed by a wet etching process using a hard mask layer pattern exposing the gate polysilicon layer on the device isolation layer.

After removing the gate polysilicon layer

Implanting phosphorus (P) ions into the entire surface of the resultant using an energy of 10 keV to 100 keV at an injection amount of 1e12 to 1e17,

It characterized in that it further comprises the step of performing a post implantation anneal (post implantation anneal) process for 3 seconds to 50 minutes at a temperature of 500 ~ 950 ℃ on the front of the result.

In addition, in the present invention, the gate electrode layer forming step is

Forming a tungsten layer over the entire surface,

Planarizing the tungsten layer until the hard mask layer pattern is exposed;

Removing a predetermined thickness of the tungsten layer by a wet etching method;

The gate hard mask layer forming step

Forming the gate hard mask layer over the entire surface;

Planarizing the gate hard mask layer until the hard mask layer pattern is exposed.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1A to 1L are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 1A, a pad oxide film is formed over the semiconductor substrate 10, and a pad nitride film is formed over the pad oxide film.

Next, the pad nitride layer, the pad oxide layer, and the semiconductor substrate 10 having a predetermined depth are etched by a photolithography process using an isolation mask to form a device isolation trench.

Next, an oxidation process is performed on the sidewalls and the bottom for device isolation to form a sidewall oxide film on the trench isolation surface.

Next, a liner nitride film and a liner oxide film are formed on the sidewall oxide film.

Next, a device isolation insulating film is formed on the entire surface to gap-fill the device isolation trench.

Next, the device isolation insulating film is planarized until the pad nitride film is exposed, and the pad nitride film and the pad oxide film are removed to form the device isolation film 14 defining the active region 12.

Next, a first hard mask layer 16 is formed on the semiconductor substrate 10.

In this case, the first hard mask layer 16 may be formed to have a thickness of 6000 to 10000 GPa, and may be greater than the height of the gate to be formed in a subsequent process in consideration of the thickness lost during the planarization process for forming the gate pattern. It is desirable to form thicker.

Referring to FIG. 1B, a photoresist pattern is formed on the first hard mask layer 16 to expose a predetermined region of a recess gate.

Next, the first hard mask layer 16 and the active region 12 are etched using the photoresist pattern as a mask to form a first hard mask layer pattern 16a and a recess 18.

Then, the photoresist pattern is removed.

Next, an ion implantation process for forming a cell well is performed using the first hard mask layer pattern 16a as an ion implantation mask, and an ion implantation process for adjusting a cell channel threshold voltage is performed to perform the active region 12. The cell channel threshold voltage adjusting layer 20 is formed on the substrate.

In this case, the ion implantation process for adjusting the cell channel threshold voltage is preferably performed using energy of 10 keV to 100 keV with an implantation amount of 1e12 to 1e15.

Referring to FIG. 1C, the gate polysilicon layer 22 is formed on the entire surface.

At this time, the gate polysilicon layer 22 is preferably formed to a thickness of 12000 ~ 140001.

Next, the gate polysilicon layer 22 is planarized until the first hard mask layer pattern 16a is exposed.

At this time, the planarization process is preferably performed by chemical mechanical polishing (CMP) method.

Referring to FIG. 1D, the gate polysilicon layer 22 is removed to form a gate polysilicon layer pattern 22a.

In this case, the process of removing the gate polysilicon layer 22 is performed to leave the thickness of the gate polysilicon layer constituting the normal gate, for example, a thickness of about 1000 to 1200 Å, and the first hard mask layer pattern 16a. And a wet etching method using an etching selectivity ratio between the gate polysilicon layer 22 and the gate polysilicon layer 22.

Then, as shown in FIG. 1D (b) over the entire surface, the gate polysilicon layer pattern 22a on the active region 12 is covered, and the gate polysilicon layer on the device isolation layer 14 The pattern 22a forms a second hard mask film pattern 24 to be exposed.

Referring to FIG. 1E, the gate polysilicon layer pattern 22a exposing the second hard mask layer pattern 24 as a mask is removed.

In this case, the gate polysilicon layer pattern 22a removal process is preferably performed by a wet etching method.

Referring to FIG. 1F, the second hard mask layer pattern 24 is removed.

Next, phosphorus (P) ions are implanted into the gate polysilicon layer pattern 22a using the first hard mask film pattern 16a using an ion implantation energy of 10 keV to 100 keV at an implantation amount of 1e12 to 1e17. Then, a post implantation anneal process is performed on the entire surface of the resultant at a temperature of 500 to 950 ° C. for 3 seconds to 50 minutes.

Accordingly, an N-type gate polysilicon layer pattern 22b having a uniform concentration is formed, and the ion implantation process as described above is performed while the gate polysilicon layer pattern 22a on the device isolation layer 14 is already removed. Since the annealing process is performed, the phenomenon of being attacked can be prevented.

Referring to FIG. 1G, the gate electrode layer 26 is formed on the entire surface.

In this case, the gate electrode layer 26 preferably forms a tungsten silicide (WSix) layer with a thickness of 8000 to 10,000 Å.

Referring to FIG. 1H, the gate electrode layer 26 is planarized until the first hard mask layer pattern 16a is exposed.

Next, the gate electrode layer 26 is removed by a predetermined thickness to form the gate electrode layer patterns 26a and 26b.

In this case, the removal process of the gate electrode layer 26 is performed in order to leave the thickness of the gate electrode layer constituting the normal gate, for example, the thickness of 1500 to 2000 microns, and the first hard mask layer pattern 16a and the gate electrode layer. It is preferable to perform by the wet etching method using the etching selectivity between (26).

Here, since the gate electrode layer pattern 26b on the device isolation layer 14 is formed thicker than the gate electrode layer pattern 26a on the active region 12 by the thickness of the N-type gate polysilicon layer pattern 22b, The gate resistance Rs can be reduced.

In addition, since the height of the entire gate is formed to be the same as in the related art, a phenomenon in which voids occur in a subsequent interlayer insulating film forming process can be prevented.

Referring to FIG. 1I, the gate hard mask layer 28 is formed over the entire surface.

In this case, the gate hard mask layer 28 is preferably formed to a thickness of 6000 ~ 8000Å.

Referring to FIG. 1J, the gate hard mask layer 28 is planarized to form the gate hard mask layer pattern 28a until the first hard mask layer pattern 16a is exposed.

Accordingly, the gate 30 including the N-type gate polysilicon layer pattern 22b, the gate electrode layer pattern 24a, and the gate hard mask layer pattern 28a is completed.

That is, in the present invention, since the recess 18 is formed using the first hard mask film pattern 16a as a mask, and the gate 30 is subsequently formed, the recess 18 and the gate ( 30) There is no misalignment between them.

Referring to FIG. 1K, the first hard mask film pattern 16a is removed.

Thereafter, a source / drain ion implantation process is performed on the entire surface of the resultant to form a source / drain region 32 in the active region 12 below both sides of the gate 30.

At this time, the source / drain ion implantation process is preferably performed by using the energy of 10keV ~ 100keV in the injection amount of phosphorus (P) ions 1e12 ~ 1e15.

Referring to FIG. 1L, a photoresist pattern 34 is formed on the entire surface of the bit line contact predetermined region.

Next, the C-halo region 36 is formed by performing the C-halo ion implantation process using the photoresist pattern 34 as an ion implantation mask.

In this case, the C-halo ion implantation process is preferably carried out using the energy of 10keV ~ 100keV in a boron (B) ion implantation amount of 1e12 ~ 1e15.

In the method of fabricating a semiconductor device according to the present invention, a gate is formed in a high concentration of an ion implantation process and a high temperature annealing process, which are performed when a dual poly gate is formed by forming a gate in a state in which a gate polysilicon layer on a device isolation film is removed. Provides the effect to prevent.

In addition, the present invention can form the gate electrode layer as thick as the thickness of the removed gate polysilicon layer to reduce the gate resistance (Rs), it is possible to prevent the occurrence of void (void) during the formation of the subsequent interlayer insulating film Provide the effect.

In addition, the present invention prevents a phenomenon in which misalignment occurs between the recess and the gate by forming the recess and the gate by using a mask exposing the gate predetermined region so that impurities are uniformly distributed during the C-halo ion implantation process. As a result, the cell threshold voltage Vt is uniform, thereby providing an effect of improving refresh characteristics.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (10)

Forming a first hard mask layer pattern exposing a gate predetermined region on the semiconductor substrate including an isolation layer defining an active region; Etching the semiconductor substrate using the first hard mask layer pattern as a mask to form a recess; Forming a gate polysilicon layer over said recess; Forming a second hard mask layer pattern covering the gate polysilicon layer formed on the active region; And Removing the polysilicon layer formed on the device isolation layer, and then removing the second hard mask layer pattern Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the first hard mask layer pattern is formed of a nitride layer having a thickness of 6000 to 10000 GPa. The method of claim 1, further comprising performing an ion implantation process to form a well and a cell channel threshold voltage control layer in the active region after the recess forming step. The method of claim 3, wherein the ion implantation process for forming the cell channel threshold voltage adjusting layer is performed using energy of 10 keV to 100 keV at an implantation amount of 1e12 to 1e15. The method of claim 1, wherein the gate polysilicon layer forming step Forming the gate polysilicon layer over the entire surface; Planarizing the gate polysilicon layer until the first hard mask layer pattern is exposed; And Removing a predetermined thickness of the gate polysilicon layer by a wet etching method Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the removing of the gate polysilicon layer is performed by a wet etching process using a second hard mask layer pattern exposing the gate polysilicon layer on the isolation layer. The method of claim 1, further comprising removing the second hard mask layer pattern. Implanting phosphorus (P) ions into the upper portion of the semiconductor substrate using energy of 10 keV to 100 keV at an implantation amount of 1e12 to 1e17; And Performing a post implantation anneal process on the semiconductor substrate at a temperature of 500 to 950 ° C. for 3 seconds to 50 minutes. Method of manufacturing a semiconductor device further comprising. The method of claim 1, Forming a gate electrode layer on the gate polysilicon layer formed on the active region; And And forming a gate hard mask layer on the gate electrode layer. The method of claim 8, wherein the forming of the gate electrode layer Forming a tungsten layer over the entire surface; Planarizing the tungsten layer until the hard mask layer pattern is exposed; And Removing a predetermined thickness of the tungsten layer by a wet etching method Method of manufacturing a semiconductor device comprising a. The method of claim 8, further comprising planarizing the gate hard mask layer after the gate hard mask layer is formed until the first hard mask layer pattern is exposed. .

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