KR100779400B1 - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device and a manufacturing method of the same are provided to improve characteristics of a transistor by preventing a shifting effect of a flat band voltage. A high dielectric layer is formed on a silicon substrate(101). An insulating layer(102) is formed on a boundary between the high dielectric layer and the silicon substrate by heat-treating the silicon substrate. A conductive layer is formed on the silicon substrate. A gate electrode(104) is formed by removing selectively the high dielectric layer and the insulating layer. An insulating layer sidewall(106) is formed at both sides of the gate electrode. A source/drain impurity region(107) is formed on a surface of the silicon substrate of both sides of the gate electrode. A metal silicide layer(108) is formed on the silicon substrate. A stress buffering layer(109) and an interlayer dielectric are formed on the semiconductor substrate. A high melting point metal layer is formed on a front surface of the semiconductor substrate.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2G are cross-sectional views illustrating a semiconductor device and a method of manufacturing the same according to the present invention.

Disclosed is a semiconductor device and a method of manufacturing the same.

Although the size of transistors has been required to decrease gradually as the degree of integration of semiconductor devices is improved, there is a limitation that the depth of source / drain junctions cannot be made infinitely shallow.

This is because as the channel length decreases from the conventional long channel to a short channel of 0.5 μm or less, the depletion region of the source / drain penetrates into the channel, thereby reducing the effective channel length and reducing the threshold voltage. This is because the threshold voltage decreases, resulting in a short channel effect in which the gate control function is lost in the MOS transistor.

To prevent this short channel effect, the thickness of the gate insulating film should be reduced, the channel width between source / drain, i.e., the maximum width of depletion under the gate, and the impurity concentration in the silicon substrate should be reduced. Should

But above all, it is important to form a shallow junction. To this end, the search for a method capable of realizing shallow bonding in ion implantation equipment and subsequent heat treatment in semiconductor device manufacturing processes continues.

In addition, the MOS transistor may be represented by a light doped drain (LDD) structure.

Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1A, the device isolation layer 22 is formed through a LOCOS or shallow trench isolation (STI) process in the device isolation region of the silicon substrate 21 defined as the active region and the device isolation region.

Subsequently, the silicon substrate 21 is thermally oxidized at a high temperature to form a gate oxide film 23 on the silicon substrate 21.

As shown in FIG. 1B, n-type or p-type impurity ions may be selectively implanted to form a channel of a transistor in an active region of the silicon substrate 21 to form an n-well or p-well ( Not shown), and a high temperature heat treatment is performed at a temperature of about 1050 to 1200 ° C.

Subsequently, a polysilicon layer is deposited on the gate oxide layer 23, and the polysilicon layer and the gate oxide layer 23 are selectively etched through a photo and etching process to form a gate electrode 24.

Then, using the gate electrode 24 as a mask, n-type or p-type impurity ions are implanted into the entire surface of the silicon substrate 21, so that LDD (in the surface of the silicon substrate 21 on both sides of the gate electrode 24) is implanted. Lightly Doped Drain) region 25 is formed.

As shown in FIG. 1C, an insulating film is deposited on the entire surface of the silicon substrate 21 by an LPCVD method, and an etch back process is performed on the entire surface of the silicon substrate 21 to form an insulating film sidewall 26 on both sides of the gate electrode 24. ).

Subsequently, n-type or p-type high concentration impurity ions are implanted into the front surface by using the gate electrode 24 and the insulating film sidewall 26 as a mask, so that the source / silicon substrates on both sides of the gate electrode 24 are formed. The drain impurity region 27 is formed, and heat treatment is performed at a temperature of about 1000 to 1050 캜.

As shown in FIG. 1D, a cleaning process is performed on the silicon substrate 21 to remove various objects such as metal impurities, organic contaminants, and natural oxide films.

Subsequently, the silicon substrate 21 having the cleaning process completed is moved to a sputter chamber (not shown) of the sputtering equipment to form a metal film 28 such as cobalt on the entire surface of the silicon substrate 21.

As shown in FIG. 1E, the silicon substrate 21 is placed in a rapid thermal process (RTP) device or an electric furnace, and subjected to heat treatment at 400 to 600 ° C. to provide the gate electrode 24 and source and drain impurity regions. A metal silicide film 29 is formed on the surface of the silicon substrate 21 on which the 27 is formed.

Here, the metal silicide layer 29 is formed by reacting silicon ions of the gate electrode 24 and the silicon substrate 21 with metal ions of the metal layer 28 during the heat treatment process, and the insulating film sidewall 26. And no reaction occurs on the device isolation film 22 and remains in the form of a metal film 28.

As shown in FIG. 1F, the silicon substrate 21 is annealed at a predetermined temperature after removing the remaining metal film 28 that is not used to form the metal silicide film 29. The metal silicide film 29 of low resistance is completed by stabilizing.

However, there is a problem in the method of manufacturing a semiconductor device according to the prior art as described above.

In other words, polysilicon gates are advantageous for high temperature processes and have excellent overall process compatibility and excellent electrical characteristics after device fabrication.However, as the ultra-high integration and size reduction of devices progress, high resistance and gate depletion of the gate oxide film Increasing thickness and threshold voltage fluctuations due to diffusion of dopants in polysilicon gates are problematic.

On the other hand, in recent years, the miniaturization of MOSFETs is progressing due to the trend of increasing capacity and high directivity of semiconductors. As the miniaturization progresses, thinning of the gate insulating film causes problems such as an increase in the gate leakage current due to the tunnel current.

In order to solve this problem, a gate insulating film using a high dielectric constant material such as HfO ₂ , Ta ₂ O ₅ , and Al ₂ O ₃ is used instead of the existing SiO ₂ to secure a physical film thickness while reducing the EOT (Equivalent Oxide). Attempts have been made to realize thickness.

In addition, Fully Silicided Poly Silicon (FUSI), which has the advantage of being compatible with high k dielectrics, is being developed as a gate to replace conventional polysilicon.

However, a transistor using a gate insulating film and a FUSI gate having a high rate of conductivity is not the only advantage. An interfacial dipole is formed in the interfacial layer between the gate insulating film and silicon having a high rate of conductivity, causing mobility degradation, and a fixed charge generated between the gate insulating film and the FUSI gate. The charge prevents the diffusion of FUSI materials such as nickel (Ni), which prevents polysilicon from fully silicide and shifts the flat band voltage. There is a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which improve the characteristics of a transistor by removing a fixed charge and preventing a flat band voltage from shifting.

A method of manufacturing a semiconductor device according to the present invention includes the steps of forming a high dielectric film on a silicon substrate; Heat-treating the silicon substrate on which the high dielectric film is formed to form an insulating film at an interface between the high dielectric film and the silicon substrate; Forming a conductive layer on the silicon substrate, and selectively removing the conductive layer, the high dielectric layer, and the insulating layer to form a gate electrode; Forming sidewalls of an insulating film on both sides of the gate electrode; Forming a source / drain impurity region in a surface of a silicon substrate on both sides of the gate electrode; Forming a metal silicide layer on the silicon substrate on which the gate electrode and the source / drain impurity region are formed; Forming a stress relaxation layer and an interlayer insulating layer on the semiconductor substrate at a height of the metal silicide layer on the gate electrode; And depositing and heat-treating a high melting point metal film on the entire surface of the semiconductor substrate.

A semiconductor device according to the present invention comprises a high dielectric film formed on a silicon substrate; An insulating film formed at an interface between the high dielectric film and a silicon substrate; A gate electrode formed on the high dielectric layer and silicided; Sidewalls of insulating layers formed on both sides of the gate electrode; Source / drain impurity regions formed in a surface of the silicon substrate on both sides of the gate electrode; A metal silicide film formed on the source / drain impurity region; And a stress relaxation layer and an interlayer insulating layer formed on the semiconductor substrates on both sides of the gate electrode.

Hereinafter, a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2G are cross-sectional views showing a semiconductor device and a method of manufacturing the same according to the present invention.

As shown in FIG. 2A, an HfO ₂ film is deposited on the silicon substrate 101 with a gate insulating film 102 at a thickness of about 20 kPa in a N ₂ atmosphere by MOCVD (Metal Organic Chemical Vapor Deposition) method.

Here, when the gate insulating layer 102 is deposited by MOCVD, a precursor material is Hf [OC (CH ₃ ) (C ₂ H ₅ ) ₂ ] ₄ , Hf (mp) ₄ (Hafnium 3-Methyl-3 Because no pentoxide is used, no additional oxygen source is required and the deposition temperature is between 500 and 600 ° C.

Meanwhile, although the HfO ₂ film is used as the gate insulating film 102 in the embodiment of the present invention, one of the high dielectric constants having a high dielectric constant is not limited thereto.

As shown in FIG. 2B, H ₂ (5%) / N ₂ atmosphere, 450 ° C., 1000 ° C., and 500 to remove stress existing between the silicon substrate 101 and the gate insulating film 102 formed thereon. Rapid thermal annealing (RTA) is performed sequentially at a temperature of ℃.

In this case, an oxide film 103 formed between HfO ₂ and the silicon substrate 101 constituting the gate insulating film 102 may reduce a stress buffer and an oxide interface dipole. do.

However, when the interface dipoles present in SiO ₂ / HfO ₂ are not completely removed, the transistor channel mobility is lowered. Thus, NH ₃ plasma treatment is performed at a temperature of 700 to 800 ° C.

Here, another important purpose of the NH ₃ plasma treatment is to remove the fix charge, such as oxygen vacancy, formed between the HfO ₂ film and the polysilicon to be deposited thereon.

In addition, it also plays a role in preventing penetration of B (Boron) and P (Phosphorous).

As shown in FIG. 2C, a polysilicon film is formed on the gate insulating film 102 at a temperature of 500 to 600 ° C. by using low pressure chemical vapor deposition (LPCVD).

Subsequently, the polysilicon layer is selectively removed through a photo and reactive ion etching (RIE) etching process to form the gate electrode 104.

Source / drain impurity ions are implanted into the silicon substrate 101 using the gate electrode 104 as a mask, so that an LDD region is formed in the surface of the silicon substrate 101 on both sides of the gate electrode 104. Form 105.

As shown in FIG. 2D, an insulating film is formed on the entire surface of the silicon substrate 101 including the gate electrode 104 and then an etch back process is performed to form insulating film sidewalls 106 on both sides of the gate electrode 104. do.

Subsequently, the source and drain impurity regions 107 are formed by implanting source and drain impurity ions onto the silicon substrate 101 using the gate electrode 104 and the insulating film sidewall 106 as a mask.

As shown in FIG. 2E, a high melting point metal film is deposited on the entire surface of the silicon substrate 101 including the gate electrode 104, and a heat treatment process is performed to obtain the metal ions of the high melting point metal film and the gate electrode 104. Silicon ions are reacted to form the metal silicide film 108.

Here, the high melting point metal film deposits cobalt, nickel, titanium, tungsten, tantalum, molybdenum, or the like by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

As shown in FIG. 2F, the SiN liner layer 109 may be 500 to LPCVD for stress relief occurring between the films on the entire surface of the silicon substrate 101 including the gate electrode 104. Deposit at 2000 ~ 2500Å at 600 ℃.

Subsequently, BPSG 110 of about 5000 to 6000 Pa is deposited on the SiN liner layer 109 at an temperature of 450 ° C to 550 ° C by APCVD (Atmospheric Pressure CVD).

As shown in FIG. 2G, the SiN liner layer 109 and the BPSG 110 are selectively removed by performing a CMP process on the entire surface of the metal silicide layer 108 on the gate electrode 104 to expose the surface thereof. do.

Subsequently, after the CMP, the upper part is washed with a diluted HF and IPA mixed solution, and then a nickel film (not shown) is deposited to a thickness of about 500 kV using a physical vapor deposition (PVD) method.

Here, although the nickel film is described as an example in the embodiment of the present invention, the nickel film may be formed of a high melting point metal film, that is, cobalt, titanium, tungsten, tantalum, molybdenum, or the like.

In addition, rapid thermal annealing (RTA) is sequentially performed at the temperatures of 450 ° C., 1000 ° C., and 500 ° C. on the silicon substrate 101 on which the nickel film is formed. At this time, the nickel film starts to react with the metal silicide film 108 formed on the gate electrode 104 and is then heat treated again through RTA to complete silicide formation.

Here, the polysilicon layer is completely silicided to the upper portion of the high dielectric film by the heat treatment reaction. In this step, since the fixed charge such as the oxygen depletion layer formed between the HfOS ₂ and the polysilicon film is removed, a fully silicided gate can be formed.

Meanwhile, the nickel film not reacted with the metal silicide film 108 is removed.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

As described above, the method for manufacturing a semiconductor device according to the present invention has the following effects.

That is, by forming a gate insulating film having a high dielectric constant and performing a heat treatment process on the entire surface, it is possible to completely silicide the polysilicon to the upper portion of the high dielectric film by removing the fixed charge generated at the interface with the gate material that is subsequently deposited. Transistor characteristics can be improved by preventing the band voltage from shifting.

Claims (10)

Forming a high dielectric film on a silicon substrate; Heat-treating the silicon substrate on which the high dielectric film is formed to form an insulating film at an interface between the high dielectric film and the silicon substrate; Forming a conductive layer on the silicon substrate, and selectively removing the conductive layer, the high dielectric layer, and the insulating layer to form a gate electrode; Forming sidewalls of an insulating film on both sides of the gate electrode; Forming a source / drain impurity region in a surface of a silicon substrate on both sides of the gate electrode; Forming a metal silicide layer on the silicon substrate on which the gate electrode and the source / drain impurity region are formed; Forming a stress relaxation layer and an interlayer insulating layer on the semiconductor substrate at a height of the metal silicide layer on the gate electrode; And And depositing and heat-treating a high melting point metal film on the entire surface of the semiconductor substrate. The method of claim 1, The heat treatment for forming the insulating film is a semiconductor device manufacturing method, characterized in that carried out sequentially at a temperature of 450 ℃, 1000 ℃, 500 ℃ in H ₂ (5%) / N ₂ atmosphere. The method of claim 1, And forming an insulating film between the high dielectric film and the silicon substrate and subjecting the silicon substrate to a NH ₃ plasma treatment at a temperature of 700 to 800 ° C. The method of claim 1, The stress relaxation layer is a semiconductor device manufacturing method, characterized in that the SiN liner layer having a thickness of 2000 ~ 2500 ~ at a temperature of 500 ~ 600 ℃ by LPCVD method. The method of claim 1, The interlayer insulating layer is a method of manufacturing a semiconductor device, characterized in that the BPSG having a thickness of 5000 ~ 6000 Å at a temperature of 450 ℃ ~ 550 ℃ by APCVD method. The method of claim 1, The high dielectric film is a semiconductor device manufacturing method characterized in that the HfO ₂ film deposited to a thickness of 20Å by MOCVD method in N ₂ atmosphere. A high dielectric film formed on a silicon substrate; An insulating film formed at an interface between the high dielectric film and a silicon substrate; A gate electrode formed on the high dielectric layer and silicided; Sidewalls of insulating layers formed on both sides of the gate electrode; Source / drain impurity regions formed in a surface of the silicon substrate on both sides of the gate electrode; A metal silicide film formed on the source / drain impurity region; And And a stress relaxation layer and an interlayer insulating layer formed on the semiconductor substrate on both sides of the gate electrode. The method of claim 7, wherein The high dielectric film is a semiconductor device, characterized in that the HfO ₂ film. The method of claim 7, wherein The stress relief layer is a semiconductor device, characterized in that the SiN liner layer. The method of claim 7, wherein The insulating film is a semiconductor device, characterized in that the oxide film.

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