KR100714281B1 - Sense amplifier circuit and sense amplifier-based flip flop including the same - Google Patents

Abstract

A sense amplifier based flip-flop that operates in response to a clock signal is disclosed. Such a sense amplifier based flip-flop outputs a signal of a second level to a first output terminal regardless of an input signal pair when the clock signal is a first level, and the input signal pair when the clock signal is a second level. A first latch unit for outputting an evaluation signal pair corresponding to the first output terminal, a second latch unit for latching the evaluation signal pair output from the first output terminal, and then outputting the second signal to the second output terminal; And a floating prevention part controlled by a signal of an output terminal and operatively connected between current passing nodes of the first latch unit to prevent floating of the first output terminal. Thus, the present invention has the effect of improving the problem that the output terminal, that is, the input terminal of the second latch portion, which is the slave latch portion, becomes in a floating state, thereby improving the problem of data loss and a decrease in input sensitivity.

Sense Amplifiers, Sensitivity, Floating, Flip-Flops

Description

Sense amplifier circuit and sense amplifier-based flip flop including the same

1 is a circuit diagram showing an example of a conventional sense amplifier based flip-flop.

FIG. 2 is a timing diagram illustrating an operation of a sense amplifier based flip flop of FIG. 1. FIG.

3 is a circuit diagram showing an example of a conventional sense amplifier based flip-flop for improving the problem in FIG.

FIG. 4 is a timing diagram illustrating an operation of a sense amplifier based flip flop of FIG. 3.

5 is a circuit diagram illustrating a flip-flop based on a sense amplifier according to an embodiment of the present invention.

FIG. 6 is a timing diagram illustrating an operation of a sense amplifier based flip flop of FIG. 5.

FIG. 7 is a circuit diagram illustrating an embodiment of a floating prevention unit in FIG. 5. FIG.

8 is a circuit diagram illustrating another embodiment of the floating prevention unit in FIG. 5.

FIG. 9 is a circuit diagram illustrating an example of a second latch unit in FIG. 5. FIG.

10 is a circuit diagram illustrating a flip-flop based on a sense amplifier according to a modified embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

CLK: Clock signal 20: Second latch portion, slave latch portion

22: first latch portion, master latch portion 100: floating prevention portion

S, R: input terminal of the second latch portion D: input signal

N21 to N27, N31 to N35: nodes

PM21 to PM24, PM100, PM102, PM31 to PM36: PMOS transistor

NM21 to NM29, NM100, NM102, NM31 to NM35: NMOS transistors

INV21, INV22: Inverter VDD: Power supply voltage, Power supply voltage terminal

The present invention relates to a semiconductor integrated circuit, and more particularly, to a sense amplifier circuit and a sense amplifier based flip-flop having the same.

Due to the explosive demand of mobile devices such as mobile phones, personal digital assistants (PDAs), notebook computers, etc., and the increase in power management costs due to the high capacity and speed of the very large scale integration (VLSI) system, low power consumption of integrated circuits is becoming an issue. . One example for lowering the power of an integrated circuit is to improve the structure of a circuit or logic.

The circuit structure of the VLSI system can be classified into two functions. One function is a logic function for transmitting a desired output signal in response to an input signal, and the other function is a memory function for storing an input signal or outputting a stored signal in response to a clock signal. The most basic and essential part of the latter block is the flip flop.

One example of the flip-flop is a sense amp.-based flip flop. In general, the sense amplifier-based flip-flop can be divided into a master latch and a slave latch.

As the mast latch portion, a current sensing type sense amplifier circuit is often used, and the setup time of the master latch portion is very small (nearly " 0 "). In addition, a NAND type SR latch is widely used as the slave latch, and a high speed operation is possible and a very stable operation can be obtained.

The master latch part employs a dynamic structure to obtain a high speed operation, which is an advantage of the dynamic structure, and the slave latch part employs a static structure, to obtain a stable operation, which is an advantage of the static structure. have.

1 is a circuit diagram showing an example of a conventional sense amplifier based flip-flop.

Referring to FIG. 1, the sense amplifier based flip-flop includes a master latch unit 2 and a slave latch unit 1.

The master latch unit 2 includes PMOS transistors PM1, PM2, PM3, PM4 and NMOS transistors NM1, NM2, NM3, NM4, and NM5, and the slave latch unit 1 is illustrated in the drawing. Although not shown in detail above, it may be a conventional NAND type SR latch.

Referring to the structure of the master latch unit 2, first, the PMOS transistor PM1 is connected between the power supply voltage terminal VDD and the output node N1 and operates in response to the clock signal CLK. The output node N1 and the output node N2 described below are the output terminals of the master latch unit 2 and also the input terminals of the slave latch unit 1.

The PMOS transistor PM2 and the NMOS transistors NM1 and NM3 are disposed between the power supply voltage terminal VDD and the drain terminal N5 of the NMOS transistor NM5. The NMOS transistor NM5 operates in response to the clock signal CLK.

The PMOS transistor PM2 and the gate terminal of the NMOS transistor NM1 are commonly connected to the output node N2, and an input signal D is applied to the gate terminal of the NMOS transistor NM3.

The PMOS transistor PM4 is disposed between the power supply voltage terminal VDD and the output node N2 and operates in response to the clock signal CLK.

The PMOS transistor PM3 and the NMOS transistors NM2 and NM4 are disposed between the power supply voltage terminal VDD and the drain terminal N5 of the NMOS transistor NM5.

The gate terminal of the PMOS transistor PM3 and the NMOS transistor NM2 is commonly connected to the output node N1, and an input signal / D is applied to the gate terminal of the NMOS transistor NM4. .

A conventional sense amplifier based flip flop having the master latch unit 2 and a slave latch 1 connected thereto is also called a sense amp D flip flop. This is because the sense amplifier-based flip-flop operates as a D flip-flop to which the input signals D and / D are applied to output delayed output signals Q and / Q in response to the clock signal CLK. .

The operation of the sense amplifier based flip-flop circuit is described below.

When the clock signal CLK is at the low level, the output nodes N1 and N2 are at the high level regardless of the data signal D. That is, when the clock signal CLK is at the low level, the output node N1 is turned high by turning on the PMOS transistor PM1, and the output node N2 is turned on by the PMOS transistor PM4. This results in a high level.

At this time, since the input signals S and R are all at the high level, the output signals Q and / Q of the slave latch unit 1 hold the previous values as they are. This is a precharge state.

When the clock signal CLK goes high, the voltages of the output nodes N1 and N2 are determined according to the logic state of the input signal D.

For example, when the clock signal CLK is at a high level and the input signal D is at a high level, the output node N1 is at a low level and the output node N2 is at a high level.

On the other hand, when the clock signal CLK is at a high level and the input signal D is at a low level, the output node N1 is at a high level and the output node N2 is at a low level.

That is, output nodes N1 and N2 are precharged when the clock signal CLK is at a low level, and signal levels of the output nodes N1 and N2 are input when the clock signal CLK is at a high level. It depends on the signal D. An interval when the clock signal CLK is at a high level is called an evaluation period, and the master latch unit 2 is in an evaluation state in the evaluation period. The output signals of the output nodes N1 and N2 at this time are referred to as evaluation signals.

In the sense amplifier based flip-flop, a problem occurs when the level of the input signal D changes while the clock signal CLK maintains a high level.

That is, the problem will be described with reference to Table 1 below and FIG. 2.

Table 1

L is low level, H is high level, X is don't care, and F is floating state.

Table 1 summarizes the operation of the flip-flop of the sense amplifier in FIG. 1, and FIG. 2 is a timing diagram illustrating the operation of the flip-flop of the sense amplifier.

As shown in Table 1 and FIG. 2, when the input signal D is changed while the clock signal CLK is at a high level, the output node N1 and the node N3 are floating although they are at a low level. Low level of the floating state. That is, since the NMOS transistor NM3 is turned off, the node N3 is in a floating state, and thus the output node N1 is also in a floating state. The floating state means that the signal levels of the output nodes N1 and N3 can be easily changed by external factors. This is the state of the output node N1 and node N3 in the period t2 in FIG. 2. That is, although the output nodes N1 and N2 and the nodes N3 and N4 are shown as having a specific level in the interval t2, these levels are easily changed by external factors.

In addition, although only the case where the input signal D is changed from the high level to the low level is shown in Table 1, the output node N1 is not changed even when the input signal D is changed from the low level to the high level. With the output node N2, the remainder is the same except that node N3 is changed to node N4.

As described above, the floating state may destabilize operation of the circuit or cause data loss.

An example of a conventional sense amplifier based flip-flop for preventing such a floating state is shown in FIG. 3.

That is, FIG. 3 is a sense amplifier based flip flop in which the NMOS transistor NM15 is added to prevent the output nodes N1 and N2 from floating in the sense amplifier based flip flop in FIG. 1. 4 is a timing diagram illustrating an operation of the sense amplifier based flip flop of FIG. 3.

First, referring to FIG. 3, the same as that of the sense amplifier based flip-flop of FIG. 1 except that the NMOS transistor NM16 is added between the node N13 and the node N14 in the master latch unit 12. Therefore, duplicate descriptions are omitted.

The NMOS transistor NM16 connected between the node N13 and the node N14 in the master latch unit 12 includes a gate terminal to which a power supply voltage VDD is always applied, a node N13 and a node N14. It has a drain and source terminal connected to. In other words, the NMOS transistor NM16 is always turned on in the circuit configuring the master latch unit 12.

Here, the NMOS transistor NM16 is a transistor having a relatively smaller driving capability than the NMOS transistors NM11, NM12, NM13, NM14, and NM15. The reason is that the NMOS transistor NM16 is always turned on to prevent the floating of the nodes N11 and N12, so that the NMOS transistor NM16 evaluates the master latch unit 12, that is, the sense amplifier. This is to reduce the effect.

As described above, in the sense amplifier-based flip-flop illustrated in FIG. 3, when the input signal D is changed while the clock signal CLK is at a high level due to the addition of the NMOS transistor NM15 (that is, the input signal D). Output node N11, N12 or node N13 in the sense amplifier based flip-flop, even when is changed from a high level to a low level or the input signal D is changed from a low level to a high level). N14) is prevented from floating.

A change in the level of the output nodes N11 and N12 or the nodes N13 and N14 will be described in detail with reference to FIGS. 3 and 4 as follows.

First, when the clock signal CLK is at the low level, since the PMOS transistors PM11 and PM14 are turned on, the output nodes N11 and N12 and the nodes N13 and N14 are independent of the input signals D and / D. Maintain high level. At this time, the NMOS transistors NM11 and NM12 are turned on and the PMOS transistors PM12 and PM13 are turned off.

When the clock signal CLK transitions to a high level, the PMOS transistors PM11 and PM14 are turned off, and the NMOS transistor NM15 is turned on. Here, assuming that the input signal D is at the high level, the output node N11 is at the low level, and the output node N12 maintains the high level as it is (A11). Since the NMOS transistor NM16 is always turned on, the node N14 descends along the level of the node N13 (A15).

That is, a current path along the node N14, the NMOS transistor NM16, the node N13, the NMOS transistor NM13, the node N15, and the NMOS transistor NM15 is generated. The level of N14 becomes equal to the level of the node N13 after a predetermined time (actually, the threshold voltage of the NMOS transistor NM16 should be taken into account, but the same level only in the high or low level) Can be seen as.).

Even if the level of the input signal changes while the clock signal CLK maintains the high level, the levels of the nodes N13 and N14 do not change. This is because the NMOS transistor NM16 is always turned on. Thus, the floating phenomenon of the output nodes N11 and N12 as in FIG. 1 is prevented.

Rather than the case where the input signal D and the input signal / D show opposite logic levels, the degree of turning on the NMOS transistor NM13 is such that the input signal D is turned on. The same applies to the case where D) is stronger than the degree of turning on the NMOS transistor NM14.

That is, when the NMOS transistor NM13 is turned on more strongly, the nodes N13 and N11 are at a low level, and the nodes N12 and N14 are at a high level. In this state, even if the level of the input signal D becomes a level at which the NMOS transistor NM13 is turned off (of course, the NMOS transistor NM14 is caused by the input signal / D). Must be turned on.) Since the NMOS transistor NM16 is turned on, the node N13 is not floated. Thus, the node N11 is prevented from floating.

However, the voltage difference between nodes N13 and N14, which changes in response to the clock signal CLK after the clock signal CLK transitions to a high level, as in g1 and g2 in the timing diagrams of nodes N13 and N14 shown in FIG. 4, is significantly reduced. Thus, the voltage difference between the output nodes N11 and N12 is reduced, thereby lowering the input sensitivity.

The input sensitivity generally requires a predetermined level difference between two signals in order for the sense amplifier to perform a sensing operation. The input sensitivity refers to a sense amplifier's ability to sense and amplify a small level difference between the two signals.

That is, since the NMOS transistor NM16 is employed in a sense amplifier based flip-flop, the NMOS transistor NM16 reduces the voltage difference between the node N13 and the node N14 during evaluation. As a result, the input sensitivity of the sense amplifier is significantly lowered. This may cause a malfunction of the sense amplifier based flip-flop.

Accordingly, there is an urgent need for a flip-flop based on a sense amplifier in which the output node, that is, the output terminal of the master latch unit does not float and the input sensitivity does not decrease.

Accordingly, an object of the present invention is to provide a sense amplifier circuit and a sense amplifier based flip-flop having the same for improving the problem that the output terminal, that is, the input terminal of the slave latch unit, becomes floating as described above.

Another object of the present invention is to provide a sense amplifier circuit having a stable operation and reducing data loss and a sense amplifier based flip-flop having the same.

Another object of the present invention is to provide a sense amplifier circuit and a sense amplifier based flip-flop having the same to improve the problem that the input sensitivity of the sense amplifier is reduced.

In order to achieve the above objects, a sense amplifier based flip-flop operating in response to a clock signal according to an aspect of the present invention may provide a second level signal regardless of an input signal pair when the clock signal is a first level. A first latch unit configured to output to a first output terminal and to output an evaluation signal pair corresponding to the input signal pair to the first output terminal when the clock signal has a second level; A second latch unit configured to latch the evaluation signal pair output from the first output terminal and then output the second signal to the second output terminal; And a floating prevention unit controlled by a signal of the first output terminal and operatively connected between current passing nodes of the first latch unit to prevent floating of the first output terminal.

Here, the first level may be a low level, and the second level may be a high level.

The first latch unit may include a first node configured to be at a high level when the clock signal is at a low level, and have a first evaluation signal when the clock signal is at a high level; And a second node having a high level when the clock signal is a low level and having a second evaluation signal when the clock signal is a high level, wherein the first node and the second node are the first output terminal and the The first evaluation signal and the second evaluation signal may be the evaluation signal pairs.

The floating prevention unit may be turned off when the output signal of the first node and the output signal of the second node are both at a high level, and any one of an output signal of the first node and an output signal of the second node is turned off. If is at the low level it can be turned on.

The floating prevention unit may be configured to apply an inverted signal of an output signal of the first node to a gate terminal of one NMOS transistor and an inverted signal of an output signal of the second node to a gate terminal of another NMOS transistor. It may be provided with two NMOS transistors which are applied and whose source and drain terminals are commonly connected.

In addition, the floating prevention unit, the output signal of the first node is applied to the gate terminal of one PMOS transistor and the output signal of the second node is applied to the gate terminal of the other PMOS transistor and their source and drain The terminals may include two PMOS transistors connected in common.

The floating prevention unit may be a transmission gate controlled by an inverted signal of the output signal of the first node and an output signal of the second node.

The first latch unit may include a first PMOS transistor disposed between a power supply voltage terminal and the first node and turned on or off in response to the clock signal; A second PMOS transistor disposed between the power supply voltage terminal and the first node and having a gate terminal connected to the second node; A first NMOS transistor disposed between the first node and a third node and having a gate terminal connected to the second node; A third PMOS transistor disposed between the power supply voltage terminal and the second node and having a gate terminal connected to the first node; A fourth PMOS transistor disposed between the power supply voltage terminal and the second node and turned on or off in response to the clock signal; A second NMOS transistor disposed between the second node and a fourth node and having a gate terminal connected to the first node; A third NMOS transistor disposed between the third node and the fifth node and controlled by a first input signal that is one of the input signal pairs; A fourth NMOS transistor disposed between the fourth node and the fifth node and controlled by a second input signal that is another one of the input signal pairs; And a fifth NMOS transistor disposed between the fifth node and a ground terminal and turned on or off in response to the clock signal.

The third node and the fourth node may be current passing nodes of the first latch unit.

In addition, the floating prevention unit may be operatively connected between the third node and the fourth node.

In order to achieve the above objects, a sense amplifier circuit operates in response to a clock signal and senses and amplifies an input signal pair and generates an output signal pair corresponding thereto according to an aspect of the present invention. Disposed between one node and the other between the power supply voltage terminal and a second node such that the voltage at the first node and the voltage at the second node are at the second level when the clock signal is at the first level. A pair of precharge enable switch units; A latch unit including a first inverter having the first node as an output terminal and the second node as an input terminal, and a second inverter having the first node as an input terminal and the second node as an output terminal; A floating prevention unit controlled by an output signal of the first node and an output signal of the second node and operatively connected between the current passing nodes of the latch unit to prevent floating of the first node or the second node ; And an input signal applying unit disposed between the current passing node of the latch unit and the ground terminal to receive the input signal pairs, respectively.

The current passing node may be a third node that is one end of a first NMOS transistor constituting the first inverter and a fourth node that is one end of a second NMOS transistor constituting the second inverter.

The floating prevention unit may be turned off when the output signal of the first node and the output signal of the second node are both at a high level, and any one of an output signal of the first node and an output signal of the second node is turned off. If is at the low level it can be turned on.

In addition, a ground switch may be provided between the input signal applying unit and the ground terminal to be turned on or off by the clock signal.

The input signal applying unit may include: a first input transistor disposed between the third node and the ground switch unit to receive a first input signal which is one of the input signal pairs; And a second input transistor disposed between the fourth node and the ground switch unit to receive a second input signal which is one of the input signal pairs.

The sense amplifier circuit may further include a voltage fluctuation preventing unit for stabilizing voltages of the third node and the fourth node when the clock signal is at a low level.

The voltage fluctuation preventing part may include: a fifth PMOS transistor having a clock signal applied to a gate terminal, a power supply voltage applied to a source terminal, and a drain terminal connected to the third node; The clock signal may be applied to a gate terminal, a power supply voltage may be applied to a source terminal, and the drain terminal may include a sixth PMOS transistor connected to the fourth node.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The accompanying drawings and the following description are by way of example only and are intended to assist those of ordinary skill in the art to understand the present invention. Accordingly, the following descriptions should not be used to limit the scope of the invention.

FIG. 5 is a circuit diagram illustrating a flip-flop based on a sense amplifier according to an embodiment of the present invention, and FIG. 6 is a timing diagram illustrating an operation of the flip-flop based on the sense amplifier of FIG. 5.

First, referring to FIG. 5, a sense amplifier based flip-flop that operates in response to a clock signal CLK may be floated to prevent floating of the first latch unit 22, the second latch unit 20, and an output node. The prevention part 100 is provided.

The first latch unit 22 is disposed between the power supply voltage terminal VDD and the first node N21 and is turned on or off in response to a clock signal CLK. A second PMOS transistor PM22 disposed between the voltage terminal VDD and the first node N21 and having a gate terminal connected to the second node N22, and the first node N21 and the third node ( The first NMOS transistor NM21 is disposed between the N23 and the gate terminal is connected to the second node N22.

In addition, the first latch unit 22 is disposed between the power supply voltage terminal VDD and the second node N22 and a third PMOS transistor PM23 having a gate terminal connected to the first node N11. A fourth PMOS transistor PM24 disposed between the power supply voltage terminal VDD and the second node N22 and turned on or off in response to the clock signal CLK, and the second node N22. ) And a second NMOS transistor NM22 disposed between the fourth node N24 and a gate terminal connected to the first node N21.

In addition, the first latch unit 22 is disposed between the third node N23 and the fifth node NM25 and is controlled by the third NMOS transistor NM23 and the third node in response to an input signal D. And a fourth NMOS transistor NM24 connected between a fourth node N24 and the fifth node NM25 and controlled in response to an inversion signal / D of the input signal D.

In addition, the first latch unit 22 includes a fifth NMOS transistor NM25 disposed between the fifth node N25 and the ground terminal and turned on or off in response to the clock signal CLK. .

Here, the first node N21 and the second node N22 become first output terminals S and R. The first output terminals S and R are output terminals of the first latch unit 22 and input terminals of the second latch unit 20. Thus, when the clock signal CLK is at the first level, the first latch unit 22 outputs a signal having a second level to the first output terminal S or R regardless of the level of the input signal pairs D and / D. When the clock signal CLK is at the second level, an evaluation signal pair corresponding to the input signal is output to the first output terminals S and R.

The first level may be a low level and the second level may be a high level. Hereinafter, for convenience of description, the case where the first level is a low level and the second level is a high level will be described by way of example.

The second latch unit 20 latches the pair of evaluation signals output from the first output terminals S and R and then outputs them to the second output terminals Q and / Q. The second latch unit 20 may include an SR latch. The SR latch is also referred to as RS flip-flop, an example of which is illustrated in FIG. 9 and will be described later with reference to FIG. 9.

The floating prevention unit 100 is operatively connected between the current passing nodes of the first latch unit 22. The current passing node is a third node N23 and a fourth node N24 in the first latch unit 22. The floating prevention unit 100 is turned off when the output signal of the first node N21 and the output signal of the second node N22 are both at a high level, and the output signal of the first node N21 is turned off. And when any one of the output signals of the second node N22 is at a low level. Thus, by preventing the third node N23 or the fourth node N24 from floating, the first node N21 or the second node N22 which is the first output terminals S and R is prevented from floating. Prevents floating. Detailed examples of the floating prevention unit 100 are illustrated in FIGS. 7 and 8, and thus, the floating prevention unit 100 will be described in more detail with reference to FIGS. 6 and 7.

5 and 6, a detailed operation of a sense amplifier based flip-flop including the first latch unit 22, the second latch unit 20, and the floating prevention unit 100 will be described below. Same as

First, when the clock signal CLK is at a low level (section t11), the first PMOS transistor PM21 and the fourth PMOS transistor PM24 are turned on so that the first node N21 and the second node N22 are turned on. ) Becomes the high level. The second PMOS transistor PM22 and the third PMOS transistor PM23 are turned off, and the first NMOS transistor NM21 and the second NMOS transistor NM22 are turned on. Since the fifth NMOS transistor NM25 is turned off, the third node N23 and the fourth node N24 maintain a high level. In addition, since the output signals S and R of the first node N21 and the second node N22 are both at a high level, the floating prevention unit 100 is turned off. At this time, the state of the sense amplifier based flip-flop can be seen as a precharge state.

When the clock signal CLK transitions to a high level (section t12), in response to the clock signal CLK (see A101), the first node N21 sets a level corresponding to the input signal D. The second node N22 has a level opposite to that of the first node N21. Here, the level corresponding to the input signal D does not mean that the level is the same as the level of the input signal D, but rather the evaluation signal according to the level of the input signal D.

For example, when the input signal D is at a high level, the third NMOS transistor NM23 is turned on and the fourth NMOS transistor NM24 is turned off. Thus, the first node N21 goes low and the second node N22 goes high. On the contrary, when the input signal D is at the low level, the third NMOS transistor NM23 is turned off and the fourth NMOS transistor NM24 is turned on, so that the first node N21 is high. Level, the second node N22 is at a low level.

Meanwhile, the input signal pairs D and / D are turned on of the third NMOS transistor NM23 and the fourth NMOS transistor NM24 instead of a logic level that can be distinguished between a high level and a low level. It may also be the case of having different levels. For example, when the input signal D has a higher level than the input signal / D, the third NMOS transistor NM23 is turned on more strongly than the fourth NMOS transistor NM24, Eventually, the first node N21 goes low and the second node N22 goes high.

Although the input signal pairs D and / D are viewed as signals having complementary levels with each other, otherwise, the first node N21 and the second node have a slight difference as described above. Since the final level of N22 has the same result, the input signal pairs D and / D are considered to be complementary to each other and will be described below.

Next, in the period t12, the third node N23 and the fourth node N24 show waveforms such as g101 and g102 in response to the clock signal CLK. For example, when the clock signal CLK transitions to a high level and the input signal D is at a high level, the third node N23 gradually drops to a low level (g101). Then, the floating prevention unit 100 is turned on, and the fourth node N24 also gradually drops to a low level (g102). That is, since the floating prevention unit 100 is turned on, a path to the fourth node N24, the third node N23, the fifth node N25, and the ground terminal is generated. In this state, even if the input signal D changes to a low level, the floating phenomenon of the node N1 due to the floating phenomenon of the node N3 does not occur as in the conventional sense amplifier based flip flop shown in FIG. 1. Do not.

In addition, the floating prevention unit 100 in the present invention can also improve the problem that the input sensitivity is also reduced as shown in the timing diagram of N13, N14 in FIG. Looking at g1, g2 in FIG. 4 and g101, g102 in FIG. 6, the difference is prominent. That is, since the signal level difference between the nodes N23 and N24 is closely related to the input sensitivity of the sense amplifier, that is, the first latch unit 22, in FIG. 4, since g1 and g2 have almost no signal level difference, the input sensitivity is lowered. This can cause a malfunction of the sense amplifier. However, since the present invention exhibits the same operating characteristics as g101 and g102 in Fig. 6, the input sensitivity does not decrease.

Finally, when the clock signal CLK transitions to the low level again (section t13), the fifth NMOS transistor NM25 is turned off, and the first PMOS transistor PM21 and the fourth PMOS transistor PM24 are turned off. Is turned on so that the first node N21 and the second node N22 are at a high level.

FIG. 7 is a circuit diagram illustrating an embodiment of the floating prevention unit 100 in FIG. 5.

5 and 7, the floating prevention unit 100 includes two NMOS transistors NM100 and NM102.

The inversion signal / S of the output signal of the first node N21 is applied to the gate terminal of one NMOS transistor NM100, and the output of the second node is applied to the gate terminal of the other NMOS transistor NM102. The inverted signal / R of the signal is applied. The source and drain terminals of the two NMOS transistors NM100 and NM102 are connected in common and are disposed between the third node N23 and the fourth node N24.

If the clock signal CLK is at a low level, that is, when the output signal S of the first node N21 and the output signal R of the second node N22 are high level, the NMOS transistor NM100, NM102 is turned off. Thus, the third node N23 and the fourth node N24 are separated.

If the clock signal CLK transitions to a high level, one of the NMOS transistors NM100 and NM102 is turned on to connect the third node N23 and the fourth node N24. Therefore, when the level of the input signal D is changed in this state, the third node N23 or the fourth node N24 is prevented from floating, and eventually, the second latch is an output terminal of the first latch portion 22. The floating of the first node N21 or the second node N22, which is an input terminal of the unit 20, is prevented.

In addition, unlike the case where the NMOS transistor (NM16 in FIG. 3), which is always turned on, is connected between nodes (N13 and N14 in FIG. 3), such as a conventional sense amplifier based flip flop shown in FIG. The input sensitivity may be improved by turning off the output signals of the first node N21 and the second node N22, which are output terminals of the first latch unit 22, at a high level. Thus, the data loss problem due to the malfunction of the sense amplifier based flip-flop can be reduced.

FIG. 8 is a circuit diagram illustrating another embodiment of the floating prevention unit in FIG. 5.

In FIG. 8, the floating prevention unit 100 includes two PMOS transistors PM100 and PM102.

The output signal S of the first node N21 is applied to the gate terminal of one PMOS transistor PM100, and the output of the second node N22 is applied to the gate terminal of the other PMOS transistor PM102. Signal R is applied. In addition, the source and drain terminals of the two PMOS transistors PM100 and PM102 are connected in common and are connected to the third node N23 and the fourth node N24.

In the floating prevention unit 100 illustrated in FIG. 8, the control signal is inverted as S, R and / S, / R when compared to the floating prevention unit 100 illustrated in FIG. Except for the different points as the MOS transistors PM100 and PM102 and the NMOS transistors NM100 and NM102, the operation is the same and detailed description thereof will be omitted.

Although not shown, the floating prevention unit 100 may be a transmission gate controlled by an inverted signal of the output signal of the first node N21 and an output signal of the second node N22. That is, the transfer gate is a conventional CMOS type transfer gate, and may be formed of one NMOS transistor and one PMOS transistor.

As illustrated in FIGS. 7 and 8, the floating prevention unit 100 is controlled by the output signals of the first node N21 and the second node N22, and the third node N23 and the fourth node ( By being operatively connected between N24, the output terminal of the first latch portion 22 is prevented from floating and the input sensitivity is improved.

FIG. 9 is a circuit diagram illustrating an example of the second latch unit 20 in FIG. 5.

Referring to FIG. 9, the SR latch constituting the second latch unit 20 is output from a latch 120 including two inverters INV21 and INV22 and an output terminal of the first latch unit 22 (FIG. 5). And NMOS transistors NM28, NM29, NM26, and NM27, which are controlled and controlled by the signals S and R and their inverted signals / S and / R.

If the logic set of the output signals S and R of the first latch unit 22 of FIG. 5 is at a high / low or low / high level, the second latch unit 20 may be configured as the first latch unit 20. An output signal corresponding to the output signals S and R of the latch unit is output to the output terminals Q and / Q. In addition, the case where the logic set of the output signals S and R is at a low / low level is not defined. When the logic set of the output signals S and R is at the high / high level, the sense amplifier based flip flop of FIG. 5 is in a precharge state.

10 is a circuit diagram illustrating a flip-flop based on a sense amplifier according to a modified embodiment of the present invention.

Referring to FIG. 10, the sense amplifier based flip-flop includes a first latch part 32, a second latch part 30, and a floating prevention part 100. The second latch unit 30 and the floating prevention unit 100 have the same configuration and operation as those shown in FIG. 5, and the first latch unit 32 also excludes the voltage variation prevention units PM35 and PM36. Since the configuration and operation are the same as those shown in FIG. 5, the description of the remaining portions other than the voltage variation preventing units PM35 and PM36 will be omitted.

The sense amplifier based flip flop may further include the voltage variation preventing units PM35 and PM36 in the sense amplifier based flip flop illustrated in FIG. 5. That is, the voltage variation preventing units PM35 and PM36 each include a master latch unit ie, a third node N33 and a fourth node N34 of the first latch unit 32 constituting the sense amplifier based flip-flop. It is connected to the third node N33 and the fourth node (N34) serves to prevent voltage fluctuations, in particular voltage drops.

The voltage variation preventing unit includes a fifth PMOS transistor PM35 and a sixth PMOS transistor PM36 controlled by the clock signal CLK.

When the clock signal CLK is at the low level, in order to prevent the voltages of the third node N33 and the fourth node N34 from being lowered by a threshold voltage due to the NMOS transistors NM31 and NM32, The fifth PMOS transistor PM35 and the sixth PMOS transistor PM36 are turned on.

When the clock signal CLK transitions to the low level, both the fifth PMOS transistor PM35 and the sixth PMOS transistor PM36 are turned off. Therefore, in this case, the fifth PMOS transistor PM35 and the sixth PMOS transistor PM36 do not affect the signal levels of the third node N33 and the fourth node N34.

The sense amplifier based flip flop according to the present invention has been described as described above, hereinafter, a sense amplifier circuit constituting the sense amplifier based flip flop will be described.

Referring to FIG. 5, the first latch unit 22 constituting the sense amplifier based flip flop may be viewed as a current sensing sense amplifier. In the above descriptions, the first latch portion 22 and the floating prevention portion 100 are described as separate components. Hereinafter, the first latch portion 22 and the floating prevention portion 100 are sensed as one component. It was explained by the amplifier circuit.

Accordingly, the sense amplifier circuit for detecting and amplifying an input signal and generating an output signal corresponding thereto according to an embodiment of the present invention includes a pair of precharge enable switch units PM21 and PM24 and latch units PM22 and PM23. And NM21 and NM22, floating prevention unit 100, input signal applying units NM23 and NM24, and grounding switch unit NM25.

The precharge enable switch units PM21 and PM24 include two PMOS transistors PM21 and PM24. One PMOS transistor PM21 is connected between the power supply voltage terminal VDD and the first node N21 and the other is connected between the power supply voltage terminal VDD and the second node N22 and a clock signal. When the CLK is at the low level, the voltages of the first node N21 and the second node N22 are at a high level.

The latch units PM22, PM23, NM21, and NM22 are composed of two inverters. A first inverter including a PMOS transistor PM22 and an NMOS transistor NM21 has the first node N21 as an output terminal and the second node N22 as an input terminal. The second inverter including the PMOS transistor PM23 and the NMOS transistor NM22 has the first node N21 as an input terminal and the second node N22 as an output terminal.

The floating prevention unit 100 is controlled by an output signal of the first node N21 and an output signal of the second node N22 to be turned on or off, thereby forming the NMOS transistor NM21 constituting the first inverter. Is connected between the third node N23, which is one end of N, and the fourth node N24, which is one end of the NMOS transistor NM22 constituting the second inverter. That is, when the clock signal CLK is at the low level, the floating prevention unit 100 is turned off, and when the clock signal CLK is at the high level, the floating prevention unit 100 is turned on. As shown in FIG. 7, the floating prevention unit 100 receives an inversion signal / S of an output signal of the first node N21 and a gate terminal of one NMOS transistor NM100. The gate terminal of the NMOS transistor NM102 may include two NMOS transistors to which the inverted signal / R of the output signal of the second node N22 is applied and their source and drain terminals are commonly connected. In addition, as shown in FIG. 8, the floating prevention unit 100 receives an output signal S of the first node N21 to the gate terminal of one PMOS transistor PM100 and the other PMOS. An output signal R of the second node N22 may be applied to a gate terminal of the transistor PM102, and two PMOS transistors may be commonly connected to their source and drain terminals.

The input signal applying units NM23 and NM24 are connected between the third node N23 and the fifth node N25 to receive a first input signal D, and an input transistor NM23 and the fourth node. An input transistor NM24 connected between an N24 and the fifth node N25 to receive a second input signal / D.

For example, when the clock signal CLK is at a high level and the level of the first input signal D is higher than the level of the second input signal / D, the input transistor NM23 may be configured to be at the high level. It is turned on more strongly than the input transistor NM24. Therefore, the third node N23 and the first node N21 become low level, and the second node N22 remains high level. At this time, the floating prevention unit 100 is turned on.

Thereafter, even when the level of the first input signal D is changed to the low level so that the input transistor NM23 is turned off (of course, in this case, the second input signal / D is the input signal). The third node N23 is not floated due to the level of the transistor NM24 being turned on and the floating prevention unit 100 being turned on. Therefore, the first node N21 also does not float.

The ground switch unit NM25 is connected between the fifth node N25 and the ground terminal and controlled by the clock signal CLK to be turned on or off. That is, the ground switch unit NM25 is turned on when the clock signal CLK is at a high level, and is turned off when the clock signal CLK is at a low level.

In addition, as illustrated in FIG. 10, when the clock signal CLK is at the low level, the sense amplifier circuit may include voltage variation preventing units PM35 and PM36 for stabilizing voltages of the nodes N33 and N34. It may be further provided.

Since the operation of the other sense amplifier circuit has been sufficiently described in the first latch units 22 and 32 and the floating prevention unit 100 described above with reference to FIGS. 5 to 10, redundant description thereof will be omitted.

The sense amplifier circuit and the flip-flop based flip flop having the sense amplifier according to the present invention may not only be employed in an input / output (I / O) sense amplifier in a semiconductor memory device, a sense amplifier in a data write path, etc. In particular, it can be widely adopted in a system requiring high speed and stable operation.

The sense amplifier circuit and the flip-flop based sense amplifier having the same according to the present invention are not limited to the above embodiments and may be variously designed and applied without departing from the basic principles of the present invention. It will be obvious to those skilled in the art.

As described above, the present invention has the effect of improving the problem that the output terminal, that is, the input terminal of the slave latch unit is in a floating state by providing a sense amplifier circuit and a sense amplifier based flip flop having the same.

In addition, the present invention provides a sense amplifier circuit and a sense amplifier based flip-flop having the same, thereby improving the problem of data loss and degradation of input sensitivity.

Claims (20)

A sense amplifier based flip-flop that operates in response to a clock signal: When the clock signal is the first level, a signal of the second level is output to the first output terminal regardless of the input signal pair. When the clock signal is the second level, the evaluation signal pair corresponding to the input signal pair is generated. A first latch unit outputting to one output terminal; A second latch unit configured to latch the evaluation signal pair output from the first output terminal and then output the second signal to the second output terminal; And And a floating prevention part controlled by a signal of the first output terminal and operatively connected between current passing nodes of the first latch unit to prevent floating of the first output terminal. . The method of claim 1, And a first level is a low level, and the second level is a high level. The method of claim 2, wherein the first latch unit, A first node that is at a high level when the clock signal is at a low level and has a first evaluation signal when the clock signal is at a high level; And And a second node having a high level when the clock signal is at a low level, and having a second evaluation signal when the clock signal is at a high level. And the first node and the second node are the first output terminal and the first evaluation signal and the second evaluation signal are the evaluation signal pairs. The method of claim 3, The floating prevention unit is turned off when the output signal of the first node and the output signal of the second node are both at a high level, and any one of the output signal of the first node and the output signal of the second node is low. In the case of a level, a flip-flop based on a sense amplifier, characterized in that turned on. The method of claim 4, wherein the floating prevention unit, The inverted signal of the output signal of the first node is applied to the gate terminal of one NMOS transistor, and the inverted signal of the output signal of the second node is applied to the gate terminal of the other NMOS transistor, and their source and drain terminals are applied. A sense amplifier based flip-flop, comprising two NMOS transistors connected in common. The method of claim 4, wherein the floating prevention unit, The output signal of the first node is applied to the gate terminal of one PMOS transistor, and the output signal of the second node is applied to the gate terminal of the other PMOS transistor, and two source and drain terminals thereof are connected in common. A sense amplifier based flip-flop, comprising a PMOS transistor. The method of claim 4, wherein And the floating prevention unit is a transmission gate controlled by an inverted signal of the output signal of the first node and an output signal of the second node. The method of claim 4, wherein the first latch unit, A first PMOS transistor disposed between a power supply voltage terminal and the first node and turned on or off in response to the clock signal; A second PMOS transistor disposed between the power supply voltage terminal and the first node and having a gate terminal connected to the second node; A first NMOS transistor disposed between the first node and a third node and having a gate terminal connected to the second node; A third PMOS transistor disposed between the power supply voltage terminal and the second node and having a gate terminal connected to the first node; A fourth PMOS transistor disposed between the power supply voltage terminal and the second node and turned on or off in response to the clock signal; A second NMOS transistor disposed between the second node and a fourth node and having a gate terminal connected to the first node; A third NMOS transistor disposed between the third node and the fifth node and controlled by a first input signal that is one of the input signal pairs; A fourth NMOS transistor disposed between the fourth node and the fifth node and controlled by a second input signal that is another one of the input signal pairs; And And a fifth NMOS transistor disposed between the fifth node and a ground terminal and turned on or off in response to the clock signal. The method of claim 8, And a third node and a fourth node are current passing nodes of the first latch unit. The method of claim 8, And the floating prevention part is operatively connected between the third node and the fourth node. A sense amplifier circuit that operates in response to a clock signal and senses and amplifies an input signal pair to produce an output signal pair corresponding thereto: One is disposed between the power supply voltage terminal and the first node and the other is disposed between the power supply voltage terminal and the second node so that the voltage of the first node and the voltage of the second node when the clock signal is at the first level. A pair of precharge enable switch sections to be at the second level; A latch unit including a first inverter having the first node as an output terminal and the second node as an input terminal, and a second inverter having the first node as an input terminal and the second node as an output terminal; A floating prevention unit controlled by an output signal of the first node and an output signal of the second node and operatively connected between the current passing nodes of the latch unit to prevent floating of the first node or the second node ; And And an input signal applying unit arranged between the current passing node of the latch unit and a ground terminal to receive the input signal pairs, respectively. The method of claim 11, wherein the current passing node, And a third node as one end of the first NMOS transistor constituting the first inverter and a fourth node as one end of the second NMOS transistor constituting the second inverter. The method of claim 11, And the first level is a low level and the second level is a high level. The method of claim 13, The floating prevention unit is turned off when the output signal of the first node and the output signal of the second node are both at a high level, and any one of the output signal of the first node and the output signal of the second node is low. If the level is sense amplifier circuit, characterized in that turned on. The method of claim 14, And a grounding switch unit between the input signal applying unit and the ground terminal to be turned on or off by the clock signal. The method of claim 15, wherein the input signal applying unit, A first input transistor disposed between the third node and the ground switch unit to receive a first input signal which is one of the input signal pairs; And And a second input transistor disposed between the fourth node and the ground switch to receive a second input signal which is one of the input signal pairs. The method of claim 14, The floating prevention unit is configured to apply an inverted signal of the output signal of the first node to a gate terminal of one NMOS transistor and an inverted signal of the output signal of the second node to a gate terminal of another NMOS transistor. A sense amplifier circuit comprising two NMOS transistors whose source and drain terminals are connected in common. The method of claim 14, wherein the floating prevention unit, The output signal of the first node is applied to the gate terminal of one PMOS transistor, and the output signal of the second node is applied to the gate terminal of the other PMOS transistor, and two source and drain terminals thereof are connected in common. A sense amplifier circuit comprising a PMOS transistor. The method of claim 11, The sense amplifier circuit further includes a voltage variation preventing unit for stabilizing voltages of the third node and the fourth node when the clock signal is at a low level. The method of claim 19, wherein the voltage fluctuation prevention unit, A fifth PMOS transistor having a clock signal applied to a gate terminal, a power supply voltage applied to a source terminal, and a drain terminal connected to the third node; And And the clock signal is applied to a gate terminal, a power supply voltage is applied to a source terminal, and a drain terminal has a sixth PMOS transistor connected to the fourth node.

Images