CN118072789A - Sense amplifier circuit and resistive random access memory device - Google Patents

Abstract

The application discloses a sensitive amplifier circuit and a resistive random access memory device, and relates to the technical field of memories, wherein the sensitive amplifier circuit comprises: a current source for generating a first driving current; the signal amplifying unit is electrically connected with the current source and is used for generating a first amplified signal and a second amplified signal according to the potential difference of the input signal and the first driving current; the first control unit is electrically connected with the first output node and the second output node respectively and is used for transmitting a first output signal to the first output node according to a first clock signal and transmitting a second output signal to the second output node according to the first clock signal; the signal output unit is electrically connected with the signal amplifying unit and the first control unit respectively, and is used for generating a first output signal according to the first amplified signal and transmitting the first output signal to the first control unit, and is also used for generating a second output signal according to the second amplified signal and transmitting the second output signal to the first control unit.

Description

Sense amplifier circuit and resistive random access memory device

Technical Field

The present application relates to the field of memory technologies, and in particular, to a sense amplifier circuit and a resistive random access memory device.

Background

Because of the current trend of miniaturization and light weight of memory architecture, and the density of memory arrays is increasing, and accordingly, the read current of data signals is decreasing, a sense amplifier capable of amplifying weak signals is becoming indispensable. For example, in an in-memory computing architecture based on SRAM (STATIC RAM, static memory), a sense amplifier is an extremely important circuit whose function is mainly to amplify and output differential data of a data bit line pair.

However, with the development of technology, the requirements on the reading and writing speeds of the memory are higher and higher, and the sense amplifier is an important component in the memory architecture, and the sensing speed of the sense amplifier plays an important role on the running speed of the memory.

Disclosure of Invention

The application provides a sense amplifier circuit and a resistive random access memory device, which can improve the sensing speed of the sense amplifier circuit.

In a first aspect, the present application provides a sense amplifier circuit comprising:

a current source for generating a first drive current;

The signal amplifying unit is electrically connected with the current source and is used for generating a first amplified signal and a second amplified signal according to an input signal potential difference and the first driving current, wherein the input signal potential difference is the potential difference of the first input signal and the second input signal received by the signal amplifying unit;

The first control unit is electrically connected with a first output node and a second output node respectively, and is used for transmitting the first output signal to the first output node according to a first clock signal and transmitting the second output signal to the second output node according to the first clock signal;

The signal output unit is respectively and electrically connected with the signal amplifying unit and the first control unit, and is used for generating the first output signal according to the first amplified signal and transmitting the first output signal to the first control unit, and is used for generating the second output signal according to the second amplified signal and transmitting the second output signal to the first control unit.

In some embodiments, the sense amplifier circuit further comprises:

And the second control unit is respectively and electrically connected with the first output node and the second output node, and is used for respectively transmitting a first reference voltage signal to the first output node and the second output node according to the first clock signal.

In some embodiments, the sense amplifier circuit further comprises:

The first interlocking unit is electrically connected with the first output node and the second output node respectively, and is used for transmitting the first reference voltage signal to the second output node according to the potential of the first output node and transmitting the first reference voltage signal to the first output node according to the potential of the second output node.

In some embodiments, the sense amplifier circuit further comprises:

The second interlocking unit is electrically connected with the first control unit, the first output node and the second output node respectively, and is used for controlling the output unit to transmit the second output signal to the first control unit according to the potential of the first output node and controlling the output unit to transmit the first output signal to the first control unit according to the potential of the second output node.

In some embodiments, the signal output unit includes:

a first transistor for generating the first output signal according to the first amplified signal and transmitting to the first control unit through a first electrode of the first transistor;

A second transistor for generating the second output signal according to the second amplified signal and transmitting to the first control unit through a second electrode of the second transistor;

The first transistor and the second transistor are electrically connected with the signal amplifying unit through gates, second electrodes of the first transistor and the second transistor are grounded, characteristics of the first transistor and the second transistor are the same, and the characteristics comprise switching characteristics.

In some embodiments, the signal amplifying unit includes:

The first output end of the differential amplifier is electrically connected with the grid electrode of the first transistor, the current receiving end of the differential amplifier is electrically connected with the current source, the first output end of the differential amplifier is used for transmitting the first amplified signal, the first input end of the differential amplifier is used for receiving the first input signal, and the second input end of the differential amplifier is used for receiving the second input signal;

And the input end of the inverter is electrically connected with the second output end of the differential amplifier, the output end of the inverter is electrically connected with the grid electrode of the second transistor, and the output end of the inverter is used for transmitting the second amplified signal.

In some embodiments, the signal amplification unit further comprises:

The input end of the transmission gate controller is electrically connected with the second output end of the differential amplifier, the output end of the transmission gate controller is electrically connected with the input end of the inverter, the first control end of the transmission gate controller is used for receiving the first clock signal, the second control end of the transmission gate controller is used for receiving the second clock signal, and the transmission gate controller is used for being controlled to be turned on or turned off under the control of at least one of the first clock signal and the second clock signal;

wherein the first clock signal and the second clock signal are opposite in potential.

In some embodiments, the differential amplifier comprises:

A third transistor having a gate for receiving the first input signal;

A fourth transistor, a gate of which is used for receiving the second input signal, and first electrodes of the third transistor and the fourth transistor are electrically connected with the current source;

a current mirror, an input end of which is electrically connected with the second electrode of the third transistor, and a mirror end of which is electrically connected with the second electrode of the fourth transistor;

The mirror end of the current mirror is electrically connected with the input end of the inverter, and the input end of the current mirror is electrically connected with the grid electrode of the first transistor.

In some embodiments, the current source comprises:

And a fifth transistor, wherein a gate of the fifth transistor is electrically connected with the input end of the current mirror, a first electrode of the fifth transistor is used for receiving a second reference voltage signal, and a second electrode of the fifth transistor is electrically connected with the first electrodes of the third transistor and the fourth transistor respectively.

In a second aspect, the present application provides a resistive random access memory device comprising:

A latch circuit;

a sense amplifier circuit as defined in any one of the first aspects;

the first output node of the sensitive amplifier circuit is electrically connected with the first input node of the latch circuit, and the second output node of the sensitive amplifier circuit is electrically connected with the second input node of the latch circuit.

In summary, the present application provides a sense amplifier circuit, comprising: the current source is used for generating a first driving current; the signal amplifying unit is electrically connected with the current source and is used for generating a first amplified signal and a second amplified signal according to the potential difference of the input signal and the first driving current, wherein the potential difference of the input signal is the potential difference of the first input signal and the second input signal received by the signal amplifying unit; the first control unit is electrically connected with the first output node and the second output node respectively, and is used for transmitting a first output signal to the first output node according to a first clock signal and transmitting a second output signal to the second output node according to the first clock signal; the signal output unit is respectively and electrically connected with the signal amplifying unit and the control unit, and is used for generating a first output signal according to the first amplified signal and transmitting the first output signal to the first control unit, and the signal output unit is used for generating a second output signal according to the second amplified signal and transmitting the second output signal to the first control unit. In a typical sense amplifier circuit, the signal input and the signal output of the sense amplifier circuit form a positive feedback stage, and the positive feedback needs to be adjusted by feedback after the whole circuit operates for a period of time, so that the sensing speed is slow, and a part of extra power consumption exists due to the need of a preheating process. Moreover, in some cases, some conventional sense amplifier circuits, in which the input node and the output node are directly connected, the amplified voltage difference is extremely susceptible to interference, and if there is some fluctuation in the time of operation of the control circuit, erroneous data output is likely to be caused. In the sense amplifier circuit, the nodes of the input signal and the output signal are isolated, so that the mutual interference of the input signal and the output signal can be reduced, the accuracy of output data is improved, the driving current is provided for the signal amplifying unit through the arrangement of the current source, the signal amplifying unit generates the first amplifying signal and the second amplifying signal according to the potential difference formed by the first input signal and the second input signal, and the potential difference of the first amplifying signal and the second amplifying signal is larger than the potential difference of the first input signal and the second input signal, therefore, positive feedback is not required to be provided for signal input through signal output, and the whole circuit can directly operate without preheating, so that the sensing speed can be improved.

Correspondingly, the resistive random access memory device provided by the embodiment of the application also has the technical effects.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for the purpose of illustrating preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

FIG. 1 is a schematic block diagram of a sense amplifier circuit provided by an embodiment of the present application;

FIG. 2 is a schematic block diagram of another sense amplifier circuit provided by an embodiment of the present application;

FIG. 3 is a schematic block diagram of a sense amplifier circuit provided by an embodiment of the present application;

fig. 4 is a schematic block diagram of a resistive random access memory device according to an embodiment of the present application.

Wherein, the names and reference numerals of the components in fig. 1 to 4 correspond to the following:

a 10-resistance-change memory device;

A 100 sense amplifier circuit, a 200 latch circuit;

A 110 current source, a 120 signal amplifying unit, a 130 first control unit, a 140 signal output unit, a 150 second control unit, a 160 first interlocking unit, and a 170 second interlocking unit;

121 differential amplifier, 122 inverter, 123 transmission gate controller;

The first clock signal CLK, the second clock signal CLKB, the first input signal BL, the second input signal BLB, the first output node OUTA, the second output node OUTB, the first amplified signal INA, the second amplified signal INB, the first output signal AS, the second output signal ASB, the first reference voltage signal VDD1, the second reference voltage signal VDD2.

Detailed Description

The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments.

In the embodiment of the application, the transistor refers to an element at least comprising a gate electrode, a drain electrode and a source electrode, and the transistor can be a thin film transistor or a field effect transistor or other switching devices with the same characteristics, and the source electrode and the drain electrode of the transistor adopted in the embodiment of the application can be symmetrical in structure, so that the source electrode and the drain electrode of the transistor can be indiscriminate in structure.

Meanwhile, the transistor in the embodiment of the application at least comprises two types of P type and N type, and a person skilled in the art can replace the transistor according to actual needs without departing from the spirit and the protection scope of the application. The present application will be described below with reference to the accompanying drawings.

In a first aspect, fig. 1 is a schematic block diagram of a sense amplifier circuit according to an embodiment of the present application, and as shown in fig. 1, the sense amplifier circuit 100 includes: a current source 110, a signal amplifying unit 120, a first control unit 130, and a signal output unit 140.

The current source 110 is used for generating a first driving current; the signal amplifying unit 120 is electrically connected to the current source 110, and the signal amplifying unit 120 is configured to generate a first amplified signal INA and a second amplified signal INB according to an input signal potential difference and a first driving current, where the input signal potential difference is a potential difference between the first input signal BL and the second input signal BLB received by the signal amplifying unit 120; the first control unit 130 is electrically connected to the first output node OUTA and the second output node OUTB, respectively, and the first control unit 130 is configured to transmit the first output signal AS to the first output node OUTA according to the first clock signal CLK and transmit the second output signal ASB to the second output node OUTB according to the first clock signal CLK; the signal output unit 140 is electrically connected to the signal amplifying unit 120 and the first control unit 130, and the signal output unit 140 is configured to generate a first output signal AS according to the first amplified signal INA and transmit the first output signal AS to the first control unit 130, and the signal output unit 140 is configured to generate a second output signal ASB according to the second amplified signal INB and transmit the second output signal ASB to the first control unit 130.

In the current memory architecture, for example, an SRAM-based memory computing architecture, data is generally written or read by using bit line pairs, and since signals in the bit lines are weak, differential data formed by the bit line pairs needs to be amplified.

The sense amplifier circuit 100 according to the embodiment of the present application may amplify differential data of a bit line pair, the input signal potential difference may be understood as the differential data, and the first input signal BL and the second input signal BLB may be provided by the bit line pair in the memory architecture, which typically have a certain potential difference to distinguish between written or read data.

It should be noted that, since the current of the bit line pair is weak and the potential difference of the input signal is small, the current source 110 electrically connected to the signal amplifying unit 120 is provided in the embodiment of the present application, the signal amplifying unit 120 generates the first amplified signal INA and the second amplified signal INB according to the first driving current provided by the current source 110 and the potential difference of the input signal, and since the additional exciting current is provided by the current source 110, the potential difference of the first amplified signal INA and the second amplified signal INB is greater than the potential difference of the second input signal BLB of the first input signal BL, so as to amplify the differential data.

AS an example, the embodiment of the present application further provides the first control unit 130 and the signal output unit 140, AS shown in fig. 1, where the signal output unit 140 receives the first amplified signal INA and the second amplified signal INB, and the signal output unit 140 generates the first output signal AS and the second output signal ASB according to the potential of the first amplified signal INA and the potential of the second amplified signal INB, and the first output signal AS and the second output signal ASB may be larger current signals.

The first control unit 130 is electrically connected to the first output node OUTA and the second output node OUTB, respectively, and receives the first output signal AS and the second output signal ASB. When the memory architecture of the sense amplifier circuit 100 needs to read or write data, the first control unit 130 may be in a conductive state under the control of the first clock signal CLK, and may respectively transmit the first output signal AS to the first output node OUTA and transmit the second output signal ASB to the second output node OUTB, and similarly, when the memory architecture of the sense amplifier circuit 100 does not need to read or write data, the first control unit 130 may be in a non-conductive state, and the output signal cannot be transmitted to the output node.

In some examples, the first output node OUTA and the second output node OUTB may be electrically connected to a data line in a memory architecture, in which the first output signal AS and the second output signal ASB can thus be written.

It should be noted that, in a typical sense amplifier, the signal input and the signal output of the sense amplifier circuit form a positive feedback stage, and the positive feedback needs to be adjusted by feedback after the whole circuit operates for a period of time, so the sensing speed is slow, and there is a part of additional power consumption due to the preheating process. Moreover, in some cases, some conventional sense amplifiers have input nodes directly connected to output nodes, and the amplified voltage difference is extremely susceptible to interference, which may lead to erroneous data output if the control circuit operates with some fluctuation in time. In the sense amplifier circuit 100 according to the embodiment of the present application, the nodes of the input signal and the output signal are isolated, so that the mutual interference between the input signal and the output signal can be reduced, and the accuracy of the output data is improved, and the driving current is provided to the signal amplifying unit 120 by setting the current source 110, and the signal amplifying unit 120 generates the first amplified signal INA and the second amplified signal INB according to the potential difference formed by the first input signal BL and the second input signal BLB, and the potential difference of the first amplified signal INA and the second amplified signal INB is greater than the potential difference of the first input signal BL and the second input signal BLB, so that the positive feedback is not provided to the signal input through the signal output, and the whole circuit can directly operate without preheating, so that the sensing speed can be improved.

Fig. 2 is a schematic block diagram of another sense amplifier circuit according to an embodiment of the present application, and as shown in fig. 2, the sense amplifier circuit 100 further includes: and a second control unit 150. The second control unit 150 is electrically connected to the first output node OUTA and the second output node OUTB, respectively, and the second control unit 150 is configured to transmit the first reference voltage signal VDD1 to the first output node OUTA and the second output node OUTB according to the first clock signal CLK, respectively.

For example, the first reference voltage signal VDD1 may be a constant voltage source, and the second control unit 150 may transmit a constant voltage to the first output node OUTA and the second output node OUTB under the control of the first clock signal CLK, so that the potentials of the first output node OUTA and the second output node OUTB may be set.

It should be noted that, the memory often needs to perform repeated reading and writing operations, the potential of the data node will often change, in this process, it is unavoidable that residual charges exist at the nodes where some potentials need to change frequently, and these residual charges will interfere with the accuracy of data output.

Illustratively, both the first control unit 130 and the second control unit 150 are controlled by the first clock signal CLK, the first control unit 130 and the second control unit 150 are turned on and off asynchronously, i.e., when the second control unit 150 is turned on, the first reference voltage signal VDD1 is written to the first output node OUTA and the second output node OUTB, and the first control unit 130 is turned off, stopping writing the first output signal AS and the second output signal ASB to the first output node OUTA and the second output node OUTB, respectively; correspondingly, when the first control unit 130 is turned off, the writing of the first reference voltage signal VDD1 to the first output node OUTA and the second output node OUTB is stopped, the first control unit 130 is turned on, and the first output signal AS and the second output signal ASB are respectively written to the first output node OUTA and the second output node OUTB. The embodiment of the application can reduce the processing logic of signals by controlling the first control unit 130 and the second control unit 150 based on the same clock signal, thereby improving the working efficiency of the sense amplifier circuit 100, further improving the sensing speed of the sense amplifier circuit 100, and further reducing the power consumption in a storage architecture.

According to some embodiments, as shown in fig. 2, the sense amplifier circuit 100 further includes: the first interlocking unit 160.

The first interlock unit 160 is electrically connected to the first output node OUTA and the second output node OUTB, respectively, and the first interlock unit 160 is configured to transmit the first reference voltage signal VDD1 to the second output node OUTB according to a potential of the first output node OUTA and transmit the first reference voltage signal VDD1 to the first output node OUTA according to a potential of the second output node OUTB.

The first interlock unit 160 is electrically connected to the first output node OUTA and the second output node OUTB, and an interlock structure is formed between the first output node OUTA and the second output node OUTB through the first interlock unit 160, for example, when the first output node OUTA is at a high potential, the first interlock unit 160 does not transmit the first reference voltage signal VDD1 to the second output node OUTB, and when the second output node OUTB is at a low potential, the first interlock unit transmits the first reference voltage signal VDD1 to the first output node OUTA, wherein the first reference voltage signal VDD1 may be a constant voltage source. And when the first output node OUTA is at a low potential, the same is omitted.

The potential difference between the first output node OUTA and the second output node OUTB is used to reflect the potential difference between the first input signal BL and the second input signal BLB, and the first interlock unit 160 is provided to clamp the potential of the first output node OUTA and the potential of the second output node OUTB, so as to prevent potential abrupt change, thereby improving accuracy of data output.

In the embodiment of fig. 2, the sense amplifier circuit 100 further includes: and a second interlocking unit 170.

The second interlock unit 170 is electrically connected to the first control unit 130, the first output node OUTA, and the second output node OUTB, respectively, and the second interlock unit 170 is configured to control the output unit to transmit the second output signal ASB to the first control unit 130 according to the potential of the first output node OUTA, and to control the output unit to transmit the first output signal AS to the first control unit 130 according to the potential of the second output node OUTB.

As illustrated in fig. 2, the second interlock unit 170 is disposed between the first control unit 130 and the output unit, and the second interlock unit 170 may control whether the output signal can be written to the first control unit 130 based on the potential of the output node, thereby preventing the first control unit 130 from being turned on erroneously due to the clock signal error of the first control unit 130, and the output signal from being written erroneously.

In some examples, fig. 3 is a schematic block diagram of a sense amplifier circuit according to an embodiment of the present application, and may be applied to the embodiment of fig. 2, as shown in fig. 3, the first control unit 130 may include an N-type sixth transistor N1 and an N-type seventh transistor N2, the second interlock unit 170 may include an N-type eighth transistor N3 and an N-type ninth transistor N4, the first interlock unit 160 may include a P-type tenth transistor P2 and a P-type eleventh transistor P3, and the second control unit 150 may include a P-type twelfth transistor P1 and a P-type transistor P4.

The gates of the sixth transistor N1 and the seventh transistor N2 are each configured to receive the first clock signal CLK, the first electrodes of the sixth transistor N1 and the seventh transistor N2 are respectively connected to the first output node OUTA and the second output node OUTB, the second electrodes of the sixth transistor N1 and the seventh transistor N2 are respectively connected to the first electrode of the eighth transistor N3 and the first electrode of the ninth transistor N4, the gates of the eighth transistor N3 and the ninth transistor N4 are respectively connected to the second output node OUTB and the first output node OUTA, the second electrodes of the eighth transistor N3 and the ninth transistor N4 are respectively configured to receive the first output signal AS and the second output signal ASB, the first electrodes of the tenth transistor P2 and the eleventh transistor P3 are respectively connected to the first output node OUTA and the first output node OUTA, the gates of the tenth transistor P2 and the eleventh transistor P3 are respectively connected to the first reference voltage signal VDD1, the second electrodes of the tenth transistor P2 and the twelfth transistor P4 are respectively connected to the first output node OUTA and the first output node 4, and the first electrodes of the tenth transistor P1 and the twelfth transistor P4 are respectively connected to the first output node OUTA.

For example, when the first clock signal CLK is at a low potential, the twelfth transistor P1 and the transistor P4 are turned on, the first reference voltage signal VDD1 is written into the first output node OUTA, the tenth transistor P2 and the eleventh transistor P3 are turned off, which may be in the precharge stage of the sense amplifier circuit 100 provided in the embodiment of the present application, the written first reference voltage signal VDD1 may set the first output node OUTA and the second output node OUTB, the eighth transistor N3 and the ninth transistor N4 are turned on, and accordingly, the sixth transistor N1 and the seventh transistor N2 are turned off, and the first output signal AS and the second output signal ASB cannot be written into the first output node OUTA and the second output node OUTB through the sixth transistor N1 and the seventh transistor N2.

When the first clock signal CLK becomes a high potential, the twelfth transistor P1 and the transistor P4 are turned off, the sixth transistor N1 and the seventh transistor N2 are in an on state, the first output signal AS and the second output signal ASB are written into the first output node OUTA through the eighth transistor N3 and the sixth transistor N1, and the ninth transistor N4 and the seventh transistor N2 are written into the second output node OUTB, respectively, completing the differential data output. For example, when the first output signal AS is at a high level and the second output signal ASB is at a low level, the eleventh transistor P3 is turned off by the potential of the first output node OUTA, the tenth transistor P2 is turned on by the potential of the second output node OUTB, the first reference voltage signal VDD1 can be written into the first output node OUTA but cannot be written into the second output node OUTB, the ninth transistor N4 is turned on by the first output node OUTA, the eighth transistor N3 is turned off by the second output node OUTB, that is, the second output signal ASB can be written into the second output node OUTB, and the potential of the first output node OUTA is provided by the first reference voltage signal VDD1, and it is easy to understand that since the first reference voltage signal VDD1 can be a constant voltage source, the potential difference between the first output node OUTA and the second output node OUTA becomes more obvious than the first output signal AS is, so that the amplifier 100 according to the embodiment of the present application provides more accurate data output. When the first output signal AS is at a low level and the second output signal ASB is at a high level, the same is omitted.

According to some embodiments, the signal output unit 140 includes: a first transistor and a second transistor. The first transistor is configured to generate a first output signal AS according to the first amplified signal INA and transmit the first output signal AS to the first control unit 130 through a first electrode of the first transistor; the second transistor is configured to generate a second output signal ASB according to the second amplified signal INB and transmit the second output signal ASB to the first control unit 130 through a second electrode of the second transistor; the gates of the first transistor and the second transistor are electrically connected to the signal amplifying unit 120, the second electrodes of the first transistor and the second transistor are grounded, and the characteristics of the first transistor and the second transistor are the same, and the characteristics include a switching characteristic.

For example, AS shown in fig. 3, the first transistor may include an N-type transistor N5, the second transistor may include an N-type transistor N6, a gate of the transistor N5 is used for receiving the first amplified signal INA, a gate of the transistor N6 is used for receiving the second amplified signal INB, second electrodes of the transistor N6 and the transistor N5 are grounded, and the first electrodes are used for transmitting the first output signal AS or the second output signal ASB to the first control unit 130, and the switching characteristics of the first and second output signals ASB are the same, so AS to ensure that the amplification coefficients of the first and second amplified signals INA and INB are the same, and thus ensure the amplification accuracy of the potential difference of the first and second input signals BL and BLB.

In some examples, AS shown in fig. 2, the output unit may further transmit the first output signal AS and the second output signal ASB to the first control unit 130 through the above-mentioned second interlock unit 170, and in combination with the embodiment of fig. 3, in the case where the second interlock unit 170 includes the eighth transistor N3 and the ninth transistor N4, the first control unit 130 includes the sixth transistor N1 and the seventh transistor N2, and the first electrodes of the transistors N5 and N6 in the output unit are electrically connected to the second electrodes of the eighth transistor N3 and the ninth transistor N4, respectively.

It should be noted that, if the transistors in the output unit are directly connected to the transistors in the first control unit 130, since the potentials of the first output node OUTA and the second output node OUTB often change, the second electrode stability of the sixth transistor N1 and the seventh transistor N2 in the first control unit 130 may also decrease along with the decrease, and the potentials of the first electrodes of the transistor N5 and the transistor N6 in the output unit electrically connected to the second electrodes of the sixth transistor N1 and the seventh transistor N2 also fluctuate, so that the threshold voltage drift of the transistor N5 and the transistor N6 is easily caused, and by disposing the second latch unit between the first control unit 130 and the output unit, the isolation effect may be performed, so that the possibility of the threshold voltage drift of the transistor N5 and the transistor N6 may be reduced, thereby improving the accuracy of the output data of the sense amplifier circuit 100 according to the embodiment of the present application.

According to some embodiments, in the embodiment of fig. 1 or fig. 2, the signal amplifying unit 120 includes: a differential amplifier 121 and an inverter 122.

The differential amplifier 121, the first output end of the differential amplifier 121 is electrically connected with the gate of the first transistor, the current receiving end of the differential amplifier 121 is electrically connected with the current source 110, the first output end of the differential amplifier 121 is used for transmitting the first amplified signal INA, the first input end of the differential amplifier 121 is used for receiving the first input signal BL, and the second input end of the differential amplifier 121 is used for receiving the second input signal BLB;

And an inverter 122, an input terminal of the inverter 122 is electrically connected to the second output terminal of the differential amplifier 121, an output terminal of the inverter 122 is electrically connected to the gate of the second transistor, and an output terminal of the inverter 122 is used for transmitting the second amplified signal INB.

As an example, as shown in fig. 2 and 3, the differential amplifier 121 may generate a differential signal based on a potential difference between the first input signal BL and the second input signal BLB, where one of the differential signals is connected to the gate of the first transistor of the signal output unit 140, for example, the gate of the transistor N5 in fig. 3, and the other differential signal is connected to the input terminal of the inverter 122, and the output terminal of the inverter 122 is connected to the gate of the second transistor of the signal output unit 140, for example, the gate of the transistor N6 in fig. 3.

In the embodiment of the present application, the inverter 122 is configured to invert the differential signal potential, so that the potential difference of the differential signal can be increased, which corresponds to the increase of the potential difference between the first input signal BL and the second input signal BLB, and thus the amplification factor of the sense amplifier circuit 100 provided in the embodiment of the present application can be improved.

Illustratively, as shown in fig. 3, the inverter 122 includes a P-type fourteenth transistor P9 and an N-type fifteenth transistor N10, the fourteenth transistor P9 functioning as a pull-up transistor having a first electrode receiving the first reference voltage signal VDD1, and the fifteenth transistor N10 functioning as a pull-down transistor having a second electrode grounded. In the case where the sense amplifier circuit 100 includes the second control unit 150, the first interlock unit 160, and the second interlock unit 170, the first amplified signal INA output from the first output terminal of the differential amplifier 121 is at a high potential, and the second amplified signal INB output from the output terminal of the inverter 122 is at a low potential. When the first clock signal CLK is at a high potential, the sixth transistor N1 and the seventh transistor N2 in the first control unit 130 are in an on state, the transistor N5 is in an on state, the transistor N6 is in an off state, the transistor N5 writes a low potential into the first output node OUTA, the ninth transistor N4 is turned off under the action of the first output node OUTA, the eleventh transistor P3 is turned on under the action of the low potential of the first output node OUTA, and the first reference voltage signal VDD1 is written into the second output node OUTB, i.e., the first output node OUTA and the second output node OUTB are in a state of "0" and "1", respectively.

The same applies to the case where the first amplified signal INA output from the first output terminal of the differential amplifier 121 is at a low potential and the second amplified signal INB output from the output terminal of the inverter 122 is at a high potential, and the description thereof will be omitted.

According to some embodiments, in the embodiment of fig. 1 or fig. 2, the signal amplifying unit 120 further includes: and a transmission gate controller 123. An input end of the transmission gate controller 123 is electrically connected with a second output end of the differential amplifier 121, an output end of the transmission gate controller 123 is electrically connected with an input end of the inverter 122, a first control end of the transmission gate controller 123 is used for receiving a first clock signal CLK, a second control end of the transmission gate controller 123 is used for receiving a second clock signal CLKB, and the transmission gate controller 123 is used for being turned on or turned off under the control of at least one of the first clock signal CLK and the second clock signal CLKB; wherein the first clock signal CLK and the second clock signal CLKB have opposite potentials.

As illustrated in fig. 2, a transmission gate controller 123 is disposed between the differential amplifier 121 and the inverter 122, and the transmission gate controller 123 is capable of being turned on under control of at least one of the first clock signal CLK and the second clock signal CLKB to electrically connect the differential amplifier 121 and the inverter 122 or turned off to disconnect the differential amplifier 121 from the inverter 122.

Note that, the transmission gate controller 123 is controlled by the first clock signal CLK in the same manner as the first control unit 130, and when the first control unit 130 is turned on, the transmission gate controller 123 is also turned on, and an electrical connection is formed between the differential amplifier 121 and the inverter 122, and the signal amplifying unit 120 can generate the first amplified signal INA and the second amplified signal INB. When the potential of the first clock signal CLK is inverted, the transfer gate controller 123 is turned off, the first control unit 130 is turned off, the differential amplifier 121 is disconnected from the inverter 122, and the signal amplifying unit 120 does not generate the first amplified signal INA and the second amplified signal INB. In the embodiment of the application, the transmission gate controller 123 is provided to control the electrical connection between the differential amplifier 121 and the inverter 122, so that the electrical connection between the differential amplifier 121 and the inverter 122 is disconnected when the sensitive amplifier circuit 100 is not in operation, thereby reducing leakage current and saving power consumption.

In some examples, as shown in fig. 3, the transmission gate controller 123 includes a P-type sixteenth transistor P8 and an N-type seventeenth transistor N9, wherein the sixteenth transistor P8 and the seventeenth transistor N9 are connected in parallel and then connected in series between the differential amplifier 121 and the inverter 122, the gate of the sixteenth transistor P8 receives the second clock signal CLKB, and the gate of the seventeenth transistor N9 receives the first clock signal CLK. Since the first clock signal CLK and the second clock signal CLKB have opposite potentials, when the first clock signal CLK is at a high potential and the second clock signal CLKB is at a low potential, both the sixteenth transistor P8 and the seventeenth transistor N9 are turned on, and when the first clock signal CLK is at a low potential and the second clock signal CLKB is at a high potential, both the sixteenth transistor P8 and the seventeenth transistor N9 are turned off.

It should be noted that, since the P-type transistor has a threshold loss when transmitting a low-potential signal between the first electrode and the second electrode, there is no threshold loss when transmitting a high-potential signal, and the N-type transistor is opposite to the P-type transistor. In the embodiment of the application, the P-type sixteenth transistor P8 and the N-type seventeenth transistor N9 are connected in parallel and then connected in series between the differential amplifier 121 and the inverter 122, so that the transmission gate controller 123 can not have threshold loss no matter the transmission gate controller transmits a high-level signal or a low-level signal, and the accuracy of output data in the embodiment of the application can be improved.

According to some embodiments, the differential amplifier 121 includes: a third transistor, a fourth transistor, and a current mirror.

A third transistor having a gate for receiving the first input signal BL; a fourth transistor having a gate for receiving the second input signal BLB, the first electrodes of the third and fourth transistors being electrically connected to the current source 110; and a current mirror, an input end of the current mirror is electrically connected with the second electrode of the third transistor, and a mirror end of the current mirror is electrically connected with the second electrode of the fourth transistor; the mirror end of the current mirror is electrically connected with the input end of the inverter 122, and the input end of the current mirror is electrically connected with the gate of the first transistor.

For example, as shown in fig. 3, the third transistor may include a P-type transistor P6, the fourth transistor may include a P-type transistor P7, gates of the transistor P6 and the transistor P7 respectively receive the first input signal BL and the second input signal BLB, and first electrodes are electrically connected to the current source 110. The current mirror may include an N-type transistor N7 and an N-type transistor N8, where a first electrode of the transistor N7 is electrically connected to a gate of the transistor N7 and a gate of the transistor N8, both the transistor N7 and a second electrode of the transistor N8 are grounded, a first electrode of the transistor N7 is electrically connected to a second electrode of the transistor P6, and a first electrode of the transistor N8 is electrically connected to a second electrode of the transistor P7.

For example, when the potential of the second input signal BLB is lower than the potential of the first input signal BL, the current flowing through the transistor is greater than the current flowing through the transistor P6, the current flowing through the transistor N8 replicates the current flowing through the branches of the transistor P6 and the transistor N7, and the potential of the mirror end of the current mirror is lower than the potential of the input end of the current mirror, the potential drops, the inverter 122 inverts to output a high level, the mirror end of the current mirror outputs a low level, the transistor N5 in the output unit is turned off, the transistor N6 is turned on, the second output node OUTB writes a low potential, the tenth transistor P2 is turned on, the first output node OUTA writes a high potential, that is, the second output node OUTB potential is "0", the first output node OUTA potential is "1", and the amplification of the potential difference between the first input signal BL and the second input signal BL is completed.

When the potential of the second input signal BLB is higher than that of the first input signal BL, the same is omitted.

In the embodiment of fig. 1 or 2, the current source 110 includes: and a fifth transistor. The gate of the fifth transistor is electrically connected to the input terminal of the current mirror, the first electrode of the fifth transistor is used for receiving the second reference voltage signal VDD2, and the second electrode of the fifth transistor is electrically connected to the first electrodes of the third transistor and the fourth transistor, respectively.

For example, as shown in fig. 3, the fifth transistor may include a P-type transistor P5, where a first electrode of the transistor P5 is configured to receive the second reference voltage signal VDD2, the second reference voltage signal VDD2 may be a constant voltage source, a second electrode of the transistor P5 is electrically connected to the first electrodes of the transistors P6 and P7, and a gate of the transistor P5 is electrically connected to the input terminal of the current mirror.

According to the embodiment of the application, the grid electrode of the fifth transistor is electrically connected with the input end of the current mirror, so that the fifth transistor can be in a self-bias state, and then the data line can be saved, and the area of a storage architecture can be reduced.

In some examples, the second reference voltage signal VDD2 may be the same as the first reference voltage signal VDD1, so that data lines may be further saved and the area of the memory architecture may be reduced.

In a second aspect, fig. 4 is a schematic block diagram of a resistive random access memory device according to an embodiment of the present application, and as shown in fig. 4, a resistive random access memory device 10 includes: a latch circuit 200; and a sense amplifier circuit 100 as in any one of the first aspects; the first output node OUTA of the sense amplifier circuit 100 is electrically connected to the first input node of the latch circuit 200, and the second output node OUTB of the sense amplifier circuit 100 is electrically connected to the second input node of the latch circuit 200.

It should be noted that, the RRAM (RESISTIVE RANDOM ACCESS MEMORY ) is a nonvolatile memory that stores data by controlling the resistance state of a resistive material, and compared with a conventional flash memory, the resistive memory has a faster writing speed, a higher storage density, and a longer lifetime, and thus can be widely used in an in-memory integrated memory architecture.

The sense amplifier circuit 100 according to the embodiment of the present application has a faster sensing speed than other conventional sense amplifiers, and the first output node OUTA and the second output node OUTB of the sense amplifier circuit 100 are electrically connected to the first input node and the second input node in the latch circuit 200, respectively, so that data can be quickly read from or written into the latch circuit 200, thereby improving the processing speed of the resistive random access memory device 10.

The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some of the technical features thereof can be replaced equivalently; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims (10)

1. A sense amplifier circuit, comprising:

a current source for generating a first drive current;

The signal amplifying unit is electrically connected with the current source and is used for generating a first amplified signal and a second amplified signal according to an input signal potential difference and the first driving current, wherein the input signal potential difference is the potential difference of the first input signal and the second input signal received by the signal amplifying unit;

The first control unit is electrically connected with a first output node and a second output node respectively, and is used for transmitting the first output signal to the first output node according to a first clock signal and transmitting the second output signal to the second output node according to the first clock signal;

The signal output unit is respectively and electrically connected with the signal amplifying unit and the first control unit, and is used for generating the first output signal according to the first amplified signal and transmitting the first output signal to the first control unit, and is used for generating the second output signal according to the second amplified signal and transmitting the second output signal to the first control unit.

2. The sense amplifier circuit of claim 1, further comprising:

And the second control unit is respectively and electrically connected with the first output node and the second output node, and is used for respectively transmitting a first reference voltage signal to the first output node and the second output node according to the first clock signal.

3. The sense amplifier circuit of claim 2, further comprising:

The first interlocking unit is electrically connected with the first output node and the second output node respectively, and is used for transmitting the first reference voltage signal to the second output node according to the potential of the first output node and transmitting the first reference voltage signal to the first output node according to the potential of the second output node.

4. A sense amplifier circuit according to claim 3, further comprising:

The second interlocking unit is electrically connected with the first control unit, the first output node and the second output node respectively, and is used for controlling the output unit to transmit the second output signal to the first control unit according to the potential of the first output node and controlling the output unit to transmit the first output signal to the first control unit according to the potential of the second output node.

5. The sense amplifier circuit of any one of claims 1-4, wherein the signal output unit comprises:

a first transistor for generating the first output signal according to the first amplified signal and transmitting to the first control unit through a first electrode of the first transistor;

A second transistor for generating the second output signal according to the second amplified signal and transmitting to the first control unit through a second electrode of the second transistor;

The first transistor and the second transistor are electrically connected with the signal amplifying unit through gates, second electrodes of the first transistor and the second transistor are grounded, characteristics of the first transistor and the second transistor are the same, and the characteristics comprise switching characteristics.

6. The sense amplifier circuit of claim 5, wherein the signal amplifying unit comprises:

The first output end of the differential amplifier is electrically connected with the grid electrode of the first transistor, the current receiving end of the differential amplifier is electrically connected with the current source, the first output end of the differential amplifier is used for transmitting the first amplified signal, the first input end of the differential amplifier is used for receiving the first input signal, and the second input end of the differential amplifier is used for receiving the second input signal;

And the input end of the inverter is electrically connected with the second output end of the differential amplifier, the output end of the inverter is electrically connected with the grid electrode of the second transistor, and the output end of the inverter is used for transmitting the second amplified signal.

7. The sense amplifier circuit of claim 6 wherein the signal amplification unit further comprises:

The input end of the transmission gate controller is electrically connected with the second output end of the differential amplifier, the output end of the transmission gate controller is electrically connected with the input end of the inverter, the first control end of the transmission gate controller is used for receiving the first clock signal, the second control end of the transmission gate controller is used for receiving the second clock signal, and the transmission gate controller is used for being controlled to be turned on or turned off under the control of at least one of the first clock signal and the second clock signal;

wherein the first clock signal and the second clock signal are opposite in potential.

8. The sense amplifier circuit of claim 6 wherein the differential amplifier comprises:

A third transistor having a gate for receiving the first input signal;

A fourth transistor, a gate of which is used for receiving the second input signal, and first electrodes of the third transistor and the fourth transistor are electrically connected with the current source;

a current mirror, an input end of which is electrically connected with the second electrode of the third transistor, and a mirror end of which is electrically connected with the second electrode of the fourth transistor;

The mirror end of the current mirror is electrically connected with the input end of the inverter, and the input end of the current mirror is electrically connected with the grid electrode of the first transistor.

9. The sense amplifier circuit of claim 8 wherein the current source comprises:

And a fifth transistor, wherein a gate of the fifth transistor is electrically connected with the input end of the current mirror, a first electrode of the fifth transistor is used for receiving a second reference voltage signal, and a second electrode of the fifth transistor is electrically connected with the first electrodes of the third transistor and the fourth transistor respectively.

10. A resistive random access memory device, comprising:

A latch circuit;

The sense amplifier circuit of any of claims 1-9;

the first output node of the sensitive amplifier circuit is electrically connected with the first input node of the latch circuit, and the second output node of the sensitive amplifier circuit is electrically connected with the second input node of the latch circuit.