JP2690212B2 - Current detection type data bus amplifier for semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current detection type data bus amplifier for a semiconductor memory device, and more particularly to a current detection type data bus amplifier for a semiconductor memory device in a memory cell information read circuit.

[0002]

2. Description of the Related Art A conventional current detection type data bus amplifier for a semiconductor memory device has a bit line pair BLi for transmitting complementary information signals of memory cells on one word line as shown in FIG.
T, BLiB (i is a natural number from 0 to n, n is the number of memory cells on one word line) is input, and the bit line pair information selected by the selected column address switch Yi is output to the data buses DBT and DBB. Column selection circuit 20i
A negative feedback circuit 21 for keeping the potentials of the data buses DBT and DBB at a fixed potential; a load circuit 22 for converting current amplitude information of the data buses DBT and DBB into voltage amplitude information signals D1T and D1B; and a voltage amplitude information signal D1T. , D1B to output an output signal DOUT.

Next, the operation of the conventional example will be described. First, the memory cell information on one word line which is voltage-amplified by the sense amplifier is input from each bit line pair BLiT, BLiB, and the bit line pair data of one column address is selected by the column address switch Yi which becomes high level at the time of selection. And outputs to the data buses DBT and DBB. At this time,
The data buses DBT and DBB are bit line pairs BLiT and BL.
N-channel transistors 200i and 201i or 202 in which a current proportional to the voltage level of iB is connected in series
flow to GND through i and 203i, and bit line pair B
Data bus DB for voltage amplitude information on LiT and BLiB
It is converted into information on the amplitude of the current flowing through T and DBB.

Next, when the potentials of the data buses DBT and DBB drop slightly, the N-channel type transistors 211 and 212 are turned on by the negative feedback inverters 210 and 213 to supply charges to the data buses DBT and DBB and the data bus D.
The potentials of BT and DBB are used as negative feedback inverters 210 and 213.
It operates so as to keep it equal to the input threshold level VTH. Therefore, the potential of the data bus is always the fixed potential V
Keep th.

Further, at this time, the P-channel type transistors 220 and 221 function as a load circuit, and the data bus DB
The potentials of the voltage amplitude information signals D1T and D1B are lowered by an amount proportional to the currents flowing in T and DBB, and the potential difference is amplified by the differential amplitude unit 230 to obtain the output data DOUT.

[0006]

In this conventional current detection type data bus amplifier for semiconductor memory devices, the bit line B
The potential of LiT or BLiB is amplified by a sense amplifier (not shown), and the N-channel transistor 201
i or 203i becomes lower than the gate threshold voltage VT, no current flows in the data bus DBT or DBB, the N-channel type transistor 211 or 212 is cut off, and the DBT in the data bus is turned off.
Alternatively, DBB goes into a high impedance state. As a result, when noise occurs, the data buses DBT, DBB
The upper potential VTH tends to fluctuate, and the data bus potential that has fluctuated to the high level side in particular cannot return to the original potential VTH because the discharge path of the electric charge is closed, and the next inverted data is output. However, there are problems such as malfunction and delay in amplification speed.

[0007]

DISCLOSURE OF THE INVENTION The gist of the present invention is to provide a first circuit for generating a first output signal having a current amplitude corresponding to a logical value of a data bit on a data bus, and a potential of the first output signal. A current detection type data bus amplifier for a semiconductor memory device, comprising: a negative feedback circuit for fixing the voltage and a second circuit for generating a second output signal having a voltage amplitude corresponding to the current amplitude of the first output signal. That is, a current circuit for supplying a constant current to a fixed voltage source is provided.

[0008]

Since the current circuit constantly supplies current from the data bus to the fixed voltage source, the negative feedback circuit does not cut off. Therefore, even if noise is transmitted to the data bus, it can be promptly recovered.

[0009]

Next, an embodiment of the present invention will be described with reference to the drawings. 1 is a circuit diagram of a current detection type data bus amplifier for a semiconductor memory device showing a first embodiment of the present invention.

The complementary information signal of the memory cell connected to the selected word line is a bit line pair BLiT, BLiB (i
Is a natural number from 0 to n, where n is the number of memory cells on one word line), and the N-channel transistors 100i and 102i of the column selection circuit 10i selected by the selected column address switch signal Yi are bit lines BLi.
N-channel transistor 10 controlled by T and BLiB
The bit line pair information is transferred to the data buses DBT and DBB in cooperation with 1i and 103i. The negative feedback circuit 11 keeps the potentials on the data buses DBT and DBB fixed, and the load circuit 12 converts the current amplitude information of the data buses DBT and DBB into voltage amplitude information signals D1T and D1B. Differential amplifier 1
3 receives the voltage amplitude information signals D1T and D1B and outputs an output signal DOUT. Further, the current circuit 14 constantly causes a current to flow from the data buses DBT and DBB.

Next, the operation of the first embodiment will be described.
First, 1 which is voltage-amplified by a sense amplifier (not shown)
The memory cell information on the word line is represented by each bit line pair BLiT,
A column address switch signal Yi is supplied to the column selection circuit 10i via BLiB and is at a high level when selected.
Selects the bit line pair data of one column address and outputs it to the data buses DBT and DBB.

At this time, the data buses DBT and DBB are connected to the N-channel type transistors 100i and 1 in which a current proportional to the voltage level of the bit line pair BLiT and BLiB is connected in series.
The voltage amplitude information on the bit line pair BLiT, LiB is converted into current amplitude information flowing on the data buses DBT, DBB through 01i or 102i and 203i. On the other hand, the current circuit 14 uses the bit line pair BLiT, B
Data bus DB even if the voltage level changes on LiB
It is flowing from T, DBB to GND.

In this embodiment, the column selection circuit 10i is the first
The load circuit 12 constitutes a second circuit.

When the potentials on the data buses DBT and DBB drop slightly, the N-channel type transistors 111 and 112 are turned on.
Due to the action of the negative feedback inverters 110 and 113, the potential difference VGS between the gate and the source increases, so that more charges are supplied to the data bus, and the data buses DBT and DBB.
Of the negative feedback inverters INV110 and 113 is kept equal to the input threshold level VTH. Therefore, the potential of the data bus always maintains the fixed potential VTH. However, since the current circuits 140 and 141 are supplying a steady current to GND, the N-channel transistors 211 and 212 are not cut off.

Further, at this time, the P-channel type transistors 120 and 121 function as a load circuit, and the data bus D
The potentials of the voltage amplitude information signals D1T and D1B are lowered by an amount proportional to the current flowing through BT and DBB, and the potential difference is amplified by the differential amplifier 130 to obtain the output data DOUT.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention. The difference between the second embodiment and the first embodiment is the code in which the current circuit 14 composed of N-channel type transistors is composed of resistors 340 and 341 in the first embodiment.
These resistors 340 and 341 supply the data bus steady-state current, and the other operations and configurations are the same as those in the first embodiment, and the description thereof will be omitted.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention. The third embodiment is different from the first embodiment in that the current circuit 44 is composed of depletion transistors 440 and 441 so that a steady current flows through the data bus. Other configurations and operations are the same as those in the first embodiment, and the description thereof will be omitted.

[0018]

As described above, according to the present invention, the current supply circuit allows the current to constantly flow in the data bus, so that the N-channel transistor for charge supply of the negative feedback circuit for maintaining the potential of the data bus. Does not cut off, so the data bus can be kept in a low impedance state. Therefore,
The fluctuation of the data bus potential VTH due to the influence of noise can be reduced, and the potential of the data bus changed by noise can be restored to the potential VTH by a path through which a steady current flows. Next, there is an effect that a malfunction does not occur when an inverted data is output, and a delay in the amplification speed does not occur.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional example.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a third embodiment of the present invention.

[Explanation of symbols]

10i, 20i Column selection circuit (i is a natural number from 0 to n, n is the number of memory cells on one word line) 11,21 Negative feedback circuit 12,22 Load circuit 13,23 Differential amplifier 14,34,44 Current Circuits 120, 121, 220, 221 P-channel type transistors 111, 112, 100i, 101i, 102i, 10
3i, 140, 141, 211, 212, 200i, 201i, 202i, 2
03i N-channel type transistor 110, 113, 210, 213 Inverter 340, 341 Resistor 440, 441 Depletion transistor 130, 230 Differential amplifier

Claims (3)

(57) [Claims] 1. A first circuit for generating a first output signal having a current amplitude corresponding to a logical value of a data bit on a data bus, a negative feedback circuit for fixing the potential of the first output signal, and a first circuit. A current detection type data bus amplifier for a semiconductor memory device, comprising: a second circuit for generating a second output signal having a voltage amplitude corresponding to the current amplitude of an output signal, wherein a constant current is supplied to a fixed voltage source in the data bus. A current detection type data bus amplifier for a semiconductor memory device, which is provided with a circuit. 2. The current detection type for a semiconductor memory device according to claim 1, wherein the current circuit is interposed between a data bus and a fixed voltage source, and is composed of a pair of transistors whose gates are connected to the data bus. Data bus amplifier. 3. The current circuit comprises a pair of resistance elements interposed between a data bus and a fixed voltage flow.
A current detection type data bus amplifier for a semiconductor memory device as described.