KR100924351B1 - Buffer circuit - Google Patents

Abstract

The present invention relates to a buffer circuit, comprising: a signal input unit including a driver for driving an internal signal at a power supply voltage level in response to an external signal input thereto, and an enable element for driving the driver in response to an enable signal; And a level shifter for level shifting the internal signal to an internal voltage level and a delay unit driven by the internal voltage to delay the output signal of the level shifter by a predetermined period.

Low Power, Level Shifter, Buffer, Clock Signal, VPERI

Description

Buffer circuit {BUFFER CIRCUIT}

The present invention relates to a buffer circuit of a semiconductor memory device, and more particularly, to a buffer circuit capable of reducing power consumption in a low power memory device.

In recent years, the semiconductor memory device has been continuously integrated with high speed and high speed according to the development of technology. Such a semiconductor memory device is composed of a plurality of memory cells, and there are a plurality of operation signals therein for accurately reading or writing desired data together with an external clock signal providing reference timing.

The operation signal is transmitted from the memory controller to the memory device, and the data signal is bidirectionally transmitted between the memory controller and the memory device according to a read / write operation. Therefore, the memory device includes a buffer circuit for receiving an external clock signal, a data signal, and an address signal transmitted from the memory controller, respectively.

1 is a block diagram showing a buffer circuit according to the prior art, Figure 2 is a circuit diagram of FIG.

As shown in FIG. 1, the conventional buffer circuit includes a clock input unit 10, an address input unit 20, a setup / hold unit 30, and an address latch unit 40.

As illustrated in FIG. 2, the clock input unit 10 includes the first driver 11 driving the node n1 in response to the external clock signal CLK1 and the node n1 in response to the enable signal ENB1. The internal clock signal CLK2 is stored in the node n2 by buffering the PMOS transistor PM2 for driving the NMOS transistor, the NMOS transistor NM2 driven in response to the enable signal ENB1, and the signal generated at the node n1. It is composed of a buffer unit 12 for generating a).

The first driver 11 includes a PMOS transistor PM1 driven in response to the external clock signal CLK1 and an NMOS transistor NM1 driven in response to the external clock signal CLK1.

The buffer unit 12 is composed of a plurality of inverters IV1 and IV2.

As illustrated in FIG. 2, the address input unit 20 may include a second driver 11 driving the node n3 in response to the address signal ADD1, and a node driven in response to the enable signal ENB1. PMOS transistor PM4 driving n3) and NMOS transistor NM4 driven in response to the enable signal ENB1.

The second driver 21 includes a PMOS transistor PM3 driven in response to the address signal ADD1 and an NMOS transistor NM3 driven in response to the address signal ADD1.

The setup / hold section 30 is composed of a plurality of inverters IV3 to IV6 and resistors R1 and R2.

The address latch unit 40 receives the address signal ADD3 through the transfer unit 41 and the transfer unit 41 driven in response to the internal clock signal CLK2 generated by the clock input unit 10, and the internal clock. The latch 42 latches in response to the signal CLK2.

The transmission part 41 is comprised with the inverter IV9 which is driven in response to the internal clock signal CLK2.

The latch 42 is an inverter IV11 driven in response to the internal clock signal CLK2, and an inverter IV10 which latches the address signal ADD3 together with the inverter IV11 when the inverter IV11 is enabled. It is composed.

The operation of the conventional address buffer circuit configured as described above is as follows.

First, the clock input unit 10 receives the external clock signal CLK1 and generates an internal clock signal CLK2. More specifically, the first driver 11 is enabled as the NMOS transistor NM2 is turned on in response to the high level enable signal ENB1. The first driver 11 generates a signal having a power supply voltage VDDI level at the node n1 in response to the external clock signal CLK1. The buffer unit 12 generates an internal clock signal CLK2 by buffering the signal generated at the node n1.

The address input unit 20 receives the address signal ADD1 and generates an address signal ADD2. More specifically, the second driver 21 is enabled as the NMOS transistor NM4 is turned on in response to the high level enable signal ENB1. The second driver 21 generates an address signal ADD2 having a power supply voltage VDDI level at the node n3 in response to the address signal ADD1.

The setup / hold unit 150 generates an address signal ADD3 which delays the input address signal ADD2 to secure the setup and hold time.

The address latch unit 40 receives and latches the address signal ADD3 from the setup / hold unit 30 in response to the internal clock signal CLK2. In more detail, when the transmission unit 41 is enabled in response to the internal clock signal CLK2, the latch 42 is disabled so that the address signal ADD3 is directly transmitted to the address signal ADD4 through the inverter IV12. Is output. On the other hand, when the transfer unit 41 is disabled, the latch 42 is enabled so that the address signal ADD3 is latched to the latch unit 42 and output as the address signal ADD4.

As described above, the clock input unit 10 and the address input unit 20 are operated by the power supply voltage VDDI, and the setup / hold unit 30 and the address latch unit 40 are operated by the internal voltage VPERI.

Conventional buffer circuits have a problem in that power consumption increases with increasing processing speed of low-power memory devices, in particular, mobile memory devices, thereby degrading the overall operating capability of devices equipped with memory devices.

Accordingly, the present invention receives an operation signal such as an external clock signal, an address signal and a data signal through an input buffer driven at a power supply voltage VDDQ of a level lower than that of the conventional power supply voltage VDDI, and consumed to transmit the operation signal. A buffer circuit that can reduce power consumption is disclosed.

To this end, an embodiment of the present invention includes a signal input unit including a driver for driving an internal signal at a power supply voltage level in response to an external signal input thereto and an enable element for driving the driver in response to an enable signal; It provides a buffer circuit comprising a level shifter for level-shifting the internal signal to the internal voltage level, and a delay unit driven by the internal voltage for delaying the output signal of the level shifter by a predetermined period.

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According to an embodiment of the present invention, a clock input unit receives a first clock signal and generates a second clock signal having a power supply voltage level, and a first level shifter for level shifting and outputting the second clock signal to an internal voltage level. And a signal input unit configured to receive the first signal and generate a second signal having a power supply voltage level, a second level shifter for level shifting the second signal to an internal voltage level, and a second level shifter for driving the internal voltage. A delay circuit for delaying an output signal of a second level shifter by a predetermined period and a latch unit driven by the internal voltage to latch an output signal of the delay unit in response to the second clock signal are provided.

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Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

3 is a block diagram illustrating a buffer circuit according to an exemplary embodiment of the present invention, and FIG. 4 is a circuit diagram of FIG. 3.

First, as shown in FIG. 3, the buffer circuit according to the embodiment of the present invention includes a clock input unit 110, a level shifter 120 and 140, an address input unit 130, a setup / hold unit 150, and an address latch unit 160. It is configured to include).

As illustrated in FIG. 4, the clock input unit 110 may include a first driver 111 driving the node n11 in response to the external clock signal CLK11 and a node n11 in response to the enable signal ENB11. ) And a PMOS transistor (PM12) for driving the NMOS transistor NM12 for enabling the first driver 111 in response to the enable signal (ENB11).

The first driver 111 includes a PMOS transistor PM11 driven in response to the external clock signal CLK11 and an NMOS transistor NM11 driven in response to the external clock signal CLK11.

The first level shifter 120 includes an NMOS transistor NM16 driven in response to the internal clock signal CLK12, an NMOS transistor NM15 turned on in response to an internal voltage VPERI, and an NMOS transistor NM15. And a PMOS transistor PM16 driven by a node n13 connected to the PMOS transistor PM16 and a PMOS transistor PM15 driven by a node n14 connected to the NMOS transistor NM16.

 The address input unit 130 includes a second driver 131 for driving the node n12 in response to the address signal ADD11, and a PMOS transistor PM14 for driving the node n12 in response to the enable signal ENB11. And an NMOS transistor NM14 for enabling the second driver 131 in response to the enable signal ENB11.

The second driver 131 includes a PMOS transistor PM13 driven in response to the address signal ADD11 and an NMOS transistor NM13 driven in response to the address signal ADD11.

The second level shifter 140 includes an NMOS transistor NM18 driven in response to the address signal ADD12, an NMOS transistor NM17 turned on in response to an internal voltage VPERI, and an NMOS transistor NM17. A PMOS transistor PM18 driven by the connected node n16 and a PMOS transistor PM17 driven by the node n17 connected to the NMOS transistor NM18 are included.

The setup / hold unit 150 includes a plurality of inverters IV22 to IV26 that buffer the address signal ADD13 and a plurality of resistors R11 and R12 that delay the address signal ADD13.

The address latch unit 160 receives the address signal ADD14 through the transfer unit 161 which is driven in response to the internal clock signal CLK13, and latches in response to the internal clock signal CLK13. It is configured to include a latch portion 162.

The transmission unit 161 includes an inverter IV29 driven in response to the internal clock signal CLK13.

The latch unit 162 includes an inverter IV31 driven in response to the internal clock signal CLK13, and an inverter IV30 which latches the address signal ADD14 together with the inverter IV31 when the inverter IV31 is enabled. It is configured to include.

The operation of the address buffer circuit configured as described above is as follows.

First, the clock input unit 110 receives the external clock signal CLK11 and generates the internal clock signal CLK11. More specifically, the first driver 111 is enabled while the NMOS transistor NM12 is turned on in response to the high level enable signal ENB11, and the enabled first driver 111 is an external clock. The internal clock signal CLK12 is generated at the node n11 by buffering the signal CLK11. In this case, the generated internal clock signal CLK12 is a signal that swings between the power supply voltage VDDQ and the ground voltage VSSQ. As described above, since the clock input unit 110 operates at a lower level than the conventional power supply voltage VDDQ, the input external clock signal CLK11 may be at a lower level than the conventional one. Therefore, the power consumption of generating the external clock signal CLK11 and transmitting it to the clock input unit 110 is reduced. Here, the power supply voltage VDDQ is set to about 1.2V, which is lower than the power supply voltage VDDI of about 1.8V conventionally used.

Next, the first level shifter 120 receives an internal clock signal CLK12 that swings between the power supply voltage VDDQ and the ground voltage VSSQ, and then swings the internal voltage VPERI and the ground voltage VSS. The clock signal CLK13 is generated.

On the other hand, the address input unit 130 receives the address signal ADD11 and generates the address signal ADD12. More specifically, the second driver 131 is enabled when the NMOS transistor NM14 is turned on in response to the high level enable signal ENB11. At this time, the second driver 131 receives the address signal ADD11 and buffers it with the power supply voltage VDDQ to generate the address signal ADD12 at the node n12. In this case, the generated address signal ADD12 is a signal swinging between the power supply voltage VDDQ and the ground voltage VSSQ. As described above, since the address input unit 130 operates with the power supply voltage VDDQ at a lower level than the conventional clock input unit 110, the input address signal ADD11 may be lower than the conventional level. Therefore, power consumption of generating and transmitting the address signal ADD11 to the address input unit 130 is reduced.

The second level shifter 140 receives an address signal ADD12 swinging between the power supply voltage VDDQ and the ground voltage VSSQ and swings an address signal ADD13 swinging between the internal voltage VPERI and the ground voltage VSS. )

The setup / hold unit 150 generates the address signal ADD14 by delaying the input address signal ADD13 to secure the setup and hold time.

The address latch unit 160 receives and latches the address signal ADD14 from the setup / hold unit 150 in response to the internal clock signal CLK13. More specifically, when the transmission unit 161 is enabled in response to the internal clock signal CLK13, the latch 162 is disabled so that the address signal ADD14 is buffered by the inverter IV20 and the inverter IV22. The signal is output as the address signal ADD15. On the other hand, when the transfer unit 161 is disabled, the latch 162 is enabled to latch the address signal ADD14 and output the address signal ADD15 through the inverter IV32.

As described above, the setup / hold unit which operates the internal clock signal CLK12 and the address signal ADD12 buffered with the power voltage VDDQ, which is a voltage lower than the internal voltage VPERI, operates as the internal voltage VPERI. When input to the 150 and the address latch unit 160, current leakage occurs when the PMOS transistors used in the circuit configuration are turned off. Therefore, as in the exemplary embodiment of the present invention, the internal clock signal CLK12 and the address signal ADD12 may be level shifted to the internal voltage VPERI level to suppress current leakage of the PMOS transistor.

1 is a block diagram showing a buffer circuit according to the prior art.

2 is a circuit diagram of FIG.

3 is a block diagram illustrating a buffer circuit according to an exemplary embodiment of the present invention.

4 is a circuit diagram of FIG.

<Description of the symbols for the main parts of the drawings>

110: clock input unit 120, 140: level shifter

130: address input section 150: setup / hold section

160: address latch unit CLK11: external clock signal

CLK12, CLK13: Internal clock signal ADD11 to ADD15: Address signal

VDDQ: Supply Voltage VPERI: Internal Voltage

VSS: Ground Voltage

Claims (14)

A signal input unit including a driving unit driving an internal signal at a power supply voltage level in response to an external signal input and an enable element driving the driving unit in response to an enable signal; A level shifter for level shifting the internal signal to an internal voltage level and outputting the level shifter; And And a delay unit which is driven by the internal voltage to delay the output signal of the level shifter by a predetermined period. The buffer circuit of claim 1, wherein the external signal is a data signal or an address signal. The buffer circuit of claim 1, wherein the power supply voltage is at a level lower than the internal voltage. The buffer circuit of claim 1, wherein the internal voltage is a VPERI voltage used in a peripheral circuit region of a semiconductor memory device. delete The buffer circuit of claim 1, wherein the delay unit generates a delay section for securing a setup and hold time of an output signal of the level shifter. A clock input unit configured to receive the first clock signal and generate a second clock signal having a power supply voltage level; A first level shifter for level shifting the second clock signal to an internal voltage level; A signal input unit receiving the first signal and generating a second signal having a power supply voltage level; A second level shifter for level shifting the second signal to an internal voltage level and outputting the second signal; A delay unit driven by the internal voltage to delay an output signal of the second level shifter by a predetermined period; And And a latch unit driven by the internal voltage to latch an output signal of the delay unit in response to the second clock signal. 8. The buffer circuit of claim 7, wherein the first signal is an address signal or a data signal. 8. The buffer circuit of claim 7, wherein the power supply voltage is at a level lower than the internal voltage. The method of claim 7, wherein the signal input unit A first driver driving the second signal to a power supply voltage level in response to the first signal; And And a first enable element for driving the driver in response to an enable signal. The method of claim 7, wherein the clock input unit A second driver driving the second clock signal at a power supply voltage level in response to the first clock signal; And And a second enable element for driving the second driver in response to an enable signal. 8. The buffer circuit of claim 7, wherein the delay unit generates a delay section for securing a setup and hold time of an output signal of the second level shifter. The method of claim 7, wherein the latch unit A transmission unit driven in response to the second clock signal; And And a latch configured to receive an output signal of the delay unit through the transfer unit and latch the latch in response to the second clock signal. The buffer circuit of claim 13, wherein only one of the transfer unit and the latch is enabled in response to the second clock signal.

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