KR100743634B1 - Command decoding circuit of semiconductor memory device - Google Patents

Abstract

The present invention relates to a command decoding circuit of a semiconductor memory device for reducing leakage current generated when not decoding command signals input from the outside to perform a specific operation. The circuit provides the clock pulse signal CLKP as the enabled pulse signal CLKPD_DEC according to the enable / disable state of the command pulse signals RAS_P and CAS_P or the pulse signal in the disabled state having a fixed potential. A pulse signal generator 100 provided to CLKPD_DEC; Decoder for processing the input data among the command decoders 20 to 70 in synchronization with one of the clock pulse signal CLKP and the pulse signal CLKPD_DEC, a decoder related to burst operation, reading according to the DDR mode and the SDR mode. And a controller 200 that provides control selection signals DIN_CTRL, ICASP_CTRL, and MODE_CTRL for selectively controlling a decoder or the like that participates in a write operation. And a decoding unit 200 which performs decoding by any one of the control selection signals DIN_CTRL, ICASP_CTRL, and MODE_CTRL provided from the control unit 200.

Description

COMMAND DECODING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE

1 is a circuit diagram for explaining a command decoder according to the prior art.

2 is a block diagram illustrating an embodiment of address buffers and command decoders of an instruction decoding circuit of a semiconductor memory device according to the present invention;

2 is a block diagram illustrating a preferred embodiment of an instruction decoding circuit of a semiconductor memory device according to the present invention.

4 is a circuit diagram illustrating a pulse signal generator 100 provided in an instruction decoding circuit according to the present invention.

5 is a waveform diagram illustrating the operation of the control unit 200 provided in the command decoding circuit according to the present invention.

6 is a waveform diagram illustrating the operation of the control unit 200 in the DDR mode.

7 is a waveform diagram illustrating the operation of the control unit 200 in the SDR mode.

8 is a circuit diagram for explaining the operation of the decoding unit 200 included in the instruction decoding circuit according to the present invention.

The present invention relates to a semiconductor memory device, and more particularly, to a command decoding circuit of a semiconductor memory device for decoding command signals input from the outside to perform a specific operation.

In general, the DRAM receives command signals such as a chip select signal CS, a row address strobe signal RAS, a column address strobe signal CAS, and a write enable signal WE from an external device. The combination of command signals performs operations such as active, write, read, precharge, interrupt, and refresh.

The command signals are converted and output as a signal for performing the operation according to the command decoding circuit as shown in FIG. As an example, the operation will be described with reference to FIG. 1 on the assumption that command signals are input to the input signals IN1 to IN4.

The conventional instruction decoding circuit performs a plurality of NAND gates NA1 to NA3 and a plurality of inverters IV1 to IV3 when a clock pulse signal CLKP generating a high level pulse at a predetermined period is input in a high pulse state. Different current path paths are formed according to the state of the decoded decoding signal IN_DEC and the inverted signal INB_DEC.

That is, in the conventional command decoding circuit, when the clock pulse signal CLKP is input in the high pulse state and the input signals IN1 to IN4 are combined to output the high level decoding signal IN_DEC, the NMOS transistor NM1, NM2 is turned on so that current flows in the direction of the arrow PATH_A shown in FIG. 1, and then outputs the enabled output signal OUT through three inverters IV6 to IV8.

In this case, the arrow PATH_A direction of the solid line means a direction of a current flowing through the PMOS transistor PM1, the NMOS transistor NM4, the NMOS transistor NM2, and the NMOS transistor NM1 from the power supply to the ground.

On the other hand, in the conventional command decoding circuit, when the clock pulse signal CLKP is input in the high pulse state and the input signals IN1 to IN4 are combined to output the low level decoding signal IN_DEC, the NMOS transistor NM3 is output. ) Is turned on so that current flows in the direction indicated by the arrow PATH_B of FIG. 1, and then outputs the disabled output signal OUT through the three inverters IV6 to IV8.

In this case, the arrow PATH_B direction indicates the direction of the current flowing through the PMOS transistor PM3, the NMOS transistor NM5, the NMOS transistor NM3, and the NMOS transistor NM1 from the power supply to the ground.

However, in the conventional circuit as shown in FIG. 1, when performing an externally required operation, that is, at least one or more of the command signals are enabled, a current path path is formed in the direction of the solid arrow PATH_A. When the requested operation is not performed, that is, when all of the command signals are disabled, the current path path is formed in the direction of the arrow PATH_B of the dotted line.

As a result, in the conventional circuit that performs decoding in response to the command signal as shown in FIG. 1, the current path path is formed in the direction of the arrow PATH_B of the dotted line even when the required operation is not performed from the outside. There is a problem that consumes.

Accordingly, the present invention was created to solve the problems inherent in the prior art as described above, and an object of the present invention is to reduce current consumption in an instruction decoding circuit when there is no operation request from the outside.

According to an aspect of the present invention for achieving the above object, the command decoding circuit of the semiconductor memory device, the clock pulse signal for generating a high level pulse every predetermined period when the first command signals input from the outside is enabled A pulse signal generator configured to output a pulse signal which is synchronized with the output signal and is disabled when the first command signals are in a disabled state; A controller which is synchronized with any one of the clock pulse signal and the pulse signal and outputs control selection signals for selectively controlling each command decoder by signals used in the operation of a semiconductor memory device; And a decoder configured to decode and output second command signals input from the outside by one of the control selection signals, and to block a discharge path for outputting the decoded signal when the control selection signals are in a disabled state. It is characterized by including.

In the above configuration, the first command signals preferably include at least a row address strobe signal and a column address strobe signal.

In the above configuration, the second command signals preferably include at least one of a row address strobe signal, a column address strobe signal, a chip select signal, and a write enable signal.

In the above configuration, the pulse signal generator includes: first combining means for logically combining the first command signals; First switching means for selecting and outputting any one of a signal having a ground level and a signal having a power supply level according to the state of the signal combined in the combining means; First latch means for latching a signal output from the first switching means; Second latch means for latching a signal latched in said first latching means by said clock pulse signal; Inverting / delaying means for inverting the latched signal by the second latching means and outputting it as a signal for controlling the first switching means; And second combining means for combining the clock pulse signal and the signal latched by the first latching means.

In the above configuration, the first combining means preferably comprises a noah gate for quinoa combining the first command signals and an inverter for inverting the phase of the quinoa combined signal at the noah gate.

In the above configuration, the first switching means comprises: an NMOS transistor for outputting a signal of ground level by the signal combined in the first combining means; A first PMOS transistor for outputting a signal of a power supply level by a signal delayed by the inversion / delay means; And a second PMOS transistor for switching the connection of the first PMOS transistor and the NMOS transistor by a signal combined by the first combining means.

In the above configuration, the second latching means includes: a first pass gate for delivering a signal latched by the first latching means when the clock pulse signal generates a pulse; A first latch for latching a signal transmitted from the first pass gate; A second pass gate that transfers the latched signal in the second latch when the clock pulse signal is in a disabled state; And a second latch for latching a signal transmitted from the second pass gate.

In the above configuration, the second combining means includes a NAND gate for NAND combining the signal latched by the first latching means and the clock pulse signal, and an inverter for inverting the phase of the NAND combined signal at the NAND gate. It is preferable.

In the above configuration, the pulse signal generator is configured to increase the potential of the output node of the first switching means by an inverter means for receiving a power-up signal for initializing an internal element of the semiconductor memory device and a signal output from the inverter means. It is preferable to further comprise a second switching means for raising to a level.

In the above configuration, the control unit may be configured to include a cast light bar signal that maintains a high level for one clock when a write command is requested in a DDR mode state, and a dial signal that maintains a high level during a DDR mode and a low level during an SDR mode. A mode selection decoder controller configured to output a first control selection signal for controlling command decoders involved in read and write operations according to the DDR mode and the SDR mode; An input data decoder control section for outputting a second control selection signal for controlling command decoders for processing data input by the write read bar signal maintaining a high level during a read operation and a low level during a write operation; And a burst decoder control unit configured to output a third control selection signal for controlling the command decoders related to the burst operation by the burst signal maintaining the high level during the burst operation.

In the above configuration, the mode selection decoder control unit outputs a first control selection signal corresponding to the pulse signal in the SDR mode, and inverts a phase in the cast light bar signal in the DDR mode and is synchronized with the clock pulse signal. It is preferable to output the first control selection signal.

In the above configuration, the mode selection control unit includes: first inverter means for inverting a phase of the cast light bar signal; Combining means for NAND combining the signal inverted in the inverter means and the clock pulse signal; Second inverter means for inverting the phase of the pulse signal; Transmission means for selecting and transmitting any one of a signal inverted by the second inverter means and a NAND combined signal by the combining means according to the state of the dial signal; And third inverter means for inverting the phase of the signal transmitted from the transmission means and outputting the signal as the first control selection signal.

In the above arrangement, the transmitting means includes a first pass gate for transmitting a NAND combined signal in the combining means when the dial signal is at a high level, and inverted in the second inverter means when the dial signal is at a low level. It is preferably composed of a second pass gate that carries a signal.

In the above configuration, the input data decoder control unit preferably outputs the second control selection signal synchronized with the clock pulse signal during a read operation and maintaining a low level during the write operation.

In the above configuration, the input data decoder controller is configured to perform NAND combining of the write lead bar signal and the clock pulse signal, and inverts the phase of the NAND combined signal by the combining means to output the second control selection signal. It is preferable to include an inverter means.

In the above arrangement, it is preferable that the burst decoder control unit outputs the third control selection signal which is synchronized with the clock pulse signal during the burst operation and which maintains the low level when the burst operation is not performed.

In the above configuration, the burst decoder control unit includes combining means for NAND combining the burst signal and the clock pulse signal, and inverter means for inverting a phase of the NAND combined signal in the combining means and outputting the third control selection signal as the third control selection signal. It is preferable to include.

In the above configuration, the decoding unit comprises: combining means for outputting a decoded signal obtained by decoding the second command signals and an inverted decoded signal inverting a phase of the decoded signal; Amplifying means operated by any one of said control selection signals, for amplifying a potential difference between said decoded signal and said inverted decoded signal; And output means for inverting and delaying the signal output from the amplifying means to output the output signal.

According to another aspect of the present invention for achieving the above object, the command decoding circuit of a semiconductor memory device, the first signal and the phase of the first signal is inverted by decoding the first command signals input from the outside; A decoding unit outputting two signals; When the clock pulse signal generating the high level pulse every predetermined period is high level, the clock signal is synchronized with any one of the pulse signal and the clock pulse signal synchronized with the second command signals inputted from the outside. A control unit for outputting control selection signals for controlling respective command decoders by signals used; An amplifying unit operating by any one of the first to third control selection signals to comparatively amplify the potential difference between the first and second signals; And an output unit for inverting and delaying the signal output from the amplifying unit to output the output signal.

In the above configuration, the first command signals preferably include at least one of a row address strobe signal, a column address strobe signal, a chip select signal, and a write enable signal.

In the above configuration, the second command signals preferably include at least a row address strobe signal and a column address strobe signal.

In the above configuration, the control unit may include a pulse signal generation unit configured to output the pulse signal synchronized with the clock pulse signal when the second command signals are enabled and disabled when the second command signals are disabled; And a control selection signal generator which is synchronized with any one of the clock pulse signal and the pulse signal and outputs the control selection signals by signals used in the operation of the semiconductor memory device.

In the above configuration, the pulse signal generator includes: first combining means for logically combining the first command signals; First switching means for selecting and outputting any one of a signal having a ground level and a signal having a power supply level according to the state of the signal combined in the combining means; First latch means for latching a signal output from the first switching means; Second latch means for latching a signal latched in said first latching means by said clock pulse signal; Inverting / delaying means for inverting the latched signal by the second latching means and outputting it as a signal for controlling the first switching means; And second combining means for combining the clock pulse signal and the signal latched by the first latching means.

In the above configuration, the first combining means preferably comprises a noah gate for quinoa combining the first command signals and an inverter for inverting the phase of the quinoa combined signal at the noah gate.

In the above configuration, the first switching means comprises: an NMOS transistor for outputting a signal of ground level by the signal combined in the first combining means; A first PMOS transistor for outputting a signal of a power supply level by a signal delayed by the inversion / delay means; And a second PMOS transistor for switching the connection of the first PMOS transistor and the NMOS transistor by a signal combined by the first combining means.

In the above configuration, the second latching means may include: a first pass gate for delivering a signal latched by the first latching means when the clock pulse signal generates a pulse; A first latch for latching a signal transmitted from the first pass gate; A second pass gate for delivering a signal latched in the second latch when the clock pulse signal is in a disabled state; And a second latch for latching a signal transmitted from the second pass gate.

In the above configuration, the second combining means includes a NAND gate for NAND combining the signal latched by the first latching means and the clock pulse signal, and an inverter for inverting the phase of the NAND combined signal at the NAND gate. It is preferable.

In the above configuration, the pulse signal generator is configured to increase the potential of the output node of the first switching means by an inverter means for receiving a power-up signal for initializing an internal element of the semiconductor memory device and a signal output from the inverter means. It is preferable to further comprise a second switching means for raising to a level.

In the above configuration, the control selection signal generation unit may include a cas light bar signal that maintains a high level for one clock when the write command is requested in the DDR mode state, and a dial that maintains the high level during the DDR mode and the low level during the SDR mode. A mode selection decoder controller configured to output a first control selection signal for controlling command decoders involved in read and write operations according to the DDR mode and the SDR mode by a signal; An input data decoder control section for outputting a second control selection signal for controlling command decoders for processing data input by the write read bar signal maintaining a high level during a read operation and a low level during a write operation; And a burst decoder controller for outputting a third control selection signal for controlling command decoders related to the burst operation by a burst signal maintaining a high level during the burst operation.

In the above configuration, the mode selection decoder control unit outputs a first control selection signal corresponding to the pulse signal in the SDR mode, and inverts a phase in the cast light bar signal in the DDR mode and is synchronized with the clock pulse signal. It is preferable to output the first control selection signal.

In the above configuration, the mode selection control unit includes: first inverter means for inverting a phase of the cast light bar signal; Combining means for NAND combining the signal inverted in the inverter means and the clock pulse signal; Second inverter means for inverting the phase of the pulse signal; Transmission means for selecting and transmitting any one of a signal inverted by the second inverter means and a NAND combined signal by the combining means according to the state of the dial signal; And third inverter means for inverting the phase of the signal transmitted from the transmission means and outputting the signal as the first control selection signal.

In the above arrangement, the transmitting means includes a first pass gate for transmitting a NAND combined signal in the combining means when the dial signal is at a high level, and inverted in the second inverter means when the dial signal is at a low level. It is preferably composed of a second pass gate that carries a signal.

In the above configuration, the input data decoder control unit preferably outputs the second control selection signal synchronized with the clock pulse signal during a read operation and maintaining a low level during the write operation.

In the above configuration, the input data decoder controller is configured to perform NAND combining of the write lead bar signal and the clock pulse signal, and inverts the phase of the NAND combined signal by the combining means to output the second control selection signal. It is preferable to include an inverter means.

In the above arrangement, it is preferable that the burst decoder control unit outputs the third control selection signal which is synchronized with the clock pulse signal during the burst operation and which maintains the low level when the burst operation is not performed.

In the above configuration, the burst decoder control unit includes combining means for NAND combining the burst signal and the clock pulse signal, and inverter means for inverting a phase of the NAND combined signal in the combining means and outputting the third control selection signal as the third control selection signal. It is preferable to include.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiment of the present invention is applied to a circuit having a block diagram as shown in FIG. FIG. 2 illustrates some of a plurality of address buffers and command decoders included in the semiconductor memory device, and the command decoders 20 to 70 illustrated in FIG. 2 are respectively used for command decoders and burst operations to process data. Related command decoders may be classified into command decoders involved in read and write operations according to a double data rate (DDR) mode and a single data rate (SDR) mode.

Specifically, FIG. 2 shows the address signals ADD <0:12> as command signals and the inverted command signals CSB, RASB after buffering the command signals CS, RAS, CAS, and WE inputted from the outside. , CASB, WEB) are provided, and a clock pulse signal CLKP is provided for synchronization of these signals.

In addition, the address buffer 10 and the command decoders 20 to 70 are configured in FIG. 2, and each of the command decoders 20 to 70 is formed of each of the inverted command signals CSB, RASB, CASB, and WEB. Selectively receives and decodes signals according to an operation, and the address buffer 10 receives an address ADD <0:12> corresponding to an operation performed by a combined signal in each of the command decoders 20 to 70. Latch.

Here, the address buffer 10 and the command decoders 20 to 70 each include a pulse signal generator 100, a controller 200, and a decoder 300 as shown in FIG. 3.

The pulse signal generator 100 may provide the clock pulse signal CLKP as the enabled pulse signal CLKPD_DEC or disable the fixed pulse signal according to the enable / disable states of the command pulse signals RAS_P and CAS_P. Provided by the pulse signal (CLKPD_DEC) of the state.

The control unit 200 may further include command decoders for processing input data among the command decoders 20 to 70 shown in FIG. 2 in synchronization with one of the clock pulse signal CLKP and the pulse signal CLKPD_DEC; Provides control selection signals DIN_CTRL, ICASP_CTRL, and MODE_CTRL for selectively controlling command decoders related to burst operation, command decoders involved in read and write operations according to DDR mode and SDR mode.

The decoding unit 300 performs decoding by any one of the control selection signals DIN_CTRL, ICASP_CTRL, and MODE_CTRL provided from the control unit 200.

Specifically, the operation of the embodiment will be described with reference to FIGS. 4 to 8.

As shown in FIG. 4, the pulse signal generator 100 uses the command pulse signals RAS_P and CAS_P because one of the command pulse signals RAS_P and CAS_P generates a high pulse to perform a specific operation. As a result, a pulse signal CLKPD_DEC for controlling the decoding unit 300 is generated.

Referring to the operation of the pulse signal generator 100 in detail, first, the PMOS transistor PM5 is turned on by receiving the power-up signal POWERUP inverted by the inverter IV9 to turn the potential of the node ND1 high. Raise to level. Therefore, the pulse signal generator 100 outputs the low level pulse signal CLKPD_DEC by the NAND gate NA4 regardless of the state of the clock pulse signal CLKP. That is, the pulse signal generator 100 is initialized when the power up signal POWERUP is enabled. Here, the power up signal POWERUP is a signal for initializing internal elements of the semiconductor memory device.

Then, when the power-up signal POWERUP is disabled and one of the command pulse signals RAS_P and CAS_P is input in a high pulse state, that is, when a specific command is input from the outside, the NMOS transistor NM6 is turned on. The potential of the node ND1 is then lowered to the ground level. Therefore, the latch signal CLKPD is maintained at the high level by the latch LAT1.

In this state, when the clock pulse signal CLKP is input as a high pulse, the NAND gate NA4 and the inverter IV15 NAND a combination of the high level latch signal CLKPD and the high level clock pulse signal CLKP. After the phase is inverted, it is output as a high level output signal (CLKPD_DEC). Since the pass gate PG1 is turned on by the clock pulse signal CLKP, the latch LAT2 receives and latches the latch signal CLKPD having a high level.

As such, when the pulse signal generator 100 receives one of the command pulse signals RAS_P and CAS_P in the high pulse state and the clock pulse signal CLKP is input in the high pulse state, the pulse signal in the enable state ( CLKPD_DEC) is printed.

After that, since the clock pulse signal CLKP is in a low level state, the latch LAT3 receives and latches a signal having a low level potential by the operation of the pass gate PG2. In addition, since the NAND gate NA4 receives the low level clock pulse signal CLKP, the NAND gate NA4 outputs a high level signal regardless of the state of the latch signal CLKPD, and then the inverter IV15 receives the NAND gate NA4. Inverts the phase of the signal output from the N-axis output as a low-level pulse signal (CLKPD_DEC).

Then, the three inverters IV12 to IV14 delay and invert the signal output from the latch LAT3 to the node ND2, and then the PMOS transistor PM6 is driven by the signal output from the inverter IV14. It is turned on to transfer the potential of the power supply level to the PMOS transistor PM7.

At this time, since the command pulse signals RAS_P and CAS_P are pulse signals, the PMOS transistor PM7 remains turned on before the PMOS transistor PM6 is turned on. Therefore, the potential of the node ND1 rises to the power supply level by the operation of the PMOS transistors PM6 and PM7.

Since the latch LAT1 latches the potential of the node ND1, the latch LAT1 outputs the low level latch signal CLKPD, and the NAND gate NA4 receives the low level latch signal CLKPD, thereby providing a clock pulse. A high level signal is output regardless of the state of the signal CLKP. Therefore, the pulse signal CLKPD_DEC is maintained at the low level.

As described above, the pulse signal generator 100 inputs one of the command pulse signals RAS_P and CAS_P in the high pulse state and the clock pulse signal CLKP is input in the high pulse state, and then the clock pulse signal CLKP is input. The pulse signal CLKPD_DEC is output when the low level state is reached.

Then, the pulse signal generator 100 keeps the disabled state of the pulse signal CLKPD_DEC regardless of the state of the clock pulse signal CLKP since the command pulse signals RAS_P and CAS_P are both at low level. .

The controller 200 may be implemented with a circuit as shown in FIG. 5. That is, the controller 200 includes a mode selection decoder controller 210, an input data decoder controller 220, and a burst decoder controller 230, and the signals CAS_WTB, DDR, and WT_RDB used for the operation of the semiconductor memory device. Using YBURST, the control selection signals DIN_CTRL, ICASP_CTRL, and MODE_CTRL are synchronized with one of the clock pulse signal CLKP and the pulse signal CLKPD_DEC.

In detail, referring to FIGS. 5 to 7, in the mode selection decoder controller 210, the inverter IV16 may maintain a low level for one clock when the write command is requested in the DDR mode state (CAS_WTB). ) Is inverted and output to the NAND gate NA5, and the NAND gate NA5 outputs the NAND combination of the signal transmitted from the inverter IV16 and the clock pulse signal CLKP to the pass gate PG2.

That is, the NAND gate NA5 outputs a signal having a level corresponding to the cas light bar signal CAS_WTB when the clock pulse signal CLKP is at a high level, and the cas light when the clock pulse signal CLKP is at a low level. The high level outputs the signal regardless of the state of the bar signal CAS_WTB.

In addition, the pass gate PG2 determines whether to transmit a signal output from the NAND gate NA5 according to the state of the DL signal DDR that maintains a high level in the DDR mode and a low level in the SDR mode. The pass gate PG1 determines whether to transfer the pulse signal CLKPD_DEC inverted by the inverter IV17 according to the state of the dial signal DDR.

Thereafter, the inverter IV19 inverts the signal transmitted from one of the pass gate PG1 and the pass gate PG2 to control the command decoders involved in the read and write operations according to the DDR mode and the SDR mode. Print (MODE_CTRL).

As described above, the mode selection decoder controller 210 outputs the control selection signal MODE_CTRL corresponding to the pulse signal CLKPD_DEC in the SDR mode, and in FIG. 7 in the DDR mode. As described above, the phase is inverted in the casright bar signal CAS_WTB and the control selection signal MODE_CTRL that is synchronized with the clock pulse signal CLKP is output.

Next, in the input data decoder controller 220, the NAND gate NA6 performs a NAND combination of the write lead bar signal WT_RDB and the clock pulse signal CLKP, which maintain a high level during a read operation and a low level during a write operation. To the inverter IV20.

Thereafter, the inverter IV20 inverts the signal output from the NAND gate NA6 and outputs a control selection signal DIN_CTRL for controlling command decoders for processing the input data.

That is, the input data decoder controller 220 outputs the control selection signal DIN_CTRL that is synchronized with the clock pulse signal CLKP during the read operation and maintains the low level during the write operation, as shown in FIGS. 6 and 7. do.

Next, in the burst decoder control unit 230, the NAND gate NA7 NAND-combines the burst signal YBURST and the clock pulse signal CLKP maintaining a high level during the burst operation to the inverter IV21.

Thereafter, the inverter IV21 inverts the signal output from the NAND gate NA7 and outputs a control selection signal DIN_CTRL for controlling the command decoders related to the burst operation.

That is, the burst decoder controller 230 outputs a control selection signal DIN_CTRL that is synchronized with the clock pulse signal CLKP during the burst operation and maintains a low level when the burst decoder control operation is not performed.

The decoding unit 300 may be implemented with a circuit as shown in FIG. 8. That is, the decoding unit 300 combines the command signals IN1 to IN4 input from the outside and outputs the combined decoding signal IN_DEC and the inverted decoding signal INB_DEC whose phases of the decoding signal IN_DEC are inverted. 310; It operates by one of the control selection signals DIN_CTRL, ICASP_CTRL, and MODE_CTRL, and changes the potential level state of the nodes ND4 and ND5 by comparing and amplifying the potential difference between the decoding signal IN_DEC and the inverted decoding signal INB_DEC. Amplifying unit 320 to make; And an output unit 330 which outputs the signal having the potential level of the node ND3 to the output signal OUT by delaying an inversion.

The operation of the decoding unit 300 having the above configuration will be described in detail with reference to FIGS. 6 to 8. In an embodiment, FIG. 6 illustrates a decoder 300 included in command decoders for processing input data among a plurality of command decoders, and the command decoder is involved in read and write operations according to DDR mode and SDR mode. These are controlled by the control selection signal MODE_CTRL, and the command decoders related to the burst operation are controlled by the control selection signal ICASP_CTRL.

First, the combination unit 310 combines the command signals IN1 to IN4 through the plurality of NAND gates NA8 to NA10 and the plurality of inverters IV22 to IV24 to decode the signal IN_DEC and the inverted decoding signal INB_DEC. ) Here, the command signals IN1 to IN4 are buffered with the command signals RAS, CAS, WE, and CS that are input to perform memory operations, and then inverted from the command signals CSB, RASB, CASB, and WEB. Corresponding.

That is, the combination unit 310 outputs the low level decoding signal IN_DEC and the high level inverted decoding signal INB_DEC when no command is input from the outside, and the high level decoding when the command is input from the outside. The signal IN_DEC and the low level inverted decoding signal INB_DEC are output.

In this case, since the control selection signal DIN_CTRL is disabled, the NMOS transistor PM7 included in the amplifier 320 is turned off to form a current path path between the node ND3 and the ground, and the amplifier 320 is not formed. The PMOS transistors PM9 and PM11 provided in FIG. 9 are turned on to transmit a signal having a power supply level to the NMOS transistor NM7.

Accordingly, the amplifier 320 does not form a current path path between the node ND3 and ground, and simultaneously precharges the nodes ND4 and ND5 regardless of the potential level state of the decoding signal IN_DEC.

Subsequently, when the decoding unit 310 outputs the high level decoding signal IN_DEC, since the control selection signal DIN_CTRL is enabled, the NMOS transistors NM7 and NM8 are turned on and the NMOS transistor NM9 is turned off. do.

Accordingly, the amplifier 320 lowers the potential of the node ND4 to the ground level by operating the PMOS transistors PM8 and PM10 and the NMOS transistors NM10 and NM11, and simultaneously moves the potential of the node ND5 to the power supply level. Raise.

When the decoding unit 310 outputs the low level decoding signal IN_DEC, since the control selection signal DIN_CTRL is enabled, the NMOS transistors NM7 and NM9 are turned on and the NMOS transistor NM8 is turned off. do.

Therefore, the amplifier 320 lowers the potential of the node ND5 to the ground level by the operation of the PMOS transistors PM8 and PM10 and the NMOS transistors NM10 and NM11, and simultaneously moves the potential of the node ND4 to the power supply level. Raise.

Thereafter, the output unit 330 inverts and delays the signal having the potential of the node ND4 through the plurality of inverters VI27 to IV29 connected in series to output the output signal OUT.

That is, as shown in FIGS. 6 to 8, when the output unit 330 requests external write operation related commands 'WT0' and 'WT1' and read operation related commands 'RD0' and 'RD1'. , The control selection signals DIN_CTRL, ICASP_CTRL, and MODE_CTRL are enabled, so that the write operation entry signal 'CASP6_WT', the read operation entry signal 'CASP6_RD', and the burst operation signal 'ICASP6' are output signals (OUT). Print each.

As described above, when the instruction decoding circuit according to the present invention does not operate, that is, when the decoding signal IN_DEC is at the low level, no current path path is formed between the node ND3 and the ground. This is because the semiconductor memory device is controlled by one of the control selection signals DIN_CTRL, ICASP_CTRL, and MODE_CTRL which are only enabled when the semiconductor memory device operates the corresponding instruction decoder to perform a specific operation.

In other words, the command decoding circuit according to the present invention synchronizes one of the clock pulse signal CLKP and the pulse signal CLKPD_DEC using the signals CAS_WTB, DDR, WT_RDB, and YBURST used in the operation of the semiconductor memory device. The control selection signals DIN_CTRL, ICASP_CTRL, and MODE_CTRL are output.

In addition, the control selection signals DIN_CTRL, ICASP_CTRL, and MODE_CTRL are provided as control signals of the corresponding command decoders, respectively. Command decoders involved in read and write operations are controlled.

For example, when the semiconductor memory device performs an operation of processing input data, the instruction decoding circuit according to the present invention operates only the instruction decoders used for the operation, and the other unused decoders control control signals ICASP_CTRL. MODE_CTRL does not form a current path path between node ND3 and ground.

Therefore, the instruction decoding circuit according to the present invention has the effect that the current pass path is formed only in the operating command decoder, and the remaining non-operating command decoders do not form the current pass path, thereby reducing the current consumption when not operating.

Therefore, according to the present invention, except for the command decoders operated by the operation command input from the outside, the current decoder does not form a current path path between the power source, thereby reducing the current consumption.

Claims (36)

A pulse signal that outputs a pulse signal that is synchronized with a clock pulse signal that generates a high level pulse every predetermined period when the first command signals input from the outside are enabled, and is disabled when the first command signals are disabled Generator; A controller which is synchronized with any one of the clock pulse signal and the pulse signal and outputs control selection signals for selectively controlling each command decoder by signals used in the operation of a semiconductor memory device; And A decoder unit for decoding and outputting second command signals input from the outside by one of the control selection signals, and blocking a discharge path for outputting the decoded signal when the control selection signals are in a disabled state; And a command decoding circuit of the semiconductor memory device. The method of claim 1, And the first command signals comprise at least a row address strobe signal and a column address strobe signal. The method of claim 1, And the second command signals include at least one of a row address strobe signal, a column address strobe signal, a chip select signal, and a write enable signal. The method of claim 1, The pulse signal generator, First combining means for logically combining the first command signals; First switching means for selecting and outputting any one of a signal having a ground level and a signal having a power supply level according to the state of the signal combined in the combining means; First latch means for latching a signal output from the first switching means; Second latch means for latching a signal latched in said first latching means by said clock pulse signal; Inverting / delaying means for inverting the latched signal by the second latching means and outputting it as a signal for controlling the first switching means; And And second combining means for combining the clock pulse signal and the signal latched by the first latching means. The method of claim 4, wherein The first combining means, A noah gate for quinoa combining the first command signals; And an inverter for inverting the phase of the quinoa combined signal at the noah gate. The method of claim 4, wherein The first switching means, An NMOS transistor for outputting a signal at ground level by the signal combined in the first combining means; A first PMOS transistor for outputting a signal of a power supply level by a signal delayed by the inversion / delay means; And And a second PMOS transistor for switching the connection of the first PMOS transistor and the NMOS transistor by a signal combined by the first combining means. The method of claim 4, wherein The second latch means, A first pass gate for transferring the latched signal in the first latching means when the clock pulse signal generates a pulse; A first latch for latching a signal transmitted from the first pass gate; A second pass gate that transfers the latched signal in the second latch when the clock pulse signal is in a disabled state; And And a second latch for latching a signal transmitted from the second pass gate. The method of claim 4, wherein The second combining means, A NAND gate NAND combining the signal latched by the first latch means and the clock pulse signal; And an inverter for inverting the phase of the NAND combined signal in the NAND gate. The method of claim 4, wherein The pulse signal generator is configured to increase the potential of the output node of the first switching means to a high level by an inverter means receiving a power-up signal for initializing an internal element of the semiconductor memory device and a signal output from the inverter means. And a second switching means. The method of claim 1, The control unit, Read according to DDR mode and SDR mode by the Cast Light Bar signal which maintains high level for one clock when the write command is requested in DDR mode and the dial signal which maintains high level during DDR mode and low level during SDR mode. And a mode selection decoder controller for outputting a first control selection signal for controlling command decoders involved in the write operation. An input data decoder control section for outputting a second control selection signal for controlling command decoders for processing data input by the write read bar signal maintaining a high level during a read operation and a low level during a write operation; And And a burst decoder controller configured to output a third control selection signal for controlling the command decoders related to the burst operation by a burst signal that maintains a high level during the burst operation. The method of claim 10, The mode selection decoder control unit outputs a first control selection signal corresponding to the pulse signal in the SDR mode, and in the DDR mode, the first control synchronized with the clock pulse signal when the phase is inverted in the cast light bar signal. And a command decoding circuit for outputting a selection signal. The method of claim 10, The mode selection control unit, First inverter means for inverting the phase of the cast light bar signal; Combining means for NAND combining the signal inverted in the inverter means and the clock pulse signal; Second inverter means for inverting the phase of the pulse signal; Transmission means for selecting and transmitting any one of a signal inverted by the second inverter means and a NAND combined signal by the combining means according to the state of the dial signal; And And third inverter means for inverting a phase of the signal transmitted from the transfer means and outputting the first control selection signal. The method of claim 12, The delivery means, A first pass gate for transferring a NAND combined signal in the combining means when the dial signal is at a high level; And a second pass gate which transfers the inverted signal by the second inverter means when the digital signal is at a low level. The method of claim 10, And the input data decoder controller outputs the second control select signal synchronized with the clock pulse signal during a read operation and maintained at a low level during a write operation. The method of claim 10, The input data decoder control unit, Combining means for NAND combining the write lead bar signal and the clock pulse signal; And inverter means for inverting the phase of the NAND combined signal by the combining means and outputting the second control selection signal as the second control selection signal. The method of claim 10, And a burst decoder controller outputs said third control selection signal synchronized with said clock pulse signal during a burst operation and maintaining a low level when not in a burst operation. The method of claim 10, Burst decoder control unit, Combining means for NAND combining the burst signal and the clock pulse signal; And inverter means for inverting a phase of the NAND combined signal by the combining means and outputting the third control selection signal. The method of claim 1, The decoding unit, Combining means for outputting a decoded signal decoded from said second command signals and an inverted decoded signal inverted phase of said decoded signal; Amplifying means operated by any one of said control selection signals, for amplifying a potential difference between said decoded signal and said inverted decoded signal; And And output means for inverting and delaying the signal output from the amplifying means and outputting the signal as the output signal. A decoder which decodes first command signals input from the outside and outputs a first signal and a second signal inverted in phase with the first signal; When the clock pulse signal generating the high level pulse every predetermined period is high level, the clock signal is synchronized with any one of the pulse signal and the clock pulse signal synchronized with the second command signals inputted from the outside. A control unit for outputting control selection signals for controlling respective command decoders by signals used; An amplifying unit operating by any one of the first to third control selection signals to comparatively amplify the potential difference between the first and second signals; And And an output unit for inverting and delaying the signal output from the amplifying unit to output an output signal. The method of claim 19, And the first command signals include at least one of a row address strobe signal, a column address strobe signal, a chip select signal, and a write enable signal. The method of claim 19, And the second command signals include at least a row address strobe signal and a column address strobe signal. The method of claim 19, The control unit, A pulse signal generator for synchronizing with the clock pulse signal when the second command signals are enabled and outputting the pulse signal disabled when the second command signals are disabled; And a control selection signal generator which is synchronized with any one of the clock pulse signal and the pulse signal and outputs the control selection signals according to signals used to operate the semiconductor memory device. Instruction decoding circuitry. The method of claim 22, The pulse signal generator, First combining means for logically combining the first command signals; First switching means for selecting and outputting any one of a signal having a ground level and a signal having a power supply level according to the state of the signal combined in the combining means; First latch means for latching a signal output from the first switching means; Second latch means for latching a signal latched in said first latching means by said clock pulse signal; Inverting / delaying means for inverting the latched signal by the second latching means and outputting it as a signal for controlling the first switching means; And And second combining means for combining the clock pulse signal and the signal latched by the first latching means. The method of claim 23, The first combining means, A noah gate for quinoa combining the first command signals; And an inverter for inverting the phase of the quinoa combined signal at the noah gate. The method of claim 23, The first switching means, An NMOS transistor for outputting a signal at ground level by the signal combined in the first combining means; A first PMOS transistor for outputting a signal of a power supply level by a signal delayed by the inversion / delay means; And And a second PMOS transistor for switching the connection of the first PMOS transistor and the NMOS transistor by a signal combined by the first combining means. The method of claim 23, The second latch means, A first pass gate for transferring the latched signal in the first latching means when the clock pulse signal generates a pulse; A first latch for latching a signal transmitted from the first pass gate; A second pass gate that transfers the latched signal in the second latch when the clock pulse signal is in a disabled state; And And a second latch for latching a signal transmitted from the second pass gate. The method of claim 23, The second combining means, A NAND gate NAND combining the signal latched by the first latch means and the clock pulse signal; And an inverter for inverting the phase of the NAND combined signal in the NAND gate. The method of claim 23, The pulse signal generator is configured to increase the potential of the output node of the first switching means to a high level by an inverter means receiving a power-up signal for initializing an internal element of the semiconductor memory device and a signal output from the inverter means. And a second switching means. The method of claim 22, The control selection signal generator, Read according to DDR mode and SDR mode by the Cast Light Bar signal that maintains high level for one clock when requesting write command in DDR mode and the dial signal that maintains high level during DDR mode and low level during SDR mode. And a mode selection decoder controller for outputting a first control selection signal for controlling command decoders involved in the write operation. An input data decoder control section for outputting a second control selection signal for controlling command decoders for processing data input by the write read bar signal maintaining a high level during a read operation and a low level during a write operation; And And a burst decoder controller configured to output a third control selection signal for controlling the command decoders related to the burst operation by a burst signal that maintains a high level during the burst operation. The method of claim 29, The mode selection decoder control unit outputs a first control selection signal corresponding to the pulse signal in the SDR mode, and in the DDR mode, the first control synchronized with the clock pulse signal when the phase is inverted in the cast light bar signal. And a command decoding circuit for outputting a selection signal. The method of claim 29, The mode selection control unit, First inverter means for inverting the phase of the cast light bar signal; Combining means for NAND combining the signal inverted in the inverter means and the clock pulse signal; Second inverter means for inverting the phase of the pulse signal; Transmission means for selecting and transmitting any one of a signal inverted by the second inverter means and a NAND combined signal by the combining means according to the state of the dial signal; And And third inverter means for inverting a phase of the signal transmitted from the transfer means and outputting the first control selection signal. The method of claim 31, wherein The delivery means, A first pass gate for transferring a NAND combined signal in the combining means when the dial signal is at a high level; And a second pass gate which transfers the inverted signal by the second inverter means when the digital signal is at a low level. The method of claim 29, And the input data decoder controller outputs the second control select signal synchronized with the clock pulse signal during a read operation and maintained at a low level during a write operation. The method of claim 29, The input data decoder control unit, Combining means for NAND combining the write lead bar signal and the clock pulse signal; And inverter means for inverting the phase of the NAND combined signal by the combining means and outputting the second control selection signal as the second control selection signal. The method of claim 29, And a burst decoder controller outputs said third control selection signal synchronized with said clock pulse signal during a burst operation and maintaining a low level when not in a burst operation. The method of claim 29, Burst decoder control unit, Combining means for NAND combining the burst signal and the clock pulse signal; And inverter means for inverting a phase of the NAND combined signal by the combining means and outputting the third control selection signal.

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