KR100940273B1 - Circuit of controlling buffer - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit of a semiconductor memory device, and in response to a write latency signal, generates a control signal by delaying the write command by a predetermined period and controls a generation time of the control signal, and responds to the control signal. The present invention provides a buffer control circuit including a buffer enable signal generator for generating a buffer enable signal for enabling the write buffer.

Write latency, buffer, delay, mode register, clock

Description

Buffer control circuit {CIRCUIT OF CONTROLLING BUFFER}

The present invention relates to a semiconductor memory device, and more particularly, to a buffer control circuit capable of controlling an enable timing of a write buffer.

In recent years, semiconductor memory devices have been continuously integrated with high speed and high speed according to the development of technology, and are used in various products ranging from large home appliances to small mobile products.

However, as the semiconductor memory device is gradually accelerated and the clock cycle for the internal operation is also shortened, a method of enabling the write buffer to receive write data by enabling the write buffer one clock faster than the preset write latency is given. Here, the write latency refers to the time from when the external write command is input until the write data is actually input.

1 is a diagram illustrating a control signal generator for generating a control signal for controlling an operation timing of a write buffer according to the prior art.

In response to the clock CLKB, the control signal generator receives a write command WT1 and generates a latch unit 310 for generating signals of the nodes n1 and n5, and the write latency signal WL <1: 2>), the signal transmission unit 320 selectively turns on and receives a signal of the node n1 or a signal of the node n5 and outputs the signal as a control signal CTL1. In addition, the control signal generator includes an NMOS transistor N300 for disabling the control signal CTL1 to a low level by fixing the node n2 to a high level in response to the power-up signal PWRUP. Here, the signal of the node n1 is an inverted signal of the write command WT1, and the signal of the node n5 is a signal from which the write command WT1 is delayed by one clock CLKB.

The signal transmitter 320 receives the first transfer gate T300 receiving the signal of the node n1 in response to the first write latency signal WL <1>, and the second write latency signal WL <2>. In response to the second transfer gate T301 receiving the signal of the node n5 and the inverter IV308 which generates the control signal CTL1 by inverting the signal of the node n1 or the signal of the node n5, It is configured to include.

The latch unit 310 sequentially delays and writes the write command WL1 in response to the clock CLKB, and alternately turns on the third transfer gate T302 and the fourth transfer gate in response to the clock CLKB. The gate T303 includes a first latch 311 and a second latch 312.

The operation of the control signal generator configured as described above will be described with reference to FIG. 2.

Here, the write command WT1 is an active high signal having a pulse width by one period of the clock CLKB, and the control signal CTL1 is also an active high signal. The second write latency signal WL <2> having a write latency of two is set in advance.

When the second transfer gate T301 is turned on in response to the second write latency signal WL <2>, the signal of the node n5 is inverted by the inverter IV308 to be generated as the control signal CTL1. . In this state, the voltage level change of the control signal CTL1 according to the voltage level change of the clock CLKB and the write command WT1 is as follows.

When the clock CLKB is input at the high level and the write command WT1 is input at the low level, the node n1 becomes high level, and the third transfer gate T302 is turned on so that the node n2 also turns on. It becomes a high level. In addition, the signal of the node n2 is latched by the first latch portion 311, and the node n3 becomes low level. On the other hand, since the fourth transfer gate T303 is turned off, the node n4 and the node n5 maintain the previous voltage level. At this time, the control signal CTL1 is at a low level.

When the clock CLKB transitions to the low level and the write command WT1 transitions to the high level, the node n1 is turned low by the inverter IV300, and the third transfer gate T302 is turned off. Since it is a state, the node n2 and the node n3 maintain the high level and the low level, respectively, as latched by the first latch portion 311. In addition, since the fourth transfer gate T303 is turned on, the node n4 becomes low and the node n5 becomes high and latched in the second latch unit 312. At this time, the control signal CTL1 maintains a low level.

When the clock CLKB transitions to the high level again while the write command WT1 maintains the high level, the node n1 is turned low by the inverter IV300, and the third transfer gate T302 is turned on. Since it is on, node n2 transitions to a low level, and node n3 becomes a high level. In addition, since the fourth transfer gate T303 is turned off again, the nodes n4 and n5 maintain low and high levels as latched by the second latch unit 312. At this time, the control signal CTL1 maintains a low level.

When the clock CLKB transitions to the low level and the write command WT1 transitions to the low level, the node n1 transitions to the high level, and the third transfer gate T302 is turned off, so that the node n2 ) And the node n3 maintain the low level and the high level, respectively, as latched by the first latch portion 311. On the other hand, since the fourth transfer gate T312 is turned on, the node n4 and the node n5 transition to the high level and the low level, respectively. At this time, the control signal CTL1 transitions to the high level as the voltage level of the node n5 transitions to the low level.

As such, the control signal CTL1 is enabled at a high level by being delayed by one period of the clock CLKB than the write command WT1. The buffer enable signal DBEN1 is enabled at a low level in response to the high level control signal CTL1. Here, the buffer enable signal DBEN1 is an active low signal. Therefore, the write buffer is delayed by one period of the clock CLKB than the write command WT1 and is enabled in response to the buffer enable signal DBEN1.

As described above, when the second write latency signal WL <2> is input, the control signal generator generates a control signal CTL1 that is enabled by delaying the write command WT1 by one period of the clock CLKB. Therefore, as a result, the write buffer is enabled as soon as one cycle of the clock CLKB at the write latency 2 to receive the write data.

However, as the operation speed of the semiconductor memory device continues to improve, the clock cycle for internal operation also becomes shorter, and the write buffer is enabled when the write buffer is enabled by delaying by one cycle of the clock CLKB at the write latency 2. Before the first write data is input, there is a problem that the write data is lost. In addition, in order to solve this problem, when the write buffer is enabled faster by one cycle of the clock CLKB, read data may flow into the write buffer.

Accordingly, the present invention controls the enable time of the write buffer by one-half cycle of the clock, such that read data flows into the write buffer or write data before the write buffer is enabled, as in the conventional write buffer controlled by one cycle of the clock. Discloses a buffer control circuit that can improve the problem of first inputting.

To this end, the present invention generates a control signal by delaying the write command by a predetermined interval in response to the write latency signal, but controls a generation time of the control signal, and enables the write buffer in response to the control signal. Provided is a buffer control circuit including a buffer enable signal generation unit for generating a buffer enable signal.

In the present invention, the control signal is preferably generated by a delay of 1/2 of the clock than the write command.

In the present invention, it is preferable to further include a mode register for outputting the write latency signal to the control signal generator in response to an external address signal and the read-write mode signal.

In the present invention, the control signal generation unit is a latch unit for delaying and latching the write command in response to the clock, and in response to the write latency signal, delays 1/2 of the clock from the latch unit from the write command in response to the write latency signal. And a signal transfer unit for receiving and transmitting the latched signal, and a logic unit generating a control signal in response to the latched signal.

In an embodiment, the latch unit includes: a first transfer device turned on in response to the clock; a first latch configured to receive and write the write command through the first transfer device to generate a first latch signal; And a second latch that is turned on in response to a clock, and a second latch that latches the first latch signal through the second transfer device to generate a second latch signal.

In the present invention, it is preferable that the first transfer element and the second transfer element are alternately turned on in response to the clock.

In the present invention, the signal transfer unit is configured to include a third transfer element for receiving and transmitting the first latch signal, and a fourth transfer element for receiving and transferring the second latch signal.

In the present invention, the logic unit preferably generates a control signal that is enabled in response to the first enable signal of the first latch signal and the second latch signal.

In an embodiment of the present invention, the buffer enable signal generation unit may buffer the control signal, a third latch for latching an output signal of the buffer unit, and an output signal of the third latch to invert the buffer enable signal. It is configured to include an inverter to generate.

In addition, the present invention provides a latch unit for sequentially delaying and latching a write command in response to a clock, a signal transfer unit receiving a first latch signal and a second latch signal from the latch unit in response to a write latency signal; It provides a buffer control circuit comprising a logic unit for generating the control signal in response to the first latch signal or the second latch signal.

In the present invention, it is preferable that the second latch signal is a signal which is delayed by a half cycle of a clock more than the first latch signal.

In the present invention, the first latch signal is preferably a signal that is delayed and latched by a period of 1/2 of the clock than the write command.

In the present invention, the second latch signal is preferably a signal that is delayed by one cycle of the clock than the write command and latched.

In an embodiment, the latch unit includes: a first transfer device turned on in response to the clock; a first latch configured to receive and write the write command through the first transfer device to generate a first latch signal; And a second latch that is turned on in response to a clock, and a second latch configured to receive and latch the first latch signal through the second transfer device to generate a second latch signal.

In the present invention, it is preferable that the first transfer element and the second transfer element are alternately turned on in response to the clock.

In the present invention, the signal transfer unit is configured to include a third transfer element for receiving and transmitting the first latch signal, and a fourth transfer element for receiving and transferring the second latch signal.

In the present invention, the logic unit preferably generates a control signal that is enabled in response to the first enable signal of the first latch signal and the second latch signal.

In the present invention, it is preferable that the second latch signal is enabled by delaying the clock by a half cycle longer than the first latch signal.

In the present invention, the buffer enable signal generation unit is a buffer for buffering the control signal, a latch unit for latching the output signal of the buffer unit, and an inverter for inverting the output signal of the latch unit to generate the buffer enable signal It is configured to include.

Hereinafter, the present invention will be described in more detail with reference to Examples. These examples are only for illustrating the present invention, and the scope of protection of the present invention is not limited by these examples.

3 is a diagram illustrating a buffer control circuit of a semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 3, the buffer control circuit includes a command decoder 1, a mode register 2, a control signal generator 3, and a buffer enable signal generator 4. As shown in FIG.

The command decoder 1 receives an external command signal CMD and generates a write command WT10 for a write operation and a read-write mode signal MRW for controlling the mode register 2.

The mode register 2 outputs a predetermined write latency signal WL <1: N> in response to the external address signals Adr <0: K> and the read-write mode signal MRW.

As illustrated in FIG. 4, the control signal generator 3 includes a latch unit 30 which sequentially delays and latches the write command WT10 in response to the clock CLKB, and the write latency signal WL <2. In response to &quot;), the signal from the latch unit 30 receives the signals of the nodes n13 and n15 and the signal from the node n13 transmitted through the signal transfer unit 31. Or a logic unit 32 for generating a control signal CTL10 in response to the signal of the node n15. Here, it is assumed that the second light latency signal WL <2> for setting the light latency 2 is preset.

The latch unit 30 may include the fifth transfer gate T34 and the sixth transfer gate T35, which are alternately turned on in response to the clock CLKB, and the first latch 301 and the second latch 302. It is configured to include.

The signal transfer unit 31 is turned on in response to the first write latency signal WL <1> to receive the ground voltage VSS and the signal of the node n11, respectively. The second transfer gate T31 and the third transfer gate T32 that are turned on in response to the second write latency signal WL <2> to receive the signal of the node n13 and the signal of the node n15, respectively. And a fourth transfer gate T33.

The logic unit 32 includes a noble gate NR30 and an inverter IV39. When the second write latency signal WL <2> is preset, the logic unit 32 turns in response to the second write latency signal WL <2>. The control signal CTL10 is generated by performing an OR operation on the signal of the node n13 and the signal of the node n15 respectively transmitted through the third transfer gate T32 and the fourth transfer gate T33 that are turned on. That is, if one of the signal of the node n13 and the signal of the node n15 is first enabled to the high level, the logic unit 32 generates a control signal CTL10 that is enabled to the high level in response thereto. .

Meanwhile, the control signal generator 3 fixes the node n12 to a high level in response to the power-up signal PWRUP, thereby disabling the control signal CTL10 generated by the logic unit 32 to a low level. It further comprises a PMOS transistor (P30). Here, the control signal CTL10 is an active high signal in which the high level is enabled. In other words, the PMOS transistor P30 is an initialization element of the control signal generator 3.

As shown in FIG. 5, the buffer enable signal generation unit 4 includes a buffer unit 40 for buffering the control signal CTL10 and a third latch 41 for latching the output signal of the buffer unit 40. And an inverter IV42 for inverting the output signal of the third latch 41 to generate the buffer enable signal DBEN10. In addition, the buffer enable signal generation unit 4 further includes a PMOS transistor P41 for initializing the buffer enable signal DBEN10 to a high level in response to the power-up signal PWRUP. Here, the buffer enable signal DBEN10 is an active low signal.

The operation of the buffer control circuit configured as described above will be described with reference to FIG.

First, as described above, it is assumed that the write latency 2 is preset and the second write latency signal WL <2> is input.

Through the third transfer gate T32 and the fourth transfer gate T33 which are turned on in response to the second write latency signal WL <2>, the signal of the node n13 and the inverted signal of the node n15 are It is passed to the logic unit 32. In this state, the voltage level change of the control signal CTL1 according to the voltage level change of the clock CLKB and the write command WT1 is as follows.

When the clock CLKB is at a high level and is at a low level before the write command WT10 is still input, the fifth transfer gate T34 is turned on and the sixth transfer gate T35 is turned off. Node n11 and node n12 become high level, node n13 becomes low level, and node n14 and node n15 maintain the previous voltage level. At this time, since the node n13 and the node n15 are both at the low level, the control signal CTL10 is at the low level.

When the clock CLKB transitions to the low level and the write command WT10 is input to the high level, the fifth transfer gate T34 is turned off and the sixth transfer gate T35 is turned on, so that the node n11 transitions to a low level, while node n12 and n13 maintain a high level and a low level, respectively, and node n14 and node n15 maintain a low level and a high level, respectively. . At this time, since the node n13 and the node n15 are both at the low level, the control signal CTL10 also maintains the low level.

When the clock CLKB transitions to the high level and the write command WT10 maintains the high level, the fifth transfer gate T34 is turned on and the sixth transfer gate T35 is turned off, so that the node n11 maintains a low level, and node n12 transitions to a low level. In addition, node n13 transitions to a high level, while node n14 and node n15 maintain a low level and a high level, respectively, by a second latch 302. At this time, since the signal of the node n13 of the signal of the node n13 and the signal of the node n15 transitions to a high level, the logic unit 32 supplies the control signal CTL10 in response to the signal of the node n13. Enable to high level. That is, the control signal CTL10 is enabled by a delay of 1/2 of the clock CLKB than the write command WT10, and the buffer enable signal generator 4 is low in response to the control signal CTL10. A buffer enable signal DBEN10 that is enabled at a level is generated. Therefore, the time at which the buffer enable signal DBEN10 is generated is faster by 3/2 periods of the clock CLKB than the preset write latency 2. FIG.

As described above, the buffer control circuit according to the present invention has a clock CLKB than the write command WT10 in addition to the signal of the node n15 which is delayed by one period of the clock CLKB than the write command WT10 compared to the conventional art. The control signal CTL10 is generated by receiving the signal of the node n13 which is delayed by 1/2 cycle of In addition, the control signal CTL10 that is enabled in response to a signal that is enabled first among the signal of the node n13 and the signal of the node n15 is generated. That is, the write buffer can be enabled 1/2 cycle earlier than the clock CLKB. Therefore, compared to the related art, by reducing the adjustment period of the enable time of the write buffer, it is possible to improve the problem of inflow of read data that may occur when the enable time of the write buffer is advanced by one cycle of the clock CLKB.

In the embodiment of the present invention, the write latency is delayed by 1/2 of the clock CLKB rather than the write command WT10 in the write latency 2 to enable the write buffer. However, the present invention provides a clock CLKB. It is not limited only to the half cycle of). That is, those skilled in the art, although not shown in FIG. 4, write commands generated at each node between a plurality of transfer gates (not shown) sequentially connected to the fifth transfer gate T302 and the sixth transfer gate T303. By using the delay signals of WT10, the write buffer may be enabled by delaying 1 / M of the clock CLKB from the write command WT10 at any write latency N. FIG.

1 is a diagram illustrating a control signal generator for generating a control signal for controlling an operation timing of a write buffer according to the prior art.

FIG. 2 is a timing diagram of signals for explaining the operation of FIG. 1.

3 is a diagram illustrating a buffer control circuit of a semiconductor memory device according to an embodiment of the present invention.

4 is a diagram illustrating the control signal generator of FIG. 3.

FIG. 5 is a diagram illustrating a buffer enable signal generator of FIG. 3.

FIG. 6 is a timing diagram of signals for explaining the operation of FIG. 3.

<Description of the symbols for the main parts of the drawings>

1: command decoder 2: mode register

3: delay unit 4: buffer enable signal generator

CMD: command signal Adr <0: K>: address signal

WT10: write command WL <1: N>: write latency signal

CTL10: Control signal DBEN10: Buffer enable signal

Claims (20)

A control signal generator configured to generate a control signal by delaying the write command by a predetermined period in response to the write latency signal, and controlling a generation time of the control signal; And And a buffer enable signal generator configured to generate a buffer enable signal for enabling a write buffer in response to the control signal. The buffer control circuit of claim 1, wherein the control signal is generated by a half cycle of a clock delay from the write command. The buffer control circuit of claim 1, further comprising a command decoder configured to receive an external command signal and generate the write command and the read-write mode signal. The buffer control circuit of claim 1, further comprising a mode register configured to output the write latency signal to the control signal generator in response to an external address signal and a read-write mode signal. The method of claim 1, wherein the control signal generator A latch unit configured to delay and latch the write command in response to a clock; A signal transfer unit configured to receive and transmit a latched signal from the latch unit in response to the write latency signal by being delayed by 1/2 of the clock from the latch command; And And a logic unit generating a control signal in response to the latched signal. The method of claim 5, wherein the latch unit A first transfer element turned on in response to the clock; A first latch receiving the write command through the first transfer device to latch the write command to generate a first latch signal; A second transfer element turned on in response to the clock; And And a second latch configured to generate a second latch signal by latching the first latch signal through the second transfer device. 7. The buffer control circuit of claim 6, wherein the first transfer element and the second transfer element are alternately turned on in response to the clock. The method of claim 6, wherein the signal transmission unit A third transfer device configured to receive and transfer the first latch signal; And And a fourth transfer device configured to receive and transfer the second latch signal. The buffer control circuit of claim 8, wherein the logic unit generates a control signal that is enabled in response to a signal that is first enabled among the first latch signal and the second latch signal. The method of claim 1, wherein the buffer enable signal generation unit A buffer unit for buffering the control signal; A third latch for latching an output signal of the buffer unit; And And an inverter configured to invert the output signal of the third latch to generate the buffer enable signal. A latch unit for sequentially delaying and latching a write command in response to a clock; A signal transfer unit receiving a first latch signal and a second latch signal from the latch unit in response to a write latency signal; And And a logic unit generating a control signal in response to the first latch signal or the second latch signal. 12. The buffer control circuit of claim 11, wherein the second latch signal is a signal which is delayed by a half cycle of a clock more than the first latch signal. The buffer control circuit of claim 12, wherein the first latch signal is a signal that is delayed and latched by a half cycle of a clock than the write command. The buffer control circuit of claim 12, wherein the second latch signal is a signal that is latched by a delay of one clock than the write command. The method of claim 11, wherein the latch unit A first transfer element turned on in response to the clock; A first latch receiving the write command through the first transfer device to latch the write command to generate a first latch signal; A second transfer element turned on in response to the clock; And And a second latch configured to receive and latch the first latch signal through the second transfer device to generate a second latch signal. 16. The buffer control circuit of claim 15, wherein the first transfer element and the second transfer element are alternately turned on in response to the clock. The method of claim 11, wherein the signal transmission unit A third transfer device configured to receive and transfer the first latch signal; And And a fourth transfer device configured to receive and transfer the second latch signal. The buffer control circuit of claim 11, wherein the logic unit generates a control signal that is enabled in response to a signal that is first enabled among the first latch signal and the second latch signal. 19. The buffer control circuit of claim 18, wherein the second latch signal is enabled by delaying a clock by a half cycle longer than the first latch signal. The method of claim 11, wherein the buffer enable signal generation unit A buffer unit for buffering the control signal; A latch unit for latching an output signal of the buffer unit; And And an inverter configured to invert the output signal of the latch unit to generate the buffer enable signal.

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