KR20080043561A - Semiconductor memory apparatus - Google Patents

Abstract

A semiconductor memory apparatus is provided to improve data output operation speed by reducing timing interval in case of continuous data output by latching plural data outputted at the same time and then transferring the continuous data to a global input/output line sequentially. A plurality of local input/output line pairs(LIO,/LIO) receive plural data from one memory block. A plurality of global output drivers(40) drive the data transmitted from the plurality of local input/output line pairs. A conversion control part(50) generates a conversion control signal from commands for data output operation. A serial conversion part(60) transmits the plural data transmitted from the plurality of global output drivers to a global input/output line according to the control of the conversion control signal and a plurality of column selection signals.

Description

Semiconductor Memory Apparatus

1 is a block diagram illustrating a data output operation of a semiconductor memory device according to the prior art;

2 is a timing diagram for explaining a data output operation of a semiconductor memory device according to the related art;

3 is a block diagram illustrating a data output operation of a semiconductor memory device according to the present invention;

4 is a configuration diagram of the conversion control unit shown in FIG. 3;

5 is a configuration diagram of a serial converter shown in FIG. 3;

6 is a timing diagram illustrating a data output operation of the semiconductor memory device according to the present invention.

<Description of the symbols for the main parts of the drawings>

10: memory cell block 20: sense amplifier unit

30: column selector 40: global output driver

50: conversion control unit 60: serial conversion unit

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having improved data output speed.

In general, a semiconductor memory device selects a word line designated by a row address to activate a corresponding memory cell. The column selection signal specified from the column address is activated to perform data input / output operations to the corresponding memory cell. In a data output operation of a semiconductor memory device, a memory cell block including a plurality of memory cells transfers data to sense amplifier input / output line pairs SIO and / SIO through pairs of bit lines connected to each memory cell. After that, the data of the sense amplifier input / output line pairs (SIO, / SIO) is transferred to the global input / output driver through the local input / output line pairs (LIO, / LIO) and driven, and then transmitted to the data output buffer through the global input / output line (GIO). do.

Hereinafter, a semiconductor memory device according to the related art will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a data output operation of a semiconductor memory device according to the related art, and it is assumed that each memory block 10 includes four memory cells.

As illustrated, the semiconductor memory device according to the related art includes a memory cell block 10, four bit line pairs BL and / BL, a sense amplifier unit 20, four sense amplifier input / output line pairs SIO, / SIO) and the corresponding bit line pair (BL, / BL) and the corresponding sense amplifier input / output line pairs (SIO, / SIO) depending on whether column selection signals 1 to 4 (YS <1: 4>) are enabled. Four column selector 30, and transfer from the local input and output line pairs (LIO, / LIO) and the local input and output line pairs (LIO, / LIO) connected to the four sense amplifier input and output line pairs (SIO, / SIO) And a global output driver 40 for driving the data to be transmitted to the global input / output line GIO.

In the data output operation of the semiconductor memory device configured as described above, when the row address selects the corresponding memory block 10 to enable the word line, the sense amplifiers of the sense amplifier unit 20 connected to the memory block 10 The bit line sensing operation is performed, and the data amplified and output from each memory cell are carried in each bit line pair BL and / BL. Thereafter, when the column select signal YS <i> enabled by the column address among the column select signals 1 to 4 (YS <1: 4>) activates any one of the four column select units 30. The data of the bit line pairs BL and / BL is transferred to the corresponding sense amplifier input / output line pairs SIO and / SIO, and then to the local input / output line pairs LIO and / LIO. The global input / output driver 40 drives data transferred from the local input / output line pairs LIO and / LIO and transmits the data to the global input / output line GIO.

The semiconductor memory device includes a large number of memory blocks 10 and peripheral devices thereof. 1 shows only one of them for convenience of description. In the data output operation of the semiconductor memory device, data is output one by one from the plurality of memory blocks 10 according to a predetermined burst length and transferred to a data output buffer through the global input / output line GIO. For example, when the burst length is 4, data is output one by one from four memory blocks 10 and four data are transferred to the data output buffer through the global input / output line GIO.

FIG. 2 is a timing diagram illustrating a data output operation of a semiconductor memory device according to the related art, and illustrates a semiconductor memory device in which the cascade latency CL is set to 3 and the burst length BL is set to 4. FIG. In addition, the time from the input of the active command ACT to the input of the read command RD (hereinafter, tRCD) is 3, and the time from the input of the precharge command PCG to the re-input of the active command ACT (tRP). ) Is assumed to be 3.

In the drawing, output timings of data D0 to D7 output to a clock clk, an active ACT for data output, a read RD, a precharge PCG command, and a global input / output line GIO are illustrated. .

When the active command ACT is input at an arbitrary time point, the read command RD is input after three cycles of the clock clk. Since the burst length BL is 4, the precharge command PCG is input with a timing difference equal to 4 cycles of the read command RD and the clock clk, and then an active command for a second data output operation. ACT is input after three cycles of the clock clk from the input of the precharge command PCG. Since the CAS latency CL is 3, the four data D0 to D3 of the global input / output line GIO start to be transferred from four memory blocks after three cycles of the clock clk at the input point of the read command RD. do.

When the active command ACT is input again and the read command RD and the precharge command PCG are sequentially input at the timing set as described above, an output operation for the four new data D4 to D7 is performed. Is performed. In general, the four memory blocks that output data at this time are different from the four memory blocks that output the first data.

The output timings of the first four data D0 to D3 and the later four data D4 to D7 differ by 6 cycles based on the clock clk by tRCD and the cascade latency CL. As such, in the related art, data is output one by one from a memory block of a plurality of memory blocks, and data is output by combining the data one by one. In view of the increasing trend of semiconductor memory devices, it is an important technical task to reduce such timing intervals.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and includes a plurality of local input / output lines per memory block, and sequentially latches a plurality of data outputs simultaneously and sequentially transmits the data to a global input / output line. There is a technical problem to provide a semiconductor memory device that improves the data output operation speed by reducing the timing interval during data output.

In accordance with an aspect of the present invention, a semiconductor memory device includes: a plurality of local input / output line pairs that simultaneously receive a plurality of data from one memory block; A plurality of global output drivers respectively driving data transmitted from the plurality of local input / output line pairs; A conversion controller for generating a conversion control signal from commands for a data output operation; And a serial converter configured to transfer a plurality of data transmitted from the plurality of global output drivers to a global input / output line according to the control of the conversion control signal and the plurality of column selection signals.

In addition, according to another embodiment of the present invention, a semiconductor memory device may include: a plurality of local input / output lines that simultaneously receive a plurality of data from one memory block; A conversion control unit which receives a command for a data output operation and generates a conversion control signal which is enabled by one cycle of the clock faster than the fastest column selection signal; And serially receiving a plurality of data of the plurality of local input / output lines simultaneously when the conversion control signal is enabled, and sequentially transferring the plurality of data to a global input / output line as the plurality of column selection signals are sequentially enabled. And a conversion unit.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 is a block diagram illustrating a data output operation of a semiconductor memory device according to an exemplary embodiment of the present invention. It is assumed that each memory block 10 includes four memory cells.

As illustrated, the semiconductor memory device according to the present invention includes a memory cell block 10, four bit line pairs BL and / BL, a sense amplifier unit 20, four sense amplifier input / output line pairs SIO, SIO), four local input / output line pairs (LIO, / LIO) connected to the four sense amplifier input / output line pairs (SIO, / SIO), and four local input / output line pairs (LIO, / LIO) transmitted from the Conversion control signal cvt from four global output drivers 40, read command RD, precharge command PCG, column access strobe signal CAS, and bank active signal BA, which respectively drive four data. The four data transmitted from the global output driver 40 under the control of the conversion control unit 50 and the conversion control signal cvt and column selection signals 1 to 4 (YS <1: 4>) It includes a serial converter 60 for transmitting to the input / output line (GIO).

In the data output operation of the semiconductor memory device configured as described above, when the row address selects the corresponding memory block 10 to enable the word line, the sense amplifiers of the sense amplifier unit 20 connected to the memory block 10 The bit line sensing operation is performed, and the data amplified and output from each memory cell are carried in each bit line pair BL and / BL. Thereafter, the data of each of the four bit line pairs BL and / BL is transferred to four sense amplifier input / output line pairs SIO and / SIO, respectively, and the four local input / output line pairs LIO and / LIO). The four global input / output drivers 40 drive four data transmitted from the four local input / output line pairs LIO and / LIO, respectively.

The conversion control unit 50 converts the commands for data output operation from the read command RD, the precharge command PCG, the column access strobe signal CAS, and the bank active signal BA. Generate a control signal cvt. In this case, the conversion control signal cvt may be faster than the column selection signal (eg, column selection signal 1 (YS <1>)) which is enabled among the column selection signals 1 to 4 (YS <1: 4>). The serial converter 60 receives four data simultaneously from the four global I / O drivers 40 when the conversion control signal cvt is enabled. As the column selection signals 1 to 4 (YS <1: 4>) are sequentially enabled, four input data are sequentially output to the global input / output line GIO.

4 is a configuration diagram of the conversion control unit illustrated in FIG. 3.

The conversion controller 50 controls to generate a control enable signal cten from the read command RD, the precharge command PCG, the column access strobe signal CAS, and the bank active signal BA. An enable signal generator 510 and a conversion control signal generator 520 for generating the conversion control signal cvt by receiving the control enable signal cten are included.

In this case, the control enable signal generator 510 receives the read command RD at a gate terminal, an external supply power VDD is applied to a source terminal, and a drain terminal is connected to the first node N1. The first transistor TR1 receives the precharge command PCG at the gate terminal, the external supply power VDD is applied at the source terminal, and the second transistor TR2 having the drain terminal connected to the first node N1. ), A third transistor TR3 and a gate terminal having the column access strobe signal CAS input to a gate terminal, a source terminal connected to the first node N1, and a drain terminal connected to a second node N2. A fourth transistor TR4 having the column access strobe signal CAS input thereto and a drain terminal thereof connected to the second node N2, and the bank active signal BA being inputted to a gate terminal thereof, and a drain terminal thereof being the Connected to Source of Four Transistors TR4 And a fifth inverter TR5 having a source terminal grounded, a first inverter IV1 receiving a signal formed at the second node N2, and a second inverter forming a latch structure with the first inverter IV1. (IV2).

The conversion control signal generator 520 has a configuration of a general pulse generator including a delay unit DLY, a NAND gate ND, and a third inverter IV3.

Here, the read command RD and the precharge command PCG are a row enable signal, and the column access strobe signal CAS is a pulse signal having an enable time of a width shorter than a half period of a clock. to be.

In order to activate a memory bank including the memory block 10 shown in FIG. 3, the corresponding bank active signal BA must be enabled. The first node N1 is supplied with the external supply power supply VDD during the enable period of the read command RD to have a high level potential, and the column access strobe signal CAS The second node N2 also has a high level of potential during the disable period. Therefore, the control enable signal cten output through the first inverter IV1 is disabled at a low level.

Thereafter, when the column access strobe signal CAS is enabled, the second node N2 has a low level potential. Therefore, the control enable signal cten is enabled at a high level. Subsequently, even when the column access strobe signal CAS is disabled, the enable state of the control enable signal cten is maintained by the latch configuration of the first and second inverters IV1 and IV2. However, when the bank active signal BA is disabled and the precharge command PCG is enabled, the potential of the second node N2 is again disabled to a low level.

The conversion control signal generator 520 generates the conversion control signal cvt by controlling the pulse width and the enable time of the control enable signal cten. The conversion control signal cvt generated at this time is preferably the earliest enabled column selection signal among the column selection signals 1 to 4 (YS <1: 4>) (for example, the column selection signal 1 (YS). <1>) is enabled at a timing faster by one cycle of the clock.

FIG. 5 is a configuration diagram of the serial converter shown in FIG. 3.

As shown in the drawing, the serial converter 60 latches data D0 to D3 respectively transmitted from the four global output drivers 40 when the conversion control signal cvt is enabled and the column select signal. The first to fourth latch units 610 to 640 output the latched data when the corresponding column selection signal YS <i> among the 1 to 4 YS <1: 4> is enabled.

Here, the first latch unit 610 is a first switching element, the first switching element to pass the data (D0) transmitted from the global output driver 40 when the conversion control signal (cvt) is enabled And a second switching element for outputting data stored in the latch to the global input / output line GIO when the column select signal 1 YS <1> is enabled.

Through the drawings, the first switching element is implemented as a sixth transistor TR6, the latch is implemented as a fourth inverter IV4 and a fifth inverter IV5, and the second switching element is implemented as a seventh transistor TR7. It can be seen that.

Similarly, the second latch unit 620 includes an eighth transistor TR8, a sixth inverter IV6, a seventh inverter IV7, and a ninth transistor TR9, and the third latch unit 630 includes the eighth transistor TR6. And a tenth transistor TR10, an eighth inverter IV8, a ninth inverter IV9, and an eleventh transistor TR11, and the fourth latch unit 640 includes the twelfth transistor TR12 and the tenth inverter IV10. ), The eleventh inverter IV11, and the thirteenth transistor TR13 may be configured to have the same structure as the first latch unit 610.

With such a configuration, the conversion control signal cvt, the column select signal 1 (YS <1>), the column select signal 2 (YS <2>), the column select signal 3 (YS <3>), and the column select signal 4 ( YS <4> is sequentially enabled, so that the four data D0 to D3 simultaneously transmitted from the four global output drivers 40 are simultaneously stored in the serial converter 50 and then sequentially To the global input / output line (GIO).

FIG. 6 is a timing diagram illustrating a data output operation of a semiconductor memory device according to the present invention. As shown in the related art of FIG. 2, a cascade latency CL is 3, a burst length BL is 4, and an active circuit is illustrated. The time from the input of the command ACT to the input of the read command RD (hereinafter, tRCD) is 3, and the time from the input of the precharge command PCG to the re-input of the active command ACT is 3 It is assumed to be.

In the drawing, the output timing of the data D0 to D7 output to the clock clk, the active ACT, the read RD, the precharge PCG command, and the global input / output line GIO is illustrated.

The four data D0 to D3 of the global input / output line GIO are simultaneously output from any one memory block 10 and then latched in the serial converter 60 and sequentially output one by one. Therefore, the semiconductor memory device does not need to instruct the data output operation of any one memory block 10 after waiting until all four data D0 to D3 are output to the global input / output line GIO. This may be confirmed by shortening the timing interval between the read command RD and the precharge command PCG. That is, the active command ACT is input while the four data D0 to D3 are sequentially transferred from the serial converter 60 to the global input / output line GIO, and the global input / output line GIO is input. As soon as all four data D0 to D3 are transferred, new four data D4 to D7 are output from one memory block 10 to any one serial converter 60. do. Through the drawings, in the present invention, the output timing of the first output four data (D0 ~ D3) and later output four data (D4 ~ D7) is three cycles based on the clock (clk), which is a conventional Compared to the technology, it can be seen that the clock is three cycles faster.

Such an operation may be variously implemented according to the cascade latency CL and the burst length of the semiconductor memory device. However, the present invention may latch the data in the serial converter 60 and sequentially output the data to the global input / output line GIO. The technical gist of the present invention is widely applicable to a semiconductor memory device that is used in various ways. That is, the present invention is to provide a technique for significantly reducing the data output timing interval between each memory block, thereby improving the data output speed of the semiconductor memory device to improve the operation efficiency of the semiconductor memory device.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The semiconductor memory device of the present invention described above has a plurality of local input / output lines per memory block, and latches a plurality of data output simultaneously at the same time and sequentially transfers the data to a global input / output line to continuously output data. By reducing the timing interval, the data output operation speed is improved.

Claims (21)

A plurality of local input / output line pairs that simultaneously receive a plurality of data from one memory block; A plurality of global output drivers respectively driving data transmitted from the plurality of local input / output line pairs; A conversion controller for generating a conversion control signal from commands for a data output operation; And A serial conversion unit transferring a plurality of data transmitted from the plurality of global output drivers to a global input / output line according to the control of the conversion control signal and the plurality of column selection signals; A semiconductor memory device comprising a. The method of claim 1, The number of the local input and output line pairs is determined according to the burst length. The method of claim 1, And a command for a data output operation is a read command, a precharge command, a column access strobe signal, and a bank active signal. The method of claim 1, And the conversion control signal is enabled by one cycle of a clock faster than the fastest enabled signal of the plurality of column selection signals. The method of claim 3, wherein The conversion control unit, A control enable signal generator configured to generate a control enable signal from the read command, the precharge command, the column access strobe signal, and the bank active signal; And A conversion control signal generator for receiving the control enable signal and generating the conversion control signal; A semiconductor memory device comprising a. The method of claim 5, wherein The control enable signal generator, A first transistor receiving the read command at a gate terminal, an external supply power source applied to a source terminal, and a drain terminal connected to a first node; A second transistor receiving the precharge command at a gate terminal, the external supply power applied to a source terminal, and a drain terminal connected to the first node; A third transistor having a column access strobe signal input to a gate terminal, a source terminal connected to the first node, and a drain terminal connected to a second node; A fourth transistor having the column access strobe signal input to a gate end thereof and a drain end thereof connected to the second node; A fifth transistor in which the bank active signal is input to a gate terminal, a drain terminal is connected to a source terminal of the fourth transistor, and a source terminal is grounded; A first inverter receiving a signal formed at the second node; And A second inverter forming a latch structure with the first inverter; A semiconductor memory device comprising a. The method of claim 5, wherein And the conversion control signal generator is a pulse generator including a delay unit, a NAND gate, and an inverter. The method of claim 4, wherein The serial converter latches data transmitted from the plurality of global output drivers when the conversion control signal is enabled, and outputs latched data when the corresponding column selection signal of the plurality of column selection signals is enabled. A semiconductor memory device comprising a portion. The method of claim 8, Any one of the plurality of latch units, A first switching element configured to pass data transmitted from a corresponding global output driver when the conversion control signal is enabled; A latch for storing data passing through the first switching element; And A second switching element configured to output data stored in the latch unit to the global input / output line when the corresponding column select signal is enabled; A semiconductor memory device comprising a. The method of claim 8, And the number of the latch portions is determined according to the burst length. A plurality of local input / output lines that simultaneously receive a plurality of data from one memory block; A conversion control unit which receives a command for a data output operation and generates a conversion control signal which is enabled by one cycle of the clock faster than the fastest column selection signal; And When the conversion control signal is enabled, serial conversion is performed by simultaneously receiving a plurality of data of the plurality of local input / output lines and sequentially transmitting the plurality of data to a global input / output line as the plurality of column selection signals are sequentially enabled. part; Delay control device of the DLL circuit comprising a. The method of claim 11, The number of the local input and output line pairs is determined according to the burst length. The method of claim 11, And a command for a data output operation is a read command, a precharge command, a column access strobe signal, and a bank active signal. The method of claim 11, And the conversion control signal is enabled by one cycle of a clock faster than the fastest enabled signal of the plurality of column selection signals. The method of claim 13, The conversion control unit, A control enable signal generator configured to generate a control enable signal from the read command, the precharge command, the column access strobe signal, and the bank active signal; And A conversion control signal generator for receiving the control enable signal and generating the conversion control signal; A semiconductor memory device comprising a. The method of claim 15, The control enable signal generator, A first transistor receiving the read command at a gate terminal, an external supply power source applied to a source terminal, and a drain terminal connected to a first node; A second transistor receiving the precharge command at a gate terminal, the external supply power applied to a source terminal, and a drain terminal connected to the first node; A third transistor having a column access strobe signal input to a gate terminal, a source terminal connected to the first node, and a drain terminal connected to a second node; A fourth transistor having the column access strobe signal input to a gate end thereof and a drain end thereof connected to the second node; A fifth transistor configured to receive the bank active signal at a gate end thereof, a drain end thereof connected to a source end of the fourth transistor, and a source end of which is grounded; A first inverter receiving a signal formed at the second node; And A second inverter forming a latch structure with the first inverter; A semiconductor memory device comprising a. The method of claim 15, And the conversion control signal generator is a pulse generator including a delay unit, a NAND gate, and an inverter. The method of claim 14, The serial converter latches data transmitted from the plurality of global output drivers when the conversion control signal is enabled, and outputs latched data when the corresponding column selection signal of the plurality of column selection signals is enabled. A semiconductor memory device comprising a portion. The method of claim 18, Any one of the plurality of latch units, A first switching element configured to pass data transmitted from a corresponding global output driver when the conversion control signal is enabled; A latch for storing data passing through the first switching element; And A second switching element configured to output data stored in the latch unit to the global input / output line when the corresponding column select signal is enabled; A semiconductor memory device comprising a. The method of claim 18, And the number of the latch portions is determined according to the burst length. The method of claim 11, And a plurality of global input / output drivers for respectively driving data transmitted from the plurality of local input / output lines to the serial conversion means.

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