KR100728961B1 - circuit for improving current of level shifter - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current improving circuit of a level shifter, and more particularly, to a current improving circuit of a level shifter that senses a change in an internal voltage and adjusts a transistor size of a level shifter.

The present invention includes a pull-up transistor supplied with a pumping voltage (Vpp) and a pull-down transistor applied with a ground voltage (Vss), and is a current improvement circuit of a level shifter for changing and outputting a level of an internal voltage. A detection unit for comparing the reference voltage with the internal voltage by using a detection signal to output a change in the detected internal voltage as a detection signal; And a sizing transistor switched by a sensing signal applied to a gate, and having a drain and a source connected to the drain and the source of the pull-down transistor in common.

The present invention has an effect of preventing malfunction caused by current and delay flowing in the level shifter by adjusting the transistor size of the level shifter by sensing a change in the internal voltage.

Level Shifter, Multi-Bank, Cell Data Level Voltage, Ground Voltage, Pumping Voltage

Description

Circuit for improving current of level shifter {circuit for improving current of level shifter}

1 is a circuit diagram of a conventional level shifter,

FIG. 2 is a signal flowchart for describing an operation of the level shifter of FIG. 1;

3 is a circuit diagram illustrating current improvement of a level shifter in accordance with an embodiment of the present invention;

FIG. 4 is a signal flowchart for describing an operation of the current improving circuit of the level shifter of FIG. 3.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current improving circuit of a level shifter, and more particularly, to a current improving circuit of a level shifter that senses a change in an internal voltage and adjusts a transistor size of a level shifter.

In general, a level shifter refers to changing a level of an operating power source used in a memory circuit. A level shifter is a circuit for shifting a voltage level from a low level internal voltage to a high level voltage. The elevated output of the level shifter is used for bit line sense amplifiers, word lines, data output buffers, and the like.

1 is a circuit diagram of a conventional level shifter. As shown in FIG. 1, the conventional level shifter includes a first pMOS transistor P1 and a second pMOS transistor P2 having a pumping voltage Vpp supplied to a source and a drain and a gate cross-coupled to each other. ), A first nMOS transistor N1 and a drain connected to a drain of the first pMOS transistor P2, a cell data level voltage Vcore is applied to a gate, and an input signal connected to a source, and a drain of the second pMOS transistor P2. The second nMOS transistor N2 is connected to the drain of P2 and operates as an output terminal, an input signal is applied to the gate, and a ground voltage Vss is applied to the source. Here, the pumping voltage Vpp is a voltage obtained by boosting the power supply voltage Vdd to a predetermined level through the pumping circuit.

The operation of the conventional level shifter circuit will be described briefly. First, when the input signal is 'LOW', the second nMOS transistor N2 is turned off, and the output terminal outputs a voltage having a 'HIGH' level. .

Next, when the input signal transitions from 'LOW' to 'HIGH' state, the second nMOS transistor N2 is turned on and the output terminal outputs a 'LOW' level voltage. A current fighting phenomenon occurs between the 2 pMOS transistor P2 and the second nMOS transistor N2.

In other words, the second nMOS transistor N2 is turned on and the second pMOS transistor P2 is turned off by the input signal transitioned from the 'low' level to the 'high' level. Both the 2 nMOS transistor N2 and the second pMOS transistor P2 may be turned on to form a DC path between the pumping voltage Vpp and the ground voltage Vss.

At this time, the output of the level shifter becomes a current fighting state between the pMOS transistor P2 and the nMOS transistor N2 as to whether to go to a 'HIGH' state or a 'LOW' state.

Therefore, the current flowing through the second nMOS transistor N2 and the delay of the output are determined by the current fighting of the second pMOS transistor P2 and the second nMOS transistor N2.

On the other hand, the memory device performs many command modes required by the system. In particular, multi-bank command operation requires a lot of voltage and current, and thus needs to be optimized.

FIG. 2 is a flowchart illustrating an operation signal for describing a problem of the level shifter of FIG. 1. Referring to FIG. 2, the problem of the conventional level shifter in the multi-bank operation will be described.

When the bank 0 BA0 is selected and the write WT command is continuously received, the cell data level voltage Vcore is degraded so that the cell data level voltage Vcore is lower than the normal voltage.

The degraded cell data level voltage Vcore makes the current fighting between the pMOS transistor P2 and the nMOS transistor N2 of the level shifter worse when bank 1 BA1 is selected and the next command operation is performed. It can cause the level shifter to malfunction by increasing the time the current flows through the 2 nMOS transistor and the delay of the output voltage.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a current shifting circuit of a level shifter that senses a change in an internal voltage and adjusts a transistor size of a level shifter.

To this end, the present invention is to provide a current improving circuit of a level shifter including a sensing unit for detecting a change in an internal voltage and a sizing transistor turned on according to a signal of the sensing unit.

In order to achieve the above object, the present invention includes a pull-up transistor to which the pumping voltage (Vpp) is supplied, and a pull-down transistor to which the ground voltage (Vss) is applied. An improvement circuit comprising: a detector configured to output a change in an internal voltage detected by comparing a reference voltage and an internal voltage by an enable signal; And a sizing transistor switched by the sensing signal applied to a gate, and having a drain and a source connected to the drain and the source of the pull-down transistor in common.

Here, the internal voltage is a cell data level voltage Vcore, and the enable signal is a signal for activating one bank after one bank is activated and the cell data voltage is continuously used.

In addition, the sensing unit is supplied with a power supply voltage Vdd to a source, an enable signal is input to a gate, a first transistor p3 and a second transistor p6, and a power supply voltage Vdd is supplied to a source and the gate is supplied to the source. A fifth transistor p4 and a fourth transistor p5 connected to the drain of the second transistor, a fifth drain connected to the drain of the first transistor and the third transistor, and a reference voltage Vrefc applied to a gate thereof; An inverter INV1 connected to a transistor N4, a drain of the fifth transistor to output a change in the internal voltage, a drain is commonly connected to a drain of the second transistor and the fourth transistor, and an internal voltage is input to the gate. A sixth transistor N5 having a source connected to a source of the fifth transistor, a drain connected to a source of a fifth transistor and a sixth transistor, and having a gate connected to the source; Signal is input, and a seventh transistor (N6) is a ground voltage is applied to the source.

The reference voltage may have a level of 1/2 of a reference cell data level voltage, and the internal voltage may have a level of 1/2 of a cell data level voltage.

The sensing unit may include a differential amplifier configured to output a change in an internal voltage detected by comparing a reference voltage and an internal voltage by an enable signal; And an eighth transistor N7 having a cell data level voltage Vcore supplied to a drain, a gate being common to the drain, and a source connected to the differential amplifier, and a drain connected to a source of the eighth transistor N7. It may include a ninth transistor (N8) is common to the drain and the ground voltage is supplied to the source.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram illustrating current improvement of a level shifter in accordance with an embodiment of the present invention. As shown in FIG. 3, the current improvement circuit of the level shifter according to an embodiment of the present invention includes a sensing unit sensing a change in an internal voltage and a sizing transistor turned on according to a signal of the sensing unit. Herein, the internal voltage will be described with an example of the cell data level voltage Vcore.

The sensing unit may be implemented as a differential amplifier that senses and outputs a change in the cell data level voltage by comparing the reference voltage with the cell data level voltage Vcore by an enable signal. The sensing unit may include a divider for supplying a cell data level voltage Vcore to a voltage level HVcore of 1/2, wherein the reference voltage Vrefc is preferably 1/2 of the cell data level voltage. Here, the enable signal will be described by exemplifying the case of the signal BA1 for selecting the bank 1 after the operation of the bank 0.

The differential amplifier includes pMOS transistors P3 and P6 in which a power supply voltage Vdd is supplied to a source and an enable signal is input to a gate, and a drain voltage of the pMOS transistor P6 is supplied to a gate and a power supply voltage Vdd is supplied to a source. The connected pMOS transistors P4 and P5, the nMOS transistor N4 and the drain of which are commonly connected to the drains of the pMOS transistors P3 and P4 and the reference voltage Vrefc is applied to the gate, and the nMOS transistor N4 Inverter INV1 connected to the drain and outputting a change in the voltage of the cell data level, the drain is commonly connected to the drain of the pMOS transistors P5 and P6, the divider output HVcore is input to the gate, and the source is the nMOS transistor. An nMOS transistor N5 connected to the source of N4 and an nMOS transistor whose drain is commonly connected to the sources of the nMOS transistors N4 and N5, an enable signal is input to a gate, and a ground voltage is supplied to the source. It may be configured to include a rotor (N6).

Here, the pMOS transistor P3 and the pMOS transistor P4 have a source and a drain connected in common to operate as a transfer gate. In addition, the pMOS transistor P5 and the pMOS transistor P6 also have a source and a drain connected in common to operate as a transfer gate.

The divider is provided with the cell data level voltage Vcore at the drain, the gate is common to the drain, and the source is connected to the gate of the nMOS transistor N5 of the differential amplifier, and the drain is connected to the source of the nMOS transistor N7. The nMOS transistor N8 is connected to the gate, and the gate is common to the drain and the ground voltage is supplied to the source. The nMOS transistor N7 and the nMOS transistor N8 preferably have the same operating characteristics to supply 1/2 of the cell data level voltage Vcore to the differential amplifier.

The sizing transistor is included in the level shifter and is turned on according to the output signal of the sensing unit to improve the current transfer capability of the level shifter.

Here, the level shifter includes a first pMOS transistor P1 and a second pMOS transistor P2 having a pumping voltage Vpp supplied to a source and a drain and a gate cross-coupled to each other, and a drain of the first pMOS transistor P2. The first nMOS transistor N1 and the drain are connected to the drain of the second pMOS transistor P2 and are connected to the gate and the cell data level voltage Vcore is applied to the gate, and an input signal is applied to the source. It may be a conventional level shifter including a second nMOS transistor N2 to which an input signal is applied and a ground voltage Vss is applied to the source.

The sizing transistor is preferably an nMOS transistor N3 whose drain is commonly connected to the drain of the second nMOS transistor N2 of the level shifter and whose source is commonly connected to the source of the second nMOS transistor N2.

FIG. 4 is a signal flowchart for describing an operation of the current improving circuit of the level shifter of FIG. 3. An operation of the current improving circuit of the level shifter according to an embodiment of the present invention will be described with reference to FIG. 4.

After the bank 0 BA0 is active ACT0 and the write WT command is continuously input from the memory device, a multi-bank operation in which the bank 1 BA1 is active ACT1 may occur. In this multi-bank operation, the cell data level voltage Vcore may be lower than the normal voltage level by a continuous write command.

At this time, when the bank 1 BA1 is active ACT1 and the enable signal is 'high', the nMOS transistor N6 is turned on to operate the current shift circuit of the level shifter.

When the cell data level voltage Vcore drops due to the continuous write command WT, the voltage level of HVcore, which is 1/2 of the cell data level voltage Vcore, is also lowered. That is, the current flowing from the nMOS transistor N4 to which the reference voltage Vrefc is applied to the ground voltage is larger than that of the nMOS transistor N5 to which HVcore is applied. As a result, the voltage levels of the reference voltage Vrefc and HVcore are applied to the node A. The voltage corresponding to the difference of is applied to detect the change in the cell data level voltage Vcore.

The voltage applied to the node A (voltage corresponding to the difference between the reference voltage and the voltage level of the HVcore) is output as the sensing signal DetVcore through the inverter INV1 and applied to the sizing transistor N3. As shown in the present embodiment, when the cell data level voltage drops, the detection signal becomes 'HIGH' to turn on the sizing transistor N3.

Therefore, when the cell data level voltage Vcore is lower than the normal voltage level by the continuous write command in the multi-bank operation in the conventional level shifter, the size of the nMOS transistor N2 of the conventional level shifter is adjusted to adjust the size of the nMOS transistor N2. It is possible to improve the transfer capability.

As described above, the current improving circuit of the level shifter according to the present invention senses a change in the internal voltage and adjusts the transistor size of the level shifter, thereby preventing the malfunction caused by the current and delay flowing through the level shifter. have.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

Claims (6)

A level shifter circuit comprising a pull-up transistor supplied with a pumping voltage (Vpp) and a pull-down transistor applied with a ground voltage (Vss), A detector for comparing a reference voltage with an internal voltage by an enable signal and outputting a change in the detected internal voltage as a detection signal; And And a sizing transistor switched by the sensing signal applied to a gate and having a drain and a source connected to the drain and the source of the pull-down transistor in common. The switched sizing transistor is turned on when the internal voltage is lower than the reference voltage. The method of claim 1, The internal voltage is a cell data level voltage (Vcore) Current improvement circuit of the level shifter. The method of claim 1, The enable signal is a signal that activates another bank after one bank is activated and the cell data voltage is continuously used. Current improvement circuit of the level shifter. The method of claim 3, wherein The sensing unit is supplied with a power supply voltage Vdd to a source and an enable signal input to a gate, a first transistor p3 and a second transistor p6, a power supply voltage Vdd to a source, and a gate to the gate. A third transistor (p4) and a fourth transistor (p5) to which a drain of the second transistor is connected; (N4), an inverter INV1 connected to the drain of the fifth transistor and outputting a change in the internal voltage, a drain is commonly connected to the drain of the second transistor and the fourth transistor, and an internal voltage is input to the gate. A sixth transistor (N5) whose source is connected to the source of the fifth transistor, and a drain is commonly connected to the source of the fifth and sixth transistors and the enable signal is connected to a gate. An input and including a seventh transistor (N6) is a ground voltage is supplied to a source Current improvement circuit of the level shifter. The method of claim 1, The reference voltage has a level of 1/2 of a reference cell data level voltage. The internal voltage has a level of 1/2 of a cell data level voltage. Current improvement circuit of the level shifter. The method of claim 5, The detection unit includes a differential amplifier for outputting a change in the internal voltage detected by comparing the reference voltage and the internal voltage by the enable signal as a detection signal; And An eighth transistor N7 having a cell data level voltage Vcore supplied to a drain, a gate being common to the drain, a source connected to the differential amplifier, a drain connected to a source of the eighth transistor N7, and a gate A ninth transistor (N8) common to the drain and supplied with a ground voltage to the source; Level shifter current improvement circuit.

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