KR100710645B1 - 반도체소자의 금속배선 형성방법 - Google Patents
반도체소자의 금속배선 형성방법 Download PDFInfo
- Publication number
- KR100710645B1 KR100710645B1 KR1020010027325A KR20010027325A KR100710645B1 KR 100710645 B1 KR100710645 B1 KR 100710645B1 KR 1020010027325 A KR1020010027325 A KR 1020010027325A KR 20010027325 A KR20010027325 A KR 20010027325A KR 100710645 B1 KR100710645 B1 KR 100710645B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- metal
- metal wiring
- semiconductor device
- forming
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (5)
- 소정의 하부구조를 가지고 있는 반도체기판 상에 접착력 향상층, 금속층, 비반사층 및 비정질 물질층을 순차적으로 적층한 후, 금속배선이 형성되도록 감광막을 도포하는 단계와;상기 감광막을 마스크로 하여 비정질 물질층을 식각한 후, 다시 상기 감광막을 마스크로 하여 반도체기판 상부까지 식각하여 금속배선을 형성하는 단계와;상기 결과물에 세정공정을 진행한 후, 감광막을 제거하는 단계;를 포함하여 이루어진 것을 특징으로 하는 반도체소자의 금속배선 형성방법.
- 제 1항에 있어서, 상기 접착력 향상층은 Ti/TiN을 사용하여 스퍼터링으로 100∼700Å 정도의 범위로 적층하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.
- 제 1항에 있어서, 상기 금속층은 알루미늄을 스퍼터링 방식으로 6000∼7000Å 정도의 범위로 적층하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.
- 제 1항에 있어서, 상기 비반사층은 Ti/TiN 또는 TiN을 스퍼터링 방식으로 400∼700Å 정도의 범위로 적층하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.
- 제 1항에 있어서, 상기 비정질 물질층은 산화질화막 또는 실리콘산화막을 플라즈마 방식으로 100∼500Å 정도의 범위로 적층하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020010027325A KR100710645B1 (ko) | 2001-05-18 | 2001-05-18 | 반도체소자의 금속배선 형성방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020010027325A KR100710645B1 (ko) | 2001-05-18 | 2001-05-18 | 반도체소자의 금속배선 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020088577A KR20020088577A (ko) | 2002-11-29 |
KR100710645B1 true KR100710645B1 (ko) | 2007-04-24 |
Family
ID=27705467
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020010027325A KR100710645B1 (ko) | 2001-05-18 | 2001-05-18 | 반도체소자의 금속배선 형성방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100710645B1 (ko) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1032334A (ja) * | 1995-12-15 | 1998-02-03 | Hyundai Electron Ind Co Ltd | ゲート電極及びその形成方法 |
KR19990006074A (ko) * | 1997-06-30 | 1999-01-25 | 김영환 | 반도체 소자의 제조방법 |
KR100280810B1 (ko) * | 1994-02-07 | 2001-03-02 | 김영환 | 반도체 소자의 비트라인 형성방법 |
-
2001
- 2001-05-18 KR KR1020010027325A patent/KR100710645B1/ko active IP Right Grant
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100280810B1 (ko) * | 1994-02-07 | 2001-03-02 | 김영환 | 반도체 소자의 비트라인 형성방법 |
JPH1032334A (ja) * | 1995-12-15 | 1998-02-03 | Hyundai Electron Ind Co Ltd | ゲート電極及びその形成方法 |
KR19990006074A (ko) * | 1997-06-30 | 1999-01-25 | 김영환 | 반도체 소자의 제조방법 |
Also Published As
Publication number | Publication date |
---|---|
KR20020088577A (ko) | 2002-11-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4827326A (en) | Integrated circuit having polyimide/metal passivation layer and method of manufacture using metal lift-off | |
US4668335A (en) | Anti-corrosion treatment for patterning of metallic layers | |
JP2000150644A (ja) | 半導体デバイスの製造方法 | |
US5950106A (en) | Method of patterning a metal substrate using spin-on glass as a hard mask | |
US7732224B2 (en) | Metal line pattern of semiconductor device and method of forming the same | |
KR100710645B1 (ko) | 반도체소자의 금속배선 형성방법 | |
US6169029B1 (en) | Method of solving metal stringer problem which is induced by the product of tin and organic ARC reaction | |
JP2003309172A (ja) | デュアルダマシンプロセスにおけるパターン形成方法 | |
US7148150B2 (en) | Method of forming metal line layer in semiconductor device | |
KR100850081B1 (ko) | 반도체 소자의 금속배선 형성 방법 | |
JPH08162460A (ja) | 半導体装置および半導体装置の製造方法 | |
TW411514B (en) | Method of defining passivation pattern | |
KR100220796B1 (ko) | 반도체 기판의 범프 에어리어 형성방법 | |
JP3158844B2 (ja) | 半導体素子の製造方法 | |
JP3225676B2 (ja) | 半導体装置の製造方法 | |
KR100349692B1 (ko) | 강유전체 메모리 소자의 보호막 식각 방법 | |
KR100596793B1 (ko) | 반도체소자의 금속배선 형성방법 | |
JP3630222B2 (ja) | 半導体装置およびその製造方法 | |
KR100309133B1 (ko) | 반도체 소자의 금속배선 형성방법 | |
JP3109506B2 (ja) | パターン形成方法 | |
KR19980048845A (ko) | 반도체소자의 패턴형성방법 | |
KR100517910B1 (ko) | 반도체소자의금속배선구조및그제조방법 | |
JP2000035678A (ja) | パターン形成方法 | |
KR100255156B1 (ko) | 반도체 소자의 금속배선 형성방법 | |
KR100252757B1 (ko) | 금속패턴 형성방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
N231 | Notification of change of applicant | ||
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20130325 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20140318 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20160318 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20170316 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20180316 Year of fee payment: 12 |
|
FPAY | Annual fee payment |
Payment date: 20190318 Year of fee payment: 13 |