KR100681018B1 - Plasma display apparatus and driving method thereof - Google Patents

Abstract

A plasma display device and a driving method thereof are provided to stably drive the plasma display device by preventing damages to scan electrode driving elements due to peaking voltages. A plasma display device includes a PDP(Plasma Display Panel,500), a scan driver(51), and a data driver(52). The PDP includes scan and data electrodes. The scan driver applies a scan pulse to the scan electrode. The scan pulse falls from a scan reference voltage to a negative scan voltage during an address period and then rises back to the scan reference voltage. The data driver decreases a data pulse, which is applied on the data electrode, after the scan pulse rises to the scan reference voltage. The data pulse rises from a ground voltage to a positive data voltage and then falls back to the ground voltage.

Description

Plasma Display Apparatus and Driving Method

1 is a perspective view showing the structure of a typical plasma display panel.

2 is a diagram illustrating a method of implementing image gradation of a conventional plasma display panel.

3 is a view showing a drive waveform of a conventional plasma display panel.

4 is a diagram showing scan pulses and data pulses applied during a conventional address discharge;

5 illustrates a plasma display device according to an exemplary embodiment of the present invention.

6 illustrates a driving waveform of a plasma display device according to an exemplary embodiment of the present invention.

7 is a diagram showing scan pulses and data pulses applied during the address discharge of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device, and more particularly, to a plasma display device and a driving method thereof for improving address discharge to ensure stable driving.

In general, a plasma display panel forms a unit cell with a space between partition walls formed between a front substrate and a rear substrate, and each cell includes neon (Ne), helium (He), or a mixture of neon and helium (Ne +). A main discharge gas such as He) and an inert gas containing a small amount of xenon (Xe) are filled. When discharged by a high frequency voltage, the inert gas generates vacuum ultraviolet rays and emits phosphors formed between the partition walls to realize an image. Plasma display devices employing such plasma display panels have been spotlighted as next generation display devices because they can be made thin and light.

1 is a perspective view showing the structure of a typical plasma display panel.

As shown in FIG. 1, the plasma display panel is coupled in parallel with a front substrate 100, which is a display surface on which an image is displayed, and a rear substrate 110, which forms a rear surface, with a predetermined distance therebetween.

The front substrate 100 is based on the front glass 101, and scan electrodes 102 (Y electrodes) and sustain electrodes 103 (Z electrodes), that is, mutually discharged in one discharge cell and maintain light emission of the cells. The scan electrode 102 and the sustain electrode 103 formed of a transparent electrode a made of a transparent ITO material and a bus electrode b made of a metal material are formed in pairs. Scan electrode 102 and sustain electrode 103 are covered by one or more dielectric layers 104 that limit the discharge current and insulate the electrode pairs, and on top of dielectric layer 104 to facilitate discharge conditions. A protective layer 105 on which magnesium oxide (MgO) is deposited is formed.

The rear substrate 110 is arranged with the stripe-type (or well-type) partition walls 112 to form a plurality of discharge spaces, that is, discharge cells, based on the rear glass 111. In addition, a plurality of address electrodes 113 (X electrodes) for performing address discharge to generate vacuum ultraviolet rays are disposed in parallel with the partition wall 112. The upper surface of the rear substrate 110 is coated with R, G, B phosphors 114 that emit visible light for image display during address discharge. A white dielectric 115 is formed between the address electrode 113 and the phosphor 114 to protect the address electrode 113 and reflect the visible light emitted from the phosphor 114 to the front substrate 100.

A method of implementing gray levels of an image in such a plasma display panel will now be described with reference to FIG. 2.

2 is a diagram illustrating a method of implementing image grayscale of a conventional plasma display panel.

As shown in FIG. 2, the conventional plasma display panel performs time division driving by dividing one frame into several subfields having different number of emission times in order to realize gray level of an image. Each subfield is divided into a reset period for initializing the full screen, an address period for selecting a scan line and selecting a discharge cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. Each of the eight subfields SF1 to SF8 is divided into a reset period RP, an address period AP, and a sustain period SP as described above. In this case, while the reset period RP and the address period AP of each subfield are the same for each subfield, the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2) in each subfield. 3,4,5,6,7).

3 is a diagram illustrating a driving waveform of a conventional plasma display panel.

Referring to FIG. 3, each of the subfields SF has a reset period RP for initializing the discharge cells of the entire screen, an address period AP for selecting the discharge cells, and a sustain for maintaining the discharge of the selected discharge cells. It includes a period SP.

In the reset period RP, the rising ramp waveform PR is simultaneously applied to all the scan electrodes Y in the setup period SU. The rising ramp waveform PR causes a weak discharge (setup discharge) to occur in the cells of the entire screen, thereby generating wall charges in the cells. After the rising ramp waveform PR is applied in the set-down period SD, a predetermined slope from the positive sustain voltage Vs lower than the peak voltage of the rising ramp waveform PR to the negative scan voltage (-Vy) is given. The falling ramp waveform NR, which falls down, is applied to the scan electrodes Y simultaneously. The falling ramp waveform NR generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by setup discharges, thereby uniformly retaining wall charges required for address discharges in the cells of the entire screen. .

In the address period AP, the negative scan pulse SCNP is sequentially applied to the scan electrodes Y, and the positive data pulse DP is applied to the address electrodes. As the voltage difference between the scan pulse SCNP and the data pulse DP and the wall voltage generated in the reset period RP are added, an address discharge is generated in the cell to which the data pulse DP is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, a positive bias voltage Vzb is applied to the sustain electrodes Z during the set down period SD and the address period AP.

In the sustain period SP, the sustain pulse SUSP is applied to the scan electrodes Y and the sustain electrodes Z alternately. Then, the cell selected by the address discharge is in the form of surface discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse SUSP is applied while the wall voltage and the sustain pulse SSUS in the cell are added. Sustain discharge, that is, display discharge for displaying an image, occurs.

In this way, the driving process of the plasma display panel in one subfield is completed.

However, in consideration of the sophisticated discharge mechanism of the plasma display panel, the driving process of the plasma display panel in one subfield includes various problems. Hereinafter, the address discharge process between the scan electrode and the address electrode during the address period will be described. Problems will be described with reference to FIG. 4.

4 is a diagram illustrating a scan pulse and a data pulse applied during a conventional address discharge.

As shown in FIG. 4, conventionally, a state in which the scan electrode Y maintains the negative scan voltage (−Vy) of the data pulse DP applied to the data electrode X to generate an address discharge. The voltage was lowered from the data voltage Va to the ground voltage GND at.

However, by doing this, the peaking voltage (-Vp) is applied to the scan electrode Y due to the variation of the voltage applied to the data electrode X while the scan electrode Y maintains the negative scan voltage (-Vy). As a result, a high voltage (-Vy-Vp) to which the scan voltage (-Vy) and the picking voltage (-Vp) is added is applied to the scan electrode Y, thereby damaging the driving elements driving the scan electrode Y. There is a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a plasma display device and a method of driving the same, which ensure stable driving by improving address discharge.

In accordance with an aspect of the present invention, there is provided a plasma display device including a plasma display panel including a scan electrode and a data electrode, and a scan reference voltage after falling from a scan reference voltage to a negative scan voltage during an address period. And a scan driver for applying a scan pulse rising upward and a data driver for dropping a data pulse applied to the data electrode after the scan pulse rises to the scan reference voltage.

A driving method of a plasma display device according to the present invention is a driving method of a plasma display device in which a plurality of subfields are divided into a reset period, an address period, and a sustain period, respectively, and display an image in frame units in which the subfields are combined. Applying a scan pulse that descends from the scan reference voltage to the negative scan voltage and then rising to the scan reference voltage for the scan electrode and during the address period the data pulse applied to the data electrode after the scan pulse rises to the scan reference voltage. Descending.

The data pulse is characterized by rising from the base voltage to the positive data voltage and then falling to the base voltage.

The scan reference voltage may be greater than -20 volts and less than +20 volts.

The lowest voltage of the scan pulse is characterized by the same as the lowest voltage of the pulse applied to the scan electrode during the reset period.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention;

<Example>

5 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 5, in the plasma display device according to an exemplary embodiment, the data electrodes X1 to Xm, the scan electrodes Y1 to Yn, and the sustain electrode Z in the reset period, the address period, and the sustain period. Plasma display panel 500 which expresses an image by generating a gas discharge in a discharge space containing an inert gas by applying a predetermined driving pulse to the data, and data electrodes X1 to Xm formed on a rear panel (not shown). A data driver 52 for supplying data to the data, a scan driver 51 for driving the scan electrodes Y1 to Yn formed on the front panel (not shown), and a sustain electrode formed on the front panel (not shown). Sustain driver 53 for driving (Z), timing controller 54 for controlling each driver (51, 52, 53), and drive voltage generation for supplying a drive voltage to each driver (51, 52, 53). And a portion 55.

Hereinafter, functions and operations of each component of the plasma display device according to an exemplary embodiment will be described in detail.

First, although not shown, the plasma display panel 500 is bonded to the front panel (not shown) and the rear panel (not shown) at regular intervals with a discharge space including an inert gas therebetween. For example, the scan electrodes Y1 to Yn and the sustain electrode Z are formed in pairs, and on the rear panel, the data electrodes are intersected with the scan electrodes Y1 to Yn and the sustain electrode Z. X1 to Xm) are formed.

The scan driver 51 applies a setup pulse that gradually rises to the scan electrodes Y1 to Yn during the setup period under the control of the timing controller 54. It also applies a progressively falling setdown pulse during the subsequent setdown period.

In addition, the scan driver 51 supplies the scan electrodes Y1 to Yn to select a scan line during an address period after a reset waveform including a setup pulse and a set down pulse is supplied to the scan electrodes Y1 to Yn. The scan pulse is lowered from the scan reference voltage Vsc and the scan reference voltage Vsc to the negative scan voltage (-Vy) and then rises again to the scan reference voltage Vsc.

In addition, the scan driver 51 supplies a sustain pulse to the scan electrodes Y1 to Yn to allow sustain discharge to occur in the selected cell in the address period during the sustain period.

The data driver 52 is subjected to inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like not shown, and then data mapped according to a subfield pattern preset by the subfield mapping circuit is supplied. The data driver 52 samples and latches data under the control of the timing controller 54, and supplies data pulses to the data electrodes X1 to Xm according to the data. In this case, the scan pulse applied to the scan electrodes Y1 to Yn rises from the scan voltage (-Vy) to the scan reference voltage Vsc and then drops the data pulse from the data voltage Va to the base voltage GND. There is a feature of the present invention.

The sustain driver 53 supplies a bias voltage having a sustain voltage Vs level to the sustain electrode Z during at least a part of the reset period and an address period under the control of the timing controller 54, and then the scan driver during the sustain period. Alternately with 51, a sustain pulse is supplied to the sustain electrode Z. As shown in FIG.

The timing controller 54 receives the vertical / horizontal synchronization signal and generates timing control signals CTRX, CTRY, and CTRZ required for each driving unit, and transmits the timing control signals CTRX, CTRY, and CTRZ to the corresponding driving units 51, 52, and the like. 53, the respective drive units 51, 52, 53 are controlled. The timing control signal CTRX applied to the data driver 52 includes a sampling clock for sampling data, a latch control signal, an energy recovery circuit, and a switch control signal for controlling on / off time of the driving switch element. The timing control signal CTRY applied to the scan driver 51 includes a switch control signal for controlling the on / off time of the energy recovery circuit and the drive switch element in the scan driver 51. The timing control signal CTRZ applied to the sustain driver 53 includes a switch control signal for controlling the on / off time of the energy recovery circuit and the drive switch element in the sustain driver 53.

The driving voltage generation unit 55 includes each driving unit 51 and 52 including a sustain voltage Vs, a scan reference voltage Vsc, a data voltage Va, a scan voltage (-Vy), a setup ramp voltage Vst, and the like. And various driving voltages required by the reference numeral 53. These driving voltages may vary depending on the composition of the discharge gas or the structure of the discharge cell.

Hereinafter, the operation principle of the plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 6.

6 illustrates a driving waveform of a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 6, a plasma display device according to an exemplary embodiment implements an image in a frame unit composed of a combination of a plurality of subfields, and each of the subfields SF initializes all cells. The driving period is divided into a reset period RP, an address period AP for selecting a cell to be discharged, and a sustain period SP for maintaining the discharge of the selected cell.

Hereinafter, the voltage applied to each period and its function will be described in detail.

First, in the reset period RP, in the setup period SU, a setup ramp pulse of positive slope is applied to all the scan electrodes Y1 to Yn simultaneously. Such a setup ramp pulse is an example of a setup waveform and may adopt various waveforms in rising form. This setup ramp pulse causes a weak dark discharge in the discharge cells of the entire screen. By this setup discharge, positive wall charges are accumulated on the data electrodes X1 to Xm and the sustain electrode Z, and negative wall charges are accumulated on the scan electrodes Y1 to Yn.

Subsequently, a set down ramp pulse of negative slope is simultaneously applied to all scan electrodes Y1 to Yn in the set down period SD, while a bias voltage having a positive sustain voltage Vs level is applied to the sustain electrode Z. When applied, the positive wall charges of the data electrodes X1 to Xm are maintained as it is, but the positive wall charges of the sustain electrode Z are erased by a discharge amount between the sustain electrode Z and the scan electrodes Y1 to Yn. At the same time, the sustain electrode Z and the scan electrodes Y1 to Yn divide a large amount of negative charges accumulated on the scan electrodes Y1 to Yn.

By this set down discharge, the wall charges such that the address discharge can stably occur remain uniformly in the cells.

On the other hand, such a set down ramp pulse is an example of the set down waveform and can adopt a variety of waveforms in the form of falling.

Next, in the address period AP, the scan pulse is lowered from the scan reference voltage Vsc to the negative scan voltage −Vy to the scan electrodes Y1 to Yn and then rises again to the scan reference voltage Vsc. SCNP is applied, and data pulses DP rising from the base voltage GND to the positive data voltage Va and falling back to the base voltage GND are applied to the data electrodes X1 to Xm in synchronization. When the voltage difference between the data electrodes X1 to Xm and the scan electrodes Y1 to Yn, and the wall between the data electrodes X1 to Xm and the scan electrodes Y1 to Yn due to wall charges formed during the reset period RP, As the voltage is added, an address discharge occurs. In this case, the scan pulse SCNP rises from the scan voltage (-Vy) to the scan reference voltage Vsc, and then the data pulse DP drops from the data voltage Va to the base voltage GND. There is this.

This will be described in more detail with reference to FIG. 7.

7 is a diagram illustrating scan pulses SCNP and data pulses DP applied during address discharge of the present invention.

As shown in FIG. 7, in the present invention, the data pulse DP applied to the data electrode X is converted to the base voltage (V) in the state in which the scan electrode Y maintains the scan reference voltage Vsc. To GND). In this way, even when the peaking voltage (-Vp) is generated at the scan electrode Y due to the falling of the data pulse DP, the voltage applied to the scan electrode Y is equal to the peaking voltage (-Vp) and the scan reference voltage. Since the voltage level (-Vp + Vsc) plus (Vsc) is maintained, the scan electrode Y is compared to the voltage level (-Vp-Vy) applied to the scan electrode Y in the conventional case shown in FIG. The voltage applied is significantly reduced.

The data pulse DP may rise from the base voltage GND to the positive data voltage Va and then fall to the base voltage GND, and the scan reference voltage Vsc may be equal to or greater than -20 volts and +20 volts. It is preferable to set it as follows. By adjusting the level of the scan reference voltage Vsc as described above, it is possible to prevent damage to the scan electrode driving elements due to the picking voltage (-Vp) generated when the data pulse DP falls, and to flexibly respond to the driving environment. .

The minimum voltage (-Vy) of the scan pulse SCNP is preferably equal to the minimum voltage (-Vy) of the pulse applied to the scan electrode Y during the reset period RP. In this way, the plasma display apparatus has a common voltage source for supplying the lowest voltage (-Vy) of the scan pulse SCNP and the lowest voltage (-Vy) of the pulse applied during the reset period RP to the scan electrode Y in common. Reduce manufacturing costs.

On the other hand, the sustain electrode Z has a positive sustain voltage Vs level so as to reduce the voltage difference between the scan electrodes Y1 to Yn during the address period AP so that no misdischarge occurs with the scan electrodes Y1 to Yn. The bias voltage is supplied.

Next, in the sustain period SP, a sustain pulse SUSP that rises from the ground GND to the sustain voltage Vs is applied to the scan electrodes Y1 to Yn and the sustain electrode Z alternately. The cell selected by the address discharge has a sustain discharge, i.e., between the scan electrodes Y1 to Yn and the sustain electrode Z every time the sustain pulse SSUS is applied as the wall voltage and the sustain pulse SSUS in the cell are added. Display discharge occurs.

In this way, the driving process of the plasma display device according to the exemplary embodiment of the present invention in one subfield is completed.

As described in detail above, the plasma display device according to an exemplary embodiment of the present invention improves address discharge and prevents damage of the scan electrode driving elements due to the picking voltage generated on the scan electrode due to the data pulse drop, thereby providing stable driving. On the other hand, the manufacturing cost can be reduced by easing the voltage resistance characteristics of the scan electrode driving elements.

Since the driving method of the plasma display device according to an embodiment of the present invention is driven under the same principle as the plasma display device according to an embodiment of the present invention described in detail above, the detailed description is directed to the plasma display device according to an embodiment of the present invention. Replace with the description.

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the following claims rather than the foregoing detailed description, and the meaning and scope of the claims are as follows. And all changes or modifications derived from the equivalent concept should be construed as being included in the scope of the present invention.

As described in detail above, the plasma display device and the driving method thereof according to the present invention prevent the damage of the scan electrode driving elements due to the picking voltage generated on the scan electrode due to the data pulse drop during the address discharge to ensure stable driving. It works.

In addition, the manufacturing cost can be reduced by alleviating the breakdown voltage characteristics of the scan electrode driving elements.

Claims (8)

A plasma display panel including a scan electrode and a data electrode; A scan driver for applying a scan pulse to the scan electrode during the address period from the scan reference voltage to the negative scan voltage and then rising to the scan reference voltage; And And a data driver configured to drop a data pulse applied to the data electrode after the scan pulse rises to the scan reference voltage. The method of claim 1, And the data pulse rises from a base voltage to a positive data voltage and then falls to the base voltage. The method according to claim 1 or 2, And the scan reference voltage is greater than -20 volts and less than +20 volts. The method of claim 3, wherein And the lowest voltage of the scan pulse is the same as the lowest voltage of the pulse applied to the scan electrode during the reset period. A driving method of a plasma display device, wherein a plurality of subfields are divided into a reset period, an address period, and a sustain period, respectively, and display an image in units of frames in which the subfields are combined. Applying a scan pulse to the scan electrode during the address period from the scan reference voltage to the negative scan voltage and then rising to the scan reference voltage; And And dropping a data pulse applied to a data electrode after the scan pulse rises to the scan reference voltage during the address period. The method of claim 5, And the data pulse rises from a base voltage to a positive data voltage and then falls to the base voltage. The method according to claim 5 or 6, And the scan reference voltage is greater than or equal to -20 volts and less than or equal to +20 volts. The method of claim 7, wherein And the lowest voltage of the scan pulse is the same as the lowest voltage of the pulse applied to the scan electrode during the reset period.

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