KR20060091200A - Driving apparatus for plasma display panel - Google Patents

Abstract

The present invention relates to a driving device of a plasma display panel, and the present invention divides the driving device of the plasma display panel up and down and performs a driving process independently, thereby reducing the capacitance of the panel (Cp) to drive the plasma display panel. Provided is a plasma display panel driver for improving efficiency.

The driving apparatus of the plasma display panel according to the present invention includes a scan driver, a sustain driver, and an address driver, in which a plurality of subfields are divided into a reset period, an address period, and a sustain period, and supply reset pulses, address pulses, and sustain pulses according to each period. In the driving apparatus of the plasma display panel comprising at least one of the scan driver or the sustain driver is divided into a plurality.

Description

Plasma Display Panel Driver {Driving Apparatus for Plasma Display Panel}

1 is a view showing the structure of a typical plasma display panel.

2 is a diagram illustrating a method of expressing image gradation of a conventional plasma display panel.

3 is a view showing a driving waveform of a conventional plasma display panel.

4 is a schematic view showing a driving apparatus of a conventional plasma display panel.

5 is a view briefly illustrating a process of supplying and recovering energy in a driving apparatus of a plasma display panel.

6 is a view showing a driving device of a plasma display panel according to the present invention;

The present invention relates to a driving device of a plasma display panel, and more particularly, by dividing the driving device of the plasma display panel up and down to perform a driving process independently of each other, thereby reducing the capacitance (Cp) of the panel so that The present invention relates to a plasma display panel driving apparatus for improving driving efficiency.

In general, a plasma display panel forms a unit cell with a space between partition walls formed between a front substrate and a rear substrate, and each cell includes neon (Ne), helium (He), or a mixture of neon and helium (Ne +). A main discharge gas such as He) and an inert gas containing a small amount of xenon are filled. When discharged by a high frequency voltage, the inert gas generates vacuum ultraviolet rays and emits phosphors formed between the partition walls to realize an image. Such a plasma display panel has a spotlight as a next generation display device because of its thin and light configuration.

1 illustrates a structure of a general plasma display panel. As shown, the plasma display panel is coupled in parallel with the front substrate 100, which is the display surface on which the image is displayed, and the rear substrate 110 forming the rear surface with a predetermined distance therebetween.

The front substrate 100 is a scan electrode 101 (Y electrode) and a sustain electrode 102 (Z electrode), that is, a transparent electrode formed of a transparent ITO material to discharge each other in one discharge cell and maintain light emission of the cell. And the scan electrode 101 and the sustain electrode 102 provided as a bus electrode b made of a metal material are formed in pairs. The scan electrode 101 and the sustain electrode 102 are covered by one or more dielectric layers 103 which limit the discharge current and insulate the electrode pairs, and the magnesium oxide top surface of the dielectric layer 103 to facilitate the discharge conditions. A protective layer 104 on which (MgO) is deposited is formed.

The rear substrate 110 is arranged such that the strips 111 of a stripe type (or well type) for forming a plurality of discharge spaces, that is, discharge cells, are kept in parallel. In addition, a plurality of address electrodes 112 (X electrodes) that perform address discharge to generate vacuum ultraviolet rays are disposed in parallel with the partition wall 111. On the upper side of the rear substrate 110, R, G, and B phosphors 113 which emit visible light for image display during address discharge are coated. A white dielectric 114 is formed between the address electrode 112 and the phosphor 113 to protect the address electrode 112 and reflect visible light emitted from the phosphor 113 to the front substrate 100.

A method of implementing gray levels of an image in such a plasma display panel is shown in FIG. 2.

2 is a diagram illustrating a method of implementing image grayscale of a conventional plasma display panel. As shown, a gray level display method of a conventional plasma display panel divides one frame into several subfields having different number of emission times, and each subfield has a reset period (RPD) for discharging all cells and a discharge. It is divided into an address period APD for selecting a cell to be used and a sustain period SPD for implementing gray scale according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8, and eight subfields SF1 to SF8) Each is subdivided into a reset period, an address period and a sustain period.

The reset period and the address period of each subfield are the same for each subfield. The address discharge for selecting the cell to be discharged is caused by the voltage difference between the address electrode and the transparent electrode which is the scan electrode. The sustain period is increased at a rate of 2 ⁿ ( ^where n = 0, 1, 2, 3, 4, 5, 6, 7) in each subfield. In this way, since the sustain period is different in each subfield, the gray scale of the image is expressed by adjusting the sustain period of each subfield, that is, the number of sustain discharges. Looking at the driving voltage according to the driving method of the plasma display panel as shown in FIG.

3 illustrates a driving waveform of a conventional plasma display panel.

As shown in FIG. 3, the plasma display panel is driven by being divided into a reset period for initializing all cells, an address period for selecting a cell to be discharged, and a sustain period for maintaining discharge of the selected cell.

In the reset period, the rising ramp voltage is simultaneously applied to all scan electrodes. This rising ramp voltage causes a weak dark discharge within the full discharge cells. By this setup discharge, positive wall charges are accumulated on the address electrode and the sustain electrode, and negative wall charges are accumulated on the scan electrode.

In the set-down period, after the rising ramp voltage is supplied, the falling ramp voltage begins to fall from the positive voltage lower than the peak voltage of the rising ramp voltage and falls to a specific voltage level below the ground (GND) level voltage. By causing the discharge, the wall charges excessively formed on the scan electrodes are sufficiently erased.

By this set-down discharge, wall charges such that the address discharge can stably occur remain uniformly in the cells.

In the address period, a negative scan signal is sequentially applied to the scan electrodes, and a positive data signal is applied to the address electrodes in synchronization with the scan signal. As the voltage difference between the scan signal and the data signal and the wall voltage generated in the reset period are added, address discharge is generated in the discharge cell to which the data signal is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when the sustain voltage Vs is applied. The sustain electrode is supplied with a positive voltage Vzb during the set down period and the address period so as to reduce the voltage difference with the scan electrode so as to prevent erroneous discharge from the scan electrode.

In the sustain period, a sustain signal is alternately applied to the scan electrode and the sustain electrodes. In the cell selected by the address discharge, as the wall voltage and the sustain signal in the cell are added, a sustain discharge, that is, a display discharge occurs between the scan electrode and the sustain electrode every time the sustain signal is applied.

In this way, the driving process of the plasma display panel in one subfield is completed.

4 is a view schematically showing a driving apparatus of a conventional plasma display panel.

As shown in FIG. 4, a conventional plasma display panel driving apparatus includes a scan driver for driving scan electrode lines, a sustain driver for driving sustain electrode lines, and a data driver for driving data electrode lines. It is.

Referring to Figure 3 briefly described the function of each drive unit as follows.

The scan driver supplies a reset pulse during the reset period, a scan pulse during the address period, and a Y sustain pulse during the sustain period to the scan electrode Y.

The sustain driver supplies a Z sustain pulse to the sustain electrode Z during the sustain period.

The data driver supplies a data pulse to the address electrode during the address period.

The scan driver and the sustain driver which perform such a function are generally implemented on one single board.

However, in the light of the recent trend of full-scale high resolution products, the scan driver and the sustain driver are implemented on a single board to drive the plasma display panel, thereby decreasing the driving efficiency of the plasma display panel by increasing the capacitance of the panel. A problem occurs.

In order to solve this problem, the present invention divides the driving apparatus of the plasma display panel up and down, and performs the driving process independently, thereby reducing the capacitance of the panel, thereby improving the driving efficiency of the plasma display panel. It is an object to provide a drive device.

In order to achieve the above object, a driving apparatus of a plasma display panel according to the present invention includes a scan driver configured to supply a reset pulse, an address pulse, and a sustain pulse according to each section, wherein a plurality of subfields are divided into a reset section, an address section, and a sustain section. In the driving apparatus of the plasma display panel including a sustain driver and an address driver, at least one of the scan driver and the sustain driver is divided into a plurality of parts.

The scan driver and the sustain driver are divided up and down, respectively.

The scan driver and the sustain driver are each characterized by two.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

5 is a view briefly illustrating a process of supplying and recovering energy in the driving apparatus of the plasma display panel.

As shown in FIG. 5A, the driving device of the plasma display panel in the process of supplying and recovering energy between the energy supply and recovery capacitor C1 and the panel includes the energy supply and recovery capacitor C1 and the inductor. Equivalent to the series circuit of L) and the panel capacitor Cp.

However, it is assumed that the energy supply and recovery capacitor C1 is a constant power source because its capacity is much larger than that of the panel capacitor Cp.

Hereinafter, referring to an equivalent circuit of the driving device of the plasma display panel during the supply and recovery of energy between the voltage source and the panel shown in FIG. 5 (b), the capacitance Cp value of the panel affects the driving efficiency of the plasma display panel. Look at the impact.

When the current value I (t) is obtained from FIG. 5 (b), Equation 1 is obtained.

Where I (t) is the current flowing from the voltage source to the panel.

However, the actual circuit has a parasitic resistance (R) component. Energy consumption due to the parasitic resistance (R) is shown in Equation 2 below.

As shown in Equation 2, the energy consumption amount W due to the parasitic resistance R is proportional to the panel capacitance Cp and inversely proportional to the inductor L value.

As described above, it can be seen that the panel capacitance Cp lowers the driving efficiency of the plasma display panel.

In particular, in the large-screen, high-resolution plasma display panel, the panel capacitance (Cp) value is inevitably larger. Therefore, countermeasures are necessary.

Therefore, as shown in FIG. 6, the method of dividing the driving device of the plasma display panel is adopted to prevent the driving efficiency of the plasma display panel from being lowered.

6 is a view showing a driving device of a plasma display panel according to the present invention.

As shown in FIG. 6, the driving apparatus of the plasma display panel according to the present invention includes a data driver 62 for supplying data to the address electrodes X1 to Xm of the plasma display panel, and the upper scan electrodes Y1 to The upper scan driver 63a for driving Yn and the lower scan driver 63b for driving the lower scan electrodes Yn + 1 to Y2n, and the upper sustain driver for driving the upper sustain electrodes Z1 to Zn ( 64a) and a lower sustain driver 64b for driving the lower sustain electrodes Zn + 1 to Z2n, a timing controller 61 for controlling each of the drivers 62, 63a, 63b, 64a, and 64b, and each driver. And a driving voltage generator 65 for supplying driving voltages to the 62, 63a, 63b, 64a, and 64b.

The data driver 62 is subjected to inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like not shown, and then data mapped to a subfield pattern preset by the subfield mapping circuit is supplied. The data driver 62 samples and latches data under the control of the timing controller 61, and then supplies the data to the address electrodes X1 to Xm.

The upper scan driver 63a applies a rising pulse voltage that gradually rises to the upper scan electrodes Y1 to Yn to initialize the full screen during the reset period under the control of the timing controller 61 and then gradually increases the rising pulse voltage. The reset voltage including the falling pulse voltage is applied.

After the reset voltage is continuously supplied to the upper scan electrodes Y1 to Yn, the negative scan pulse voltage is sequentially supplied to the upper scan electrode lines Y1 to Yn during the address period to select the discharge cell. .

In addition, after the address period is completed, a sustain pulse is applied to the upper scan electrodes Y1 to Yn to display an image in a cell selected by the address discharge.

In addition, independently of the upper scan driver 63a, the lower scan driver 63b gradually rises to the lower scan electrodes Yn + 1 to Y2n to initialize the full screen during the reset period under the control of the timing controller 61. A rising pulse voltage is applied and a reset voltage is applied, which includes a falling pulse voltage that gradually falls following the rising pulse voltage.

After the reset voltage is continuously supplied to the lower scan electrodes Yn + 1 to Y2n, a negative scan pulse voltage is applied to the lower scan electrode lines Yn + 1 to Y2n during the address period to select a discharge cell. Supply sequentially.

In addition, a sustain pulse is applied to the lower scan electrodes Yn + 1 to Y2n to display an image in a cell selected by the address discharge after the address period is completed.

The upper sustain driver 64a applies a sustain pulse to the upper sustain electrodes Z1 to Zn alternately with the upper scan driver 63a described above in order to display an image in a cell selected by the address discharge after the address period is completed. do.

In addition, independently of the upper sustain driver 64a, the lower sustain driver 64b alternates with the lower scan driver 63b described above to display an image in a cell selected by the address discharge after the address period is completed. A sustain pulse is applied to (Zn + 1 to Z2n).

The timing controller 61 receives the vertical / horizontal synchronization signal and generates timing control signals CTRX, CTRYa, CTRYb, CTRZa, and CTRZb necessary for each of the driving units 62, 63a, 63b, 64a, and 64b, and the timing control signal. Each drive unit 62, 63a, 63b, 64a, 64b is controlled by supplying (CTRX, CTRYa, CTRYb, CTRZa, CTRZb) to the drive units 62, 63a, 63b, 64a, 64b. The timing control signal CTRX applied to the data driver 62 includes a sampling clock for sampling data, a latch control signal, an energy recovery circuit, and a switch control signal for controlling on / off time of the driving switch element. The timing control signal CTRYa applied to the upper scan driver 63a includes an energy recovery circuit in the upper scan driver 63a and a switch control signal for controlling on / off time of the driving switch element. The timing control signal CTRYb applied to the lower scan driver 63b includes an energy recovery circuit in the lower scan driver 63b and a switch control signal for controlling on / off time of the driving switch element. The timing control signal CTRZa applied to the upper sustain driver 64a includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the upper sustain driver 64a. The timing control signal CTRZb applied to the lower sustain driver 64b includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the lower sustain driver 64b.

The driving voltage generator 65 includes a setup voltage Vsetup set to the voltage of the rising ramp waveform, a scan reference voltage Vsc supplied to the scan electrode during the address period, a sustain voltage Vs of the sustain pulse, and a data voltage Va. And various driving voltages required by each of the driving units 62, 63a, 63b, 64a, and 64b.

As described above in detail, the driving apparatus of the plasma display panel according to the present invention divides the driving apparatus of the plasma display panel up and down and performs a driving process independently, thereby reducing the capacitance of the panel, thereby reducing the plasma display panel. Improve the driving efficiency.

As described above, the technical configuration of the present invention described above will be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the following claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

As described above in detail, the present invention divides the driving apparatus of the plasma display panel up and down and performs a driving process independently, thereby reducing the capacitance of the panel, thereby improving the driving efficiency of the plasma display panel. Provide a panel drive.

Claims (3)

A plurality of subfields are divided into a reset section, an address section, and a sustain section, and include a scan driver, a sustain driver, and an address driver for supplying a reset pulse, an address pulse, and a sustain pulse according to each section. , And at least one of the scan driver and the sustain driver is divided into a plurality. The method of claim 1, And the scan driver and the sustain driver are divided up and down, respectively. The method of claim 2, And the scan driver and the sustain driver are two respectively.

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