KR100811593B1 - Plasma display apparatus and driving method there of - Google Patents

Abstract

A plasma display apparatus and a method for driving the same are provided to reduce noises by preventing peak currents in a scan drive IC(Integrated Circuit) using a scan pulse. A plasma display apparatus includes a plasma display panel(100) and a scan driver(123). The plasma display panel includes scan electrodes. The scan driver supplies a scan pulse which is decreased from a reference voltage level to a scan voltage level and has a ramp-up time of 500ns to 1.2 s, to the scan electrodes during an address period. The voltage rising time of the scan pulse extends as the reference voltage level increases.

Description

Plasma Display Apparatus and Driving Method there of}

1 is a diagram illustrating a plasma display device according to an embodiment of the present invention.

2 is a view showing an example of the structure of a plasma display panel of the present invention.

3 is a diagram showing an example of a driving method of the plasma display device of the present invention.

4 illustrates a driving waveform of the plasma display device according to an embodiment of the present invention.

5 illustrates a scan pulse according to an embodiment of the present invention.

6 is a graph illustrating a scan pulse according to an embodiment of the present invention.

7 is a graph illustrating a relationship between a scan pulse and a current according to an embodiment of the present invention.

***** Explanation of symbols for main parts of drawing *****

100: plasma display panel 121: control unit

122: data driver 123: scan driver

124: sustain driver 125: drive voltage generator

The present invention relates to a display device, and more particularly, to a plasma display device and a driving method thereof.

In general, a plasma display apparatus is formed by attaching a plasma display panel for displaying an image and a driving unit for driving the plasma display panel to a rear surface of the plasma display panel.

In general, a plasma display panel is a partition wall formed between a front panel and a rear panel to form a unit discharge cell, and each cell includes neon (Ne), helium (He), or a mixture of neon and helium (Ne + He). An inert gas containing a main discharge gas such as and a small amount of xenon is filled. A plurality of unit discharge cells described above are gathered to form one pixel. For example, a red (R) cell, a green (G) cell, and a blue (B) cell may form one pixel.

When a high frequency voltage is applied to such a unit discharge cell to discharge, an inert gas generates vacuum ultra violet rays and emits phosphors formed between the partition walls to realize an image.

The plasma display panel includes a plurality of electrodes, for example, a scan electrode (Y), a sustain electrode (Z), and an address electrode (X), each of which has driving parts for supplying a driving voltage to the electrodes of the plasma display panel. Is connected to.

Each driving unit implements an image by supplying driving pulses, such as a reset pulse in a reset period, a scan pulse in an address period, and a sustain pulse in a sustain period, to the electrodes of the plasma display panel during a predetermined period in driving the plasma display panel. will be. Such a plasma display device has a spotlight as a display device because of its thin and light configuration.

Meanwhile, in driving the plasma display apparatus by supplying the pulses to each electrode, the reliability of the driving may be deteriorated due to various factors. Accordingly, researches for optimizing the driving conditions of the plasma display apparatus continue to proceed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a plasma display apparatus and a driving method thereof capable of preventing an overcurrent flowing in a driving unit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a plasma display device and a driving method thereof capable of shielding electromagnetic waves.

The technical problem of the present invention is not limited to the above-mentioned thing, and another technical problem to be achieved by the present invention will be clearly understood by those skilled in the art by the effect of the configuration of the present invention.

A plasma display device according to an embodiment of the present invention for achieving the above object is a plasma display panel including a scan electrode; And a scan driver for dropping from a scan reference voltage level to a scan voltage level to the scan electrode and applying a scan pulse having a voltage rise time of 500 kV to 1.2 kV in an address period.

The voltage rise time of the scan pulse is characterized in that more than five times than the voltage fall time of the scan pulse falling from the reference voltage level to the scan voltage level.

The voltage fall time of the scan pulse is characterized in that the time to fall from a voltage of 10% of the scan voltage to a voltage of 90%.

The voltage rise time of the scan pulse is a time that rises from a voltage of 90% of the scan voltage to a voltage of 10%.

The voltage rise time of the scan pulse is characterized in that more than 700 kHz 800 kHz.

The scan reference voltage level range is 110V or more and 135V or less.

The higher the scan reference voltage level is, the longer the voltage rise time of the scan pulse is.

In the driving method of the plasma display device including the scan electrode according to an embodiment of the present invention for achieving the above object, the scan electrode is lowered from the scan reference voltage level to the scan voltage level in the address period, the voltage rises It is characterized by applying a scan pulse having a time of 500 ms or more and 1.2 ms or less.

The voltage rise time of the scan pulse is characterized in that more than five times than the voltage fall time of the scan pulse falling from the reference voltage level to the scan voltage level.

The voltage fall time of the scan pulse is characterized in that the time to fall from a voltage of 10% of the scan voltage to a voltage of 90%.

The voltage rise time of the scan pulse is a time that rises from a voltage of 90% of the scan voltage to a voltage of 10%.

The voltage rise time of the scan pulse is characterized in that more than 700 kHz 800 kHz.

The scan reference voltage level range is 110V or more and 135V or less.

The higher the scan reference voltage level is, the longer the voltage rise time of the scan pulse is.

Hereinafter, with reference to the accompanying drawings will be described in more detail the configuration of the plasma display panel according to the present invention.

1 is a diagram illustrating a plasma display device according to an embodiment of the present invention.

As shown in FIG. 1, the plasma display apparatus according to the present invention includes a plasma display panel 100, a driver for driving electrodes formed on the plasma display panel 100, a controller 121 for controlling the driver, And a driving voltage generator 125 for supplying a driving voltage necessary for the driving units 122, 123, and 124.

The driver includes a data driver 122 for supplying data to the data electrodes X1 to Xm, a scan driver 123 for driving the scan electrodes Y1 to Yn, and sustain electrodes as common electrodes. And a sustain driver 124 for driving (Z).

The plasma display panel 100 is bonded to the upper substrate (not shown) and the lower substrate (not shown) at regular intervals, and a plurality of electrodes, for example, the scan electrodes (Y1 to Yn) and the sustain electrode on the upper substrate as an example. (Z) is formed in pairs, and the data electrodes X1 to Xm are formed on the lower substrate to intersect the scan electrodes Y1 to Yn and the sustain electrode Z.

An example of the structure of the plasma display panel will be described in detail with reference to FIG. 2 to help understanding of the present invention.

2 is a view showing an example of the structure of a plasma display panel of the present invention.

As shown in FIG. 2, the plasma display panel includes a plurality of sustain electrodes formed by pairing scan electrodes 202 and Y and sustain electrodes 203 and Z on the front substrate 201, which is a display surface on which an image is displayed. The rear panel 210 in which the plurality of data electrodes 213 and X are arranged on the front panel 200 having the pairs arranged on the rear substrate 211 intersecting with the plurality of storage electrode pairs described above has a predetermined distance. They are coupled in parallel to each other.

The front panel 200 is, for example, a scan electrode 202 and Y and a sustain electrode 203 and Z for mutually discharging and maintaining light emission in one discharge cell, that is, a transparent electrode formed of a transparent ITO material. And the scan electrodes 202 and Y and the sustain electrodes 203 and Z provided as a bus electrode b made of a metal material may be included in pairs. It is also possible to form only the transparent electrode a or only the bus electrode b. Scan electrodes 202 and Y and sustain electrodes 203 and Z are covered by one or more top dielectric layers 204 that limit the discharge current and insulate the electrode pairs, and discharge on top of top dielectric layer 204. In order to facilitate the condition, for example, a protective layer 205 on which magnesium oxide (MgO) is deposited is formed.

In the rear panel 210, for example, stripe-type or well-type partition walls 212 for forming a plurality of discharge spaces, that is, discharge cells are arranged in parallel. In addition, a plurality of data electrodes 213 and X for performing address discharge to generate vacuum ultraviolet rays are arranged in parallel with the partition wall 212. The upper surface of the rear panel 210 is coated with R, G, and B phosphors 214 that emit visible light for image display during address discharge. A lower dielectric layer 215 is formed between the data electrodes 213 and X and the phosphor 214 to protect the data electrodes 213 and X.

The front panel 200 and the rear panel 210 formed as described above are bonded to each other through a sealing process to form a plasma display panel. The plasma display panel is provided with a driving unit for driving electrodes such as a plurality of electrodes, for example, scan electrodes 202 and Y, sustain electrodes 203 and Z, and data electrodes 213 and X. To achieve.

The method of driving the plasma display device according to the present invention will be described with reference to FIG. 3.

3 is a view showing an example of a driving method of the plasma display device of the present invention.

As illustrated in FIG. 3, the plasma display apparatus of the present invention may drive one frame by dividing the frame into a plurality of subfields. For example, each subfield may be divided into a reset period for initializing all cells, an address period for selecting a cell to be discharged, and a sustain period for implementing gray levels according to the number of discharges.

For example, when displaying an image with 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into a plurality of subfields SF1 to SF8. Each of the eight subfields SF1 to SF8 is divided into a reset period RP, an address period AP, and a sustain period SP as described above. In this case, while the reset period RP and the address period AP of each subfield are the same for each subfield, the sustain period and the number of sustain pulses allocated thereto may be different. For example, gray levels may be expressed by increasing the ratio of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield.

As such, an example of a basic panel structure of the plasma display apparatus and an example of a driving method for implementing an image have been described. Hereinafter, an embodiment of the plasma display device of the present invention of FIG. 1 will be described.

The scan driver 123 is a reset pulse for initializing the wall charge states of all the discharge cells in the previous subfield during the reset period under the control of the controller 121, for example, a setup pulse that is a rising ramp waveform and a setdown pulse that is a falling ramp waveform. Is supplied to the scan electrodes Y1 to Yn.

In addition, the scan driver 123 scans the scan pulse that is lowered to the scan voltage (-Vy) level while maintaining the reference voltage level, for example, the scan reference voltage Vsc, during the address period under the control of the control unit 121. To Y1 to Yn sequentially. Here, the scan driver 123 according to the embodiment of the present invention may control a current flowing through the driver by applying a scan pulse having a voltage rise time of 500 kV to 1.2 kV to the scan electrode. 4 will be described below.

Further, under the control of the control unit 121, the scan driver 123 may alternately apply a sustain pulse to the sustain pulse supplied by the sustain driver 124, which will be described later, to cause sustain discharge.

The data driver 122 is subjected to inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like, and then data mapped to each subfield is supplied by the subfield mapping circuit. The data driver 122 samples and latches data in response to the timing control signal CTRX of the control unit 121, and then supplies the data to the data electrodes X1 to Xm. According to such data, a discharge cell that is turned on / off, i.e., a cell that generates sustain discharge, which is a display discharge, is selected in the sustain period.

When the sustain pulse is applied to the discharge cell supplied with the data pulse in the sustain period, which will be described later, wall charges such that sustain discharge is generated are formed.

The sustain driver 124, for example, supplies the positive voltage Vz to the sustain electrodes Z under the control of the control unit 121.

In addition, the sustain driver 124 operates the sustain drive circuit provided therein during the sustain period alternately with the sustain drive circuit provided in the scan driver 123 to sustain the sustain pulse Vs. Will be supplied to

The control unit 121 receives the vertical / horizontal synchronization signal and the clock signal and receives timing control signals for controlling the operation timing and synchronization of the driving units 122, 123, and 124 in the reset period, the address period, and the sustain period. Each driver is controlled by generating CTRX, CTRY, and CTRZ, and supplying the timing control signals CTRX, CTRY, and CTRZ to the drivers 122, 123, and 124. FIG.

The data control signal CTRX includes a sampling clock for sampling data, a latch control signal, a switch control signal for controlling on / off time of the sustain driving circuit and the driving switch element. The scan control signal CTRY includes a switch control signal for controlling on / off time of the sustain driving circuit in the scan driver 123 and the driving switch element, and the sustain control signal CTRZ includes the sustain in the sustain driver 124. A switch control signal for controlling the on / off time of the driving circuit and the driving switch element is included.

The driving voltage generator 125 generates a setup voltage Vsetup, a scan common voltage Vsc, a scan voltage -Vy, a sustain voltage Vs, a data voltage Va, and the like. These driving voltages may vary depending on the composition of the discharge gas or the structure of the discharge cell.

The configuration of the plasma display device of the present invention described above is an embodiment for the convenience of understanding, and the configuration of the present invention is not limited thereto. In other words, even if the configuration and operation of the driving device are somewhat varied, the configuration and the role of the driving unit of the present invention shown in the claims are considered to be included in the present invention.

4 illustrates a driving waveform of the plasma display device according to an embodiment of the present invention.

As shown in FIG. 4, a driving waveform in one subfield SF among a plurality of subfields implemented by the plasma display apparatus according to an exemplary embodiment of the present invention is shown.

The subfield SF includes a reset period RP for initializing discharge cells of all screens, an address period AP for selecting discharge cells, and a sustain period SP for implementing images by maintaining discharge of the selected discharge cells. Are divided into

In the reset period RP, the high rising ramp waveform PR is simultaneously applied to the scan electrode Y lines in the setup period SU. The rising ramp waveform PR causes a weak discharge (setup discharge) to occur in the cells of the full screen, thereby generating wall charges in the cells. The rising ramp waveform PR may be supplied as a sum of the sustain voltage Vs and the scan reference voltage Vsc.

In the set down period SD, the falling ramp waveform NR is simultaneously applied to the scan electrode Y lines. This falling ramp waveform NR causes a weak erase discharge in the cells, thereby making the wall charges of the excessively accumulated discharge cells generated by the setup discharge uniform.

In the address period AP, the scan pulse SCNP having the scan voltage −Vy is applied to the scan electrode Y lines and the data pulse DP is applied to the data electrode X lines. As the voltage difference between the scan pulse SCNP and the data pulse DP and the wall voltage generated in the reset period RP are added, an address discharge is generated in the cell to which the data pulse DP is applied. Wall charges are generated in the cells selected by the address discharge.

Here, in one embodiment of the present invention, the scan pulse applied to the scan electrode in the address period is adjusted. That is, during the address period, the scan electrode Y drops from the scan reference voltage Vsc level to the scan voltage (-Vy) level, maintains the scan voltage (-Vy) level for a predetermined time, and then scans the scan reference voltage Vsc level. Rising scan pulses are applied. The voltage rise time at which the scan pulse rises from the scan voltage (-Vy) to the scan reference voltage (Vsc) level is 500 ㎱ or more and 1.2 ㎲ or less to control the current flowing to protect the device and shield the electromagnetic wave. Such a scan pulse will be described in detail later with reference to FIG. 5.

On the other hand, a positive voltage (+) is applied to the sustain electrode (Z) lines to maintain a voltage that does not cause discharge with the scan electrode (Y).

In the sustain period SP, a sustain pulse SUSP is applied to the scan electrode Y and the sustain electrode Z alternately to generate sustain discharge.

5 illustrates a scan pulse according to an embodiment of the present invention.

As shown in FIG. 5, an exemplary embodiment of the present invention has a scan electrode having a scan voltage (Vsc) level down to a scan voltage (-Vy) level and having a voltage rise time of 500 mA or more and 1.2 mA or less. Supply a scan pulse. The voltage rise time of the scan pulse can be measured as a time t rising from a voltage of approximately 90% of the scan voltage to a voltage of 10% of the scan voltage.

In addition, the voltage rise time of the scan pulse may be 5 times or more than the voltage fall time of the scan pulse falling from the reference voltage level, for example, the scan reference voltage Vsc to the scan voltage (-Vy) level. Here, the voltage fall time of the scan pulse can be measured as a time that falls from a voltage of approximately 10% of the scan voltage (-Vy) to a voltage of 90% of the scan voltage (-Vy).

As such, the voltage rise time of the scan pulse may be adjusted to prevent overcurrent flowing through the scan driver, particularly the scan driver integrated circuit IC, which is susceptible to impact. Thus, the overcurrent can be prevented to protect the circuit elements and the noise of the pulse can be reduced to ensure the stability of the circuit operation. In addition, the electromagnetic shielding performance is improved to improve the reliability of the plasma display device.

Here, various factors such as the magnitude of the scan reference voltage can be adjusted. Looking at the experimental graph of the scan pulse as shown in FIG. 6.

6 is a graph illustrating a scan pulse according to an embodiment of the present invention.

As illustrated in FIG. 6, the voltage rise time of the scan pulse rising from the scan voltage −Vy to the scan reference voltage Vsc may be adjusted to, for example, 700 mW or more and 800 mW or less. The scan reference voltage (Vsc) level can also be adjusted. For example, the scan reference voltage Vsc may be adjusted from 110V to 135V.

Here, as the scan reference voltage Vsc level increases, the voltage rise time of the scan pulse may also increase. That is, the voltage rise time of the scan reference voltage Vsc and the scan pulse can be adjusted in an optimized state. The factor that can adjust the voltage rise time of the scan pulse is not limited to the scan reference voltage Vsc. The graph of FIG. 6 shows that the scan pulse adjusted as described above is applied to two successive scan electrodes.

In this way, even if the voltage rise time of the scan pulse is adjusted, the application time of the scan pulse applied as a whole does not increase, thereby ensuring a margin of the address period, thereby improving the jitter characteristic. In addition, the circuit shock and the electromagnetic wave can be prevented while improving the accuracy of the address discharge.

7 is a graph illustrating a relationship between a scan pulse and a current according to an embodiment of the present invention.

FIG. 7A shows a current flowing in the scan driver integrated circuit IC when a conventional scan pulse is applied, and FIG. 7B shows a current flowing in the scan driver integrated circuit IC when a scan pulse of the present invention is applied. Indicated.

Looking at the voltage rise period of the conventional scan pulse of Figure 7a it can be seen that the peak current flows to 200mA for about 600ns. Looking at the voltage rise period of the scan pulse of the present invention of Figure 7b it can be seen that the peak current is reduced to 80mA for about 600ns.

As described above, the current flowing through the scan driver integrated circuit (IC) due to the scan pulse of the present invention of FIG. 7B is not the peak current, but rather a small amount of the current flowing smoothly. It becomes a current. It can also be seen that this small amount of current flows slowly for a long time. As a result, the influence of electromagnetic waves can be minimized and noise can be reduced.

The scan pulse of the present invention can be said to be very useful because it can optimize the driving by reducing the influence of electromagnetic waves and securing noise while securing the jitter characteristic which is a significant factor in address discharge.

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all aspects, and the scope of the present invention is indicated by the following claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

As described above, the plasma display device and the driving method thereof of the present invention have the effect of stabilizing the address discharge.

In addition, the plasma display device and the driving method thereof of the present invention have the effect of minimizing the effects of electromagnetic waves.

In addition, the plasma display device and the driving method thereof of the present invention have the effect of preventing overcurrent.

In addition, the plasma display device and the driving method thereof according to the present invention have an effect of improving jitter characteristics and securing an address margin.

Claims (14)

A plasma display panel including a scan electrode; And And a scan driver for dropping from a reference voltage level to a scan voltage level to the scan electrode in an address period, and applying a scan pulse having a voltage rising time of 500 kV to 1.2 kV. And the voltage rise time of the scan pulse increases as the reference voltage level increases. The method of claim 1, And the voltage rise time of the scan pulse is five times or more than the voltage fall time of the scan pulse falling from the reference voltage level to the scan voltage level. The method of claim 2, And the voltage drop time of the scan pulse is a time dropping from a voltage of 10% of the scan voltage to a voltage of 90%. The method of claim 1, And a voltage rising time of the scan pulse is a time rising from a voltage of 90% of the scan voltage to a voltage of 10%. The method of claim 1, And a voltage rise time of the scan pulse is 700 mW or more and 800 mW or less. The method of claim 1, And the reference voltage level range is 110V or more and 135V or less. delete In the driving method of a plasma display device including a scan electrode, In the address period, a scan pulse having a voltage rising time of 500 s or more and 1.2 s or less is applied to the scan electrode from a reference voltage level to a scan voltage level. The driving method of the plasma display apparatus characterized by the above-mentioned. The method of claim 8, And the voltage rise time of the scan pulse is five times or more than the voltage fall time of the scan pulse falling from the reference voltage level to the scan voltage level. The method of claim 9, And the voltage drop time of the scan pulse is a time for dropping from a voltage of 10% of the scan voltage to a voltage of 90%. The method of claim 8, And a voltage rising time of the scan pulse is a time rising from a voltage of 90% of the scan voltage to a voltage of 10%. The method of claim 8, And a voltage rise time of the scan pulse is 700 mW or more and 800 mW or less. The method of claim 8, And the reference voltage level range is 110V or more and 135V or less. delete

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