KR20050111913A - Driving method of plasma display panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel.

In the method of driving a plasma display panel according to the present invention, a first voltage is applied to at least one first electrode of the plurality of first electrodes in an address period for selectively applying a scan pulse to the plurality of first electrodes, The voltage of the first electrode to which the first voltage is applied is gradually raised to a second voltage. In this manner, the low discharge phenomenon can be prevented in the plasma display panel.

Description

Driving method of plasma display panel {DRIVING METHOD OF PLASMA DISPLAY PANEL}

The present invention relates to a method of driving a plasma display panel (PDP).

A plasma display panel is a flat panel display device that displays characters or images using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.

In the DC plasma display panel, since the electrode is exposed to the discharge space as it is, the current flows in the discharge space while the voltage is applied, and for this purpose, a resistance for limiting the current must be made. On the other hand, in the AC plasma display panel, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component, and the life is longer than that of the DC type because the electrode is protected from the impact of ions during discharge.

In such an AC plasma display panel, scan electrodes and sustain electrodes parallel to each other are formed on one surface thereof, and address electrodes are formed on the other surface in a direction orthogonal to these electrodes. The sustain electrode is formed corresponding to each scan electrode, and one end thereof is connected in common to each other.

1 is a partial perspective view of a typical AC plasma display panel.

As shown in FIG. 1, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 4 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 2, the electrodes of the plasma display panel have a matrix form of n × m. Specifically, the address electrodes A ₁ to A _m extend in the column direction and the scan electrode Y in the row direction. _{1 to} Y _n and the sustain electrodes X _{1 to} X _n extend. The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG.

3 is a driving waveform diagram of a conventional plasma display panel.

As shown in FIG. 3, each subfield has a reset period P _r , an address period P _a , and _a sustain period P _s. )

The reset period P _r serves to set up the wall charge to erase the wall charge formed by the previous sustain discharge and to stably perform the next address discharge. An address period (P _a) is turned on to select a cell does not turn on, and the cell is turned on, the panel is a period for performing the operations laying up the wall charges in the cells (the addressed cells). The sustain period P _s is a period in which sustain discharge is performed to actually display an image in the addressed cell.

Conventional plasma In the address period (P _a) in the driving waveform of the display panel, and the other scan electrode (Y) to V by applying a sequential V _{sc_L} voltage to the scan electrode (Y) in a holding state by _{sc_H} voltage scan electrode (Y Select). And it is applied to the address voltage (V _a) to the address electrode (A) to form a discharge cell to be selected among the discharge cells formed by the V _{sc_L} voltage is applied to the scan electrode (Y). In this way, all the scan electrodes Y are sequentially scanned from the first scan electrode Y ₁ to the last scan electrode Y _n . Then, the voltage applied to the address electrodes (A) (V _a) and the wall voltage due to the wall charges formed on the difference and the address electrode (A) and scan electrodes (Y) of the voltage (V _{sc_L)} applied to the scan electrode (Y) This causes address discharge.

However, in such a driving waveform, the wall charges formed in the reset period P _r in the process of sequentially scanning from the first scan electrode Y ₁ to the last scan electrode Y _n in the address period P _a are over time. Will decrease accordingly. Thus, different amounts of wall charges are formed in all the scan electrodes after the address discharge. The discharge at the first scan electrode Y ₁ is greatest, so that a lot of wall charges are formed on each electrode, and as time passes, the wall charges formed on each electrode and priming particles in the discharge space decrease in the reset period P _r . Therefore, the magnitude of the discharge decreases toward the last scan electrode Y _n . As a result, since the amount of addressed wall charges varies according to the position of the panel, there is a problem that the image quality of the plasma display panel is deteriorated.

In addition, the wall discharge and priming particles in the discharge space of each electrode decrease toward the last scan electrode (Y _n ), thereby making the address discharge unstable and causing low discharge in the plasma display panel.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve such a conventional problem, and to provide a method of driving a plasma display panel capable of preventing low discharge in a plasma display panel.

According to one aspect of the present invention, in order to solve this problem, the present invention provides a method for driving a plasma display panel in which discharge cells are formed by a plurality of first electrodes and second electrodes. The driving method includes applying a first voltage to at least one first electrode of a plurality of first electrodes in an address period for selectively applying a scan pulse to the plurality of first electrodes, and wherein the first voltage is Gradually raising the voltage of the applied first electrode to the second voltage. The driving method may further include applying the first voltage to a first electrode other than the first electrode whose voltage rises to the second voltage, wherein the voltage of the first electrode The period in which the first voltage is increased from the first voltage to the second voltage overlaps at least partially with the period in which the first voltage is applied to the other first electrode.

The driving method may further include applying a third voltage to the second electrode of the discharge cell to be turned on among the discharge cells formed on the first electrode to which the first voltage is applied.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification. In addition, when a part is connected to another part, this includes not only a direct connection but also an indirect connection between other elements in between.

In addition, the wall charges mentioned below refer to charges that are formed on the walls of the discharge cells (eg, dielectric layers) close to each electrode and accumulate in the electrodes. This wall charge is not actually in contact with the electrode itself, but here the wall charge is described as "formed", "accumulated" or "stacked" on the electrode. In addition, a wall voltage refers to the potential difference formed in the wall of a discharge cell by wall charge.

Hereinafter, a driving method of a plasma display panel according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a plasma display panel according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the plasma display panel according to an exemplary embodiment of the present invention includes a plasma panel 100, a controller 200, an address driver 300, a sustain electrode driver 400, and a scan electrode driver 500. do.

The plasma panel 100 includes a plurality of address electrodes A1 to Am arranged in the column direction, a plurality of sustain electrodes X1 to Xn arranged in the row direction, and scan electrodes Y1 to Yn.

The controller 200 receives an image signal from the outside and outputs an address driving control signal, a sustain electrode X driving control signal, and a scan electrode Y driving control signal.

The address driver 300 receives an address driving control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The sustain electrode driver 400 receives the sustain electrode X driving control signal from the controller 200 and applies a driving voltage to the sustain electrode X.

The scan electrode driver 500 receives the scan electrode Y driving control signal from the controller 200 and applies a driving voltage to the scan electrode Y.

5 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention. The description of the reset period P _r and the sustain period P _s will be omitted below.

5, the address period (P _a), bias the scan electrodes applying scan pulses sequentially to the scan electrode (Y) and that is not applied with the scan pulse to a voltage (V _{sc_H).} Here, the scan pulse is a pulse for selecting the scan electrode Y by sequentially applying the selection voltage V _{sc_L} to the scan electrode Y while maintaining the other scan electrode Y at the V _{sc_H} voltage.

According to an embodiment of the invention, an address period (P _a) in sequence the selection of a scan pulse applied to the voltage (V _{sc_L1, sc_L2} V) to the scan electrode (Y) in a two-stage level. _{Hereinafter, the} voltage V _{sc_L1} is referred to as a first selection voltage and the voltage V _{sc_L2} is referred to as a second selection voltage.

And applies an address voltage (V _a) to the address electrode (A) passing through the discharge cell to be selected from a plurality of discharge cells formed by the first selection voltage (V _{sc_L1)} is applied to the scan electrode (Y). Then, an address voltage applied to the electrodes (A) (V _a) and the differential, and the address electrode wall by wall charges formed in the (A) and scan electrodes (Y) of the voltage (V _{sc_L1)} applied to the scan electrode (Y) The address discharge is caused by the voltage.

The time (t ₁ + t ₂ ) at which the scan pulse is applied is the sum of the time (t ₁ ) at which the first selection voltage is applied and time (t ₂ ) at which the second selection voltage is applied, and overlaps the adjacent scan line. . Thus, the longer than the time (t ₁₎ to which the scan pulse in the address period (P _a) of the conventional plasma display panel. Here, the time corresponds to the width of the scan pulse. In this case, the first selection voltage V _{sc_L1} of the scan pulse is a voltage that causes the address discharge to _occur in the cell (addressed cell) that is turned on by selecting a cell that is not turned on and a cell that is not turned on in the plasma display panel. The second selection voltage V _{sc_L2} is a voltage which forms a wall charge after the address discharge by the first selection voltage V _{sc_L1} . Thus, the first selection voltage (V _{sc_L1)} of the scan pulse is the address voltage and the voltage to cause address discharge along with (V _a), scanning a second selection voltage (V _{sc_L2)} of the pulse applied to the address electrode (A) It is a voltage so as to cause the address discharge with the address voltage (V _a) applied to the address electrode (a).

In detail, the scan electrode Y ₁ of the first scan line has the first selection voltage V _{sc_L1} at the scan electrode Y while maintaining the other scan electrode Y at the voltage V _{sc_H} for t ₁ hour. Is applied to select the scan electrode (Y) and the address voltage (V _a ) to the address electrode (A) forming the discharge cell to be selected among the discharge cells formed by the scan electrode (Y) to which the V _{sc_L1} voltage is applied. Is applied to cause an address discharge. The wall charge is accumulated by applying the second selection voltage V _{sc_L2} to the scan electrode Y ₁ of the first scan line for t ₂ hours. The time t ₂ causes the address discharge by applying an address voltage (V _a) a first selection voltage (V _{sc_L1)} at the same time is applied to the address electrode (A) to the second scan electrode (Y ₂₎ for the second scan line. After t ₂ hours, the second selection voltage V _{sc_L2} is applied to the scan electrode Y ₂ of the second scan line to accumulate wall charges formed by the address discharge generated above. Similarly, the first selection voltage V _{sc_L1} is applied to the scan electrode Y ₃ of the third scan line at the same time as the wall charge is accumulated on the scan electrode Y _{2 of the} second scan line.

That is, the time when the second selection voltage V _{sc_L2} of the scan pulse is applied to the scan electrode Y _m of the m th scan line is the scan pulse from the scan electrode Y _{m + 1} of the adjacent scan line m + 1. The time when the first selection voltage V _{sc_L1} is applied and the time when the first selection voltage V _{sc_L1} of the scan pulse is applied to the m th scan electrode is equal to that of the scan electrode of the adjacent scan line m-1. Y _m-1 ) overlaps the time when the second selection voltage V _{sc_L2} of the scan pulse is applied.

In this case, even if the time t _{1 when} the first selection voltage V _{sc_L1} for the address discharge is applied is short, the wall charges can be sufficiently accumulated on all the scan electrodes after the address discharge, and in the subsequent sustain period P _s . It is easy to cause maintenance discharge.

In the driving waveform of the plasma display panel according to the first embodiment of the present invention, the time t _{1 when} the first selection voltage V _{sc_L1} of the scan pulse is applied and the time t when the second selection voltage V _{sc_L2} is applied ₂ ) are the same, but may be different. Hereinafter, such an embodiment will be described in detail with reference to FIG. 7.

7 is a driving waveform diagram of a plasma display panel according to a second embodiment of the present invention.

7, the time at which the applied second selection voltage (V _{sc_L2)} than the time (t ₁₎ which is applied to the first selection voltage (V _{sc_L1)} of the scan pulse (t ₂₎ is longer. In this case, after the address discharge by the first selection voltage V _{sc_L1} , more wall charges can be accumulated than in the driving waveform of the plasma display panel according to the first embodiment.

In the first and second embodiments of the present invention, the first and second selection voltages V _{sc_L1} and V _{sc_L2} of the scan pulse are applied in a step form, but may be different. Such an embodiment will be described in detail with reference to FIG. 8.

8 is a driving waveform diagram of a plasma display panel according to a third exemplary embodiment of the present invention.

As shown in FIG. 8, the scan electrode Y is selected by applying the first selection voltage V _{sc_L1} to the scan electrode Y while maintaining the other scan electrode Y at the voltage V _{sc_H} for t ₁ hour. And an address voltage V _a is applied to an address electrode A forming a discharge cell to be selected among the discharge cells formed by the scan electrode Y to which the V _{sc_L1} voltage is applied, causing an address discharge, and then t _2. and it applies a second ramp voltage that gradually rises from voltage V _{sc_H} in the first selection voltage (V _{sc_L1)} to the scan electrode (Y) during a selected time. As such, when a ramp voltage gradually rising from the first selection voltage V _{sc_L1} to the V _{sc_H} voltage is applied, the time to reach the V _{sc_H} voltage becomes longer, thereby allowing more wall charges to be accumulated.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, there is an effect that the low discharge generated due to poor address discharge in the address period can be eliminated.

1 is a schematic partial perspective view of an AC plasma display panel.

2 is an arrangement diagram of electrodes of a plasma display panel.

3 is a driving waveform diagram of a conventional plasma display panel.

4 is a schematic conceptual diagram of a plasma display panel according to an exemplary embodiment of the present invention.

5 is a driving waveform diagram of a plasma display panel according to a first embodiment of the present invention.

6 is a driving waveform diagram of a plasma display panel according to a second embodiment of the present invention.

7 is a driving waveform diagram of a plasma display panel according to a third exemplary embodiment of the present invention.

Claims (3)

A driving method of a plasma display panel in which discharge cells are formed by a plurality of first electrodes and second electrodes, In an address period for selectively applying a scan pulse to the plurality of first electrodes, Applying a first voltage to at least one first electrode of the plurality of first electrodes, and Gradually increasing the voltage of the first electrode to which the first voltage is applied to a second voltage; Method of driving a plasma display panel comprising a. The method of claim 1, Applying the first voltage to a first electrode other than the first electrode where the voltage rises to the second voltage More, And a period in which the voltage of the first electrode rises from the first voltage to the second voltage and at least a portion of the period in which the first voltage is applied to the other first electrode overlap. The method of claim 1, Applying a third voltage to the second electrode of the discharge cell to be turned on among discharge cells formed on the first electrode to which the first voltage is applied; The driving method of the plasma display panel further comprising.