KR100674830B1 - Multilayered chip capacitor array - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked capacitor, comprising: a capacitor body formed by stacking a plurality of dielectric layers; A second internal electrode, at least one first external terminal and a plurality of second external terminals formed on at least one of an upper surface and a lower surface of the capacitor body, and formed in a stacking direction of the capacitor body to form the first external terminal and the first And at least one first conductive via hole and a plurality of second conductive via holes respectively connected to the second external terminal, wherein the at least one first conductive via hole is connected to the first internal electrode, and electrically connected to the second internal electrode. And the plurality of second conductive via holes include k (k ≧ 2) including at least one second conductive via hole. The second internal electrode is divided into k groups including at least one second internal electrode, and the second conductive via hole of each group is connected to the second internal electrode of each group, and A stacked capacitor array is electrically isolated from a second internal electrode and the first internal electrode.

Multi-Layered Chip Capacitors, Equivalent Series Inductance (ESL), Decoupling Capacitors

Description

Multilayer Capacitor Array {MULTILAYERED CHIP CAPACITOR ARRAY}

1A and 1B are exploded and schematic perspective views showing a stacked capacitor array according to a conventional example, respectively.

2A and 2B are schematic perspective and side cross-sectional views of a stacked capacitor array in accordance with one embodiment of the present invention.

3A to 3C show the arrangement of the inner electrode and the conductive via hole of each dielectric layer employed in the stacked capacitor array shown in FIG. 2B, respectively.

4A and 4B are schematic diagrams for explaining an ESL reduction effect in a stacked capacitor array according to the present invention.

5A to 5C are top plan views and cross-sectional views, respectively, of a stacked capacitor array according to another embodiment of the present invention.

6A and 6B are top plan views and cross-sectional views respectively illustrating stacked capacitor arrays according to still another embodiment of the present invention.

<Code Description of Main Parts of Drawing>

20: stacked capacitor array 21: capacitor body

22a, 22b: second internal electrodes 23a, 23b

24a and 24b: second conductive via holes 25: first conductive via holes

26a, 26b: first external terminal 27: first external terminal

The present invention relates to a stacked capacitor, and more particularly, a plurality of capacitors are implemented as one chip, and more particularly, to a stacked capacitor.

In general, the stacked capacitor MLCC has a structure in which an internal electrode is inserted between a plurality of dielectric layers. These MLCCs are widely used as components of various electronics because of their small size, high capacity, and easy mounting.

Recently, in order to miniaturize components and to easily mount, there is a need for a stacked capacitor array in which two or more capacitors having the same or different capacitances are implemented in one chip.

1A and 1B are exploded and schematic perspective views showing a stacked capacitor array according to a conventional example, respectively.

Referring to the exploded perspective view of FIG. 1A, two first internal electrodes 12a and 12b and two second internal electrodes 13a and 13b are formed in each of the plurality of dielectric layers 11a and 11b. The first and second internal electrodes 12a, 12b, 13a, and 13b have leads 14a, 14b, 15a, and 15b drawn from one side thereof. The dielectric layers 11a and 11b on which the first and second internal electrodes 12a, 12b, 13a, and 13b shown in FIG. 1A are formed are stacked to form the capacitor body 11 as shown in FIG. 1B. In addition, as shown in FIG. 1B, external terminals 16a, 16b, 17a, and 17b connected to the leads 14a, 14b, 15a, and 15b are formed to complete the stacked capacitor 10.

In such a structure, the first and second internal electrodes 12a and 13a on one side and the first and second internal electrodes 12b and 13b on the other side operate independent capacitors. The conventional stacked capacitor array 10 illustrated in Figs. 1A and 1B has a disadvantage in that miniaturization is difficult when configuring three or more capacitors by configuring other capacitors in a horizontal arrangement.

In addition, the conventional stacked capacitor array 10 has a relatively large equivalent series inductance (ESL), and therefore, there is a problem that it is not suitable as a decoupling capacitor connected between a semiconductor chip and a power supply, especially in a power supply circuit such as an LSI.

As a method of reducing a general equivalent series inductance, a structure in which a plurality of leads are drawn out and arranged so that leads of different polarities cross each other is disclosed in US Patent 5,880,925, but a conventional stacked capacitor array in which a plurality of internal electrodes are arranged horizontally Not suitable for adoption. In other words, when the lead is doubled on one side of one internal electrode in the stacked capacitor array shown in FIG. 1A, the lead number is increased by the product according to the number of capacitors, so that the lead is increased for sufficient ESL reduction in a limited space. There is a structural problem that makes it difficult.

Therefore, the conventional stacked capacitor array has a disadvantage in that it is difficult to miniaturize due to structural limitations, and there is a limit in changing a lead structure for reducing ESL.

The present invention is to solve the above-mentioned problems of the prior art, the object is to configure a plurality of capacitors using the conductive via hole formed in the stacking direction and the external terminal provided on the upper or lower surface of the capacitor body, and further, each conductive via hole The present invention provides a stacked capacitor array capable of improving the ESL reduction effect by properly disposing the position.

In order to achieve the above technical problem, the present invention

A capacitor body formed by stacking a plurality of dielectric layers, a plurality of pairs of first and second internal electrodes formed on the plurality of dielectric layers and alternately disposed to face each other with one dielectric layer interposed therebetween, and the capacitor body At least one first external terminal and a plurality of second external terminals formed on at least one of an upper surface and a lower surface of the at least one surface, and at least one connected to the first external terminal and the second external terminal in a stacking direction of the capacitor body And a first conductive via hole and a plurality of second conductive via holes, wherein the at least one first conductive via hole is connected to the first internal electrode, is electrically insulated from the second internal electrode, and the plurality of second conductive via holes. The conductive via hole is divided into k (k≥2) groups including at least one second conductive via hole, and the second internal electrode is red. FIG. 5 is divided into k groups including one second internal electrode, and the second conductive via holes of each group are connected to the second internal electrodes of the respective groups, and the second internal electrodes and the first internal electrodes of the other groups. Provides a stacked capacitor array, which is electrically insulated.

Preferably, the first and second conductive via holes may be disposed such that magnetic fields induced by currents flowing through the internal electrodes connected to each other cancel each other, thereby reducing ESL.

In a preferred embodiment for reducing ESL, the second conductive via holes of each group adjacent to the particular first conductive via holes are arranged at the same interval as the particular first conductive via holes.

In addition, the first conductive via hole may be plural, and in this case, it is preferable to arrange the first and second conductive via holes at respective corner positions of substantially square, in terms of improving ESL. In particular, in this embodiment, it is more preferable to arrange | position the said 1st conductive via hole in the two opposite corners diagonally among the said corners, and arrange | positioning another group of 2nd conductive via holes in the other two corners, respectively.

According to an embodiment, the second internal electrodes connected to the second conductive via holes of one group may be installed to be electrically insulated without being connected to the second conductive via holes of the other group so that the second internal electrodes of each group do not overlap each other. Can be. Alternatively, at least one internal electrode may overlap at least two groups in the second internal electrode of each group.

In addition, the second internal electrodes of each group may be the same number, and each capacitor may be designed to have the same capacitance value. Alternatively, the number of the second internal electrodes of the at least one group may be the second internal electrode of the other group. In contrast to the number of, at least one capacitor portion can be designed to have different capacitance. Similarly, the number of at least one group of second conductive via holes may be different from the number of other groups of second conductive via holes.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A and 2B are schematic perspective and side cross-sectional views of a stacked capacitor array in accordance with one embodiment of the present invention. This embodiment illustrates a stacked capacitor array comprising two capacitors having the same capacitance.

Referring to FIG. 2A, the stacked capacitor array 20 according to the present embodiment includes a capacitor body 21, and a first external terminal 27 and two groups of second external terminals 26a and 26b on an upper surface thereof. Is formed. The first external terminal 27 is connected to the negative polarity and is shared by two capacitors, and the second external terminal 26a of one group is provided as a positive terminal of one capacitor, and The second external terminal 26b may be provided as a positive terminal of another capacitor. In FIG. 2A, the upper surface of the capacitor body is illustrated, but external terminals 26a, 26b and 27 corresponding to the upper surface may be formed on the lower surface of the capacitor body.

In the present embodiment, the first and second external terminals 27, 26a and 26b and the internal electrodes 25 and 24 are connected by the conductive via holes 25, 24a and 24b formed in the vertical direction as shown in FIG. 2B. Is implemented. FIG. 2B may be understood as a cross-sectional view taken along the line AA ′ of the stacked capacitor array 20 of FIG. 2A.

As shown in FIG. 2B, the main body 21 of the stacked capacitor array 20 is formed by stacking a plurality of dielectric layers 21a to 21e, and the first and second internal electrodes are disposed on the dielectric layers 21a to 21e. (25, 24a, 24b) are alternately arranged to face each other with one dielectric layer in between.

In addition, the first conductive via hole 25 is connected to the two first internal electrodes 22a and 22b to electrically connect the first external terminal 27 and the first internal electrodes 22a and 22b. . However, the first conductive via hole 25 is electrically insulated from the two second internal electrodes 23a and 23b through an open area.

One second conductive via hole 24a is connected to one second internal electrode 22a as indicated by C to electrically connect the second internal electrode 22a to the second external terminal 26a. The first internal electrodes 23a and 23b and the other second internal electrodes 22b are electrically insulated through the open region as indicated by O. Similarly, another second conductive via hole 24b is connected to the other second internal electrode 22b to electrically connect the second internal electrode 22b with the second external terminal 26b. The first internal electrodes 23a and 23b and the other second internal electrodes 22a are electrically insulated through the open area.

In FIG. 2B, the connection structure of the conductive via hole connected to the outermost terminal of the front row along the A-A 'direction and the internal electrode therethrough has been described. Similarly, the connection of the outer terminal of the other row to the inner electrode using the conductive via hole is similar. Has a structure.

That is, the first external terminal 27 is electrically connected to the second internal electrodes 22a and 22b while being connected to the first internal electrodes 23a and 23b as in the first conductive via hole 25 shown in FIG. 2B. The second external terminal 26a related to the first (+) polarity and the second external terminal 26b related to the second (+) polarity have a separated structure, respectively, and have a lowermost second internal electrode 22a. Or it is formed to be electrically connected only to the other second internal electrode (22b).

The connection structure shown in FIG. 2B can be described in more detail with reference to FIGS. 3A to 3C.

3A to 3C show internal electrodes 22a, 22b, 23a, and 23b and conductive via holes 24a, respectively, of the dielectric layers 21a, 21b, 21c, and 21d employed in the stacked capacitor array 20 shown in FIG. 2b, respectively. The arrangement of 24b, 25) is shown.

Referring to FIG. 3A, a second internal electrode 22a formed on the first dielectric layer 21a of FIG. 2B is illustrated. As shown, only the second conductive via hole 24a related to the first (+) polarity is connected to the second internal electrode 22a, and the second conductive via hole 24b different from the first conductive via hole 25 is connected. Electrically separated by the open area.

As shown in FIG. 3B, only the second conductive via hole 24b related to the second (+) polarity is connected to the second internal electrode 22b formed on the third dielectric layer 21c and is connected to the first conductive via hole 25. The other second conductive via holes 24a are electrically separated by the open area.

In addition, the first internal electrodes 23a and 23b formed on the second dielectric layer 21b and the fourth dielectric layer 21c may have a first conductive via hole 25 related to the (−) polarity, as shown in FIG. 3C. And is electrically isolated from all of the second conductive via holes 24a and 24b.

The arrangement illustrated in this embodiment is advantageous in that the magnetic fields induced by the current flowing through the internal electrodes cancel each other out. That is, as shown in FIGS. 3A to 3B, the first and second conductive via holes 25, 24a and 24b are continuously arranged to be positioned at respective corners of a substantially square shape, and further, the first conductive via holes 25 are provided. ) Are disposed at two diagonally opposite corners of the corners, and the second conductive via holes 24a and 24b of different groups (associated with the first (+) polarity and the second (+) polarity) are respectively two remaining corners. Posted in As such, the first and second conductive via holes 26 and 24a and 24b associated with opposite polarities are arranged regularly adjacently so that the corresponding first and second internal electrodes 22a, 23a and 22b as indicated by arrows. At 23b, the current direction may be reversed. Therefore, the generated magnetic field can be effectively canceled to greatly reduce the ESL.

4A and 4B are schematic diagrams for explaining an ESL reduction effect in a stacked capacitor array according to the present invention.

In the stacked capacitor array shown in FIG. 2B, when a voltage is applied to the first external terminal 27 and the second external terminal 26a related to the first (+) polarity, the second external terminal ( In the second conductive via hole 24a connected to 26a and the first conductive via hole 25 adjacent thereto, magnetic fluxes opposite to each other may be generated to cancel each other. Also, when voltage is applied to the first external terminal 27 and the second external terminal 26b related to the second (+) polarity, the second conductive via hole connected to the second external terminal 26b as shown in FIG. 4B. At 24b and the first conductive via hole 25 adjacent thereto, magnetic fluxes opposite to each other are generated and canceled out.

As described above, in the vertical connection structure through the conductive via holes 24a, 24b, and 25 according to the present invention, the ESL can be greatly reduced by reducing the magnetic field between the conductive via holes associated with adjacent opposite polarities.

In order to further improve the ESL reduction effect in the present invention, it is preferable to arrange the second conductive via holes of each group adjacent to the specific first conductive via holes at the same interval as the specific first conductive via holes, but from the outside, The arrangement structure of the conductive via hole may be changed to facilitate the connection of the terminal and the external circuit. Such an embodiment is illustrated in FIGS. 5A-5C.

5A to 5C are top plan views and cross-sectional views, respectively, of a stacked capacitor array 50 according to another embodiment of the present invention.

Referring to FIG. 5A, the upper surface of the capacitor body 51 has a first external terminal 57 related to the negative polarity and a second external terminal 56a and a second positive polarity related to the first polarity. The second external terminal 56b associated with is formed. Eight first external terminals 57 are arranged in two columns on one side, and the second external terminals 56a and 56b are divided into groups and arranged in four squares in the other two columns.

FIG. 5B is a cross-sectional view taken along line BB ′ in FIG. 5A. Referring to FIG. 5B, a first conductive via hole 55 connected to the first external terminal 57 and a second conductive via hole 54a connected to a second external terminal 56a related to the first (+) polarity. The first and second internal electrodes 52a, 52b, 53a, 53b and a connection structure are shown.

The first conductive via hole 55 is connected to the two first internal electrodes 53a and 53b to electrically connect the first external terminal 57 and the first internal electrodes 53a and 53b. The second internal electrodes 52a and 52b are electrically insulated through the open region. In addition, the second conductive via hole 54a is connected to one second internal electrode 52a to electrically connect the second internal electrode 52a to the second external terminal 56. The electrode 53 is electrically insulated from the second internal electrode 52b through the open area.

5C is a cross-sectional view taken along line C-C 'in FIG. 5A. 5C, a first conductive via hole 55 connected to the first external terminal 57 and a second conductive via hole 54b connected to a second external terminal 56a related to the second (+) polarity. The first and second internal electrodes 52a, 52b, 53a, 53b and a connection structure are shown.

As shown in FIG. 5B, the second conductive via hole 54b is connected to the two first internal electrodes 53a and 53b to electrically connect the first external terminal 57 and the first internal electrodes 53a and 53b. The second internal electrodes 52a and 52b are electrically insulated from each other through an open area. The second conductive via hole 54b is connected to one second internal electrode 52b to electrically connect the second internal electrode 52b to the second external terminal 56b and to connect the first internal electrode 52b. The second internal electrodes 52a and 53a and 53b are electrically insulated through the open area.

In the present embodiment, the ESL reduction effect is expected to be limited to only two rows in which the other polarities of the first external terminal 57 and the second external terminal 56a and 56b are adjacent to each other, but the terminal arrangement is simplified to facilitate mounting. There may be advantages.

In the above-described embodiment, the first and second conductive via holes are plural in number, and the same number of embodiments are exemplified. However, this is for convenience of description and only one of the first conductive via holes may be shared. have.

In addition, although only a stacked capacitor array having two capacitors is illustrated and described, three or more capacitors may also be implemented. In this case, the plurality of second conductive via holes and the plurality of second internal electrodes may be manufactured by dividing the plurality of capacitors into the same number of groups to implement the connection structure described above.

6A and 6B are top plan views and cross-sectional views respectively illustrating a stacked capacitor array 60 having three capacitors as still another embodiment of the present invention. The stacked capacitor array 60 exemplifies a form in which three capacitors are formed by sharing a negative polarity and being separated and connected only for the positive polarity.

Referring to FIG. 6A, the first external terminal 67 associated with the negative polarity and the second external terminals 66a and 66b associated with the positive polarity may be formed on the upper surface (or may be the lower surface) of the capacitor body 61. 66c), and the second external terminals related to the (+) polarity are divided into second external terminals 66a, 66b and 66c related to the first to third (+) polarities, respectively.

In addition, the external terminal arrangement structure of the present embodiment arranges the external polarities of the positive polarities at the corners of the square so that the external terminals of the different polarities ((+), (-)) are adjacent to the external terminals of the same polarity. It is arranged so that the negative terminal of the negative polarity is located at the center thereof.

FIG. 6B is a cross-sectional view taken along the line D-D 'in FIG. 6A. Referring to FIG. 6B, a first conductive via hole 65 connected to the first external terminal 67 and second external terminals 66a, 66b and 66c associated with the first to third (+) polarities, respectively; The connection structure of the connected second conductive via holes 64a, 64b, 64c is shown.

The first conductive via hole 65 is connected to the three first internal electrodes 63a, 63b and 63c to electrically connect the first external terminal 67 and the first internal electrodes 63a, 63b and 63c. The three second internal electrodes 62a, 62b, and 62c are electrically insulated from each other through the open area.

Second conductive via holes 64a, 64b, and 64c related to the first to third polarities are connected to one second internal electrode 62a, 62b or 62c, respectively, and the first internal electrodes 63a, 63b and 63c. ) And two other second internal electrodes 62b and 62c; 62a, 62c or 62a and 62b are electrically insulated through the open area.

In addition, as in the present embodiment, the second conductive via holes 64c related to the third (+) polarity may have a larger number than the second conductive via holes 64a and 64b related to the other (+) polarity. The second conductive via holes 64c associated with the third (+) polarity are the same number of second internal electrodes 62c as the number of internal electrodes 62a or 62b connected to the other second conductive via holes 64a or 64b, respectively. It is connected, but at the same time, it is connected to both sides spaced apart to ensure a larger capacitance value.

In a similar manner, a second internal electrode connected to a second conductive via hole related to a group of (+) polarities may be implemented to have a different capacitance by varying the number of other internal electrodes. In addition, although the second internal electrode is illustrated as an embodiment not correspondingly overlapping with the group of the second conductive via holes, the second internal electrode may be connected to the second conductive via hole related to the positive polarity of the other group. Capacitor array structures can be implemented.

In addition, the first and second external terminals are formed to correspond to the number of the first and second conductive via holes, respectively, but external terminals of the same polarity and the same group may be connected to each other and partially integrated. For example, in FIG. 3A, the conductive material may be additionally printed in the diagonal direction to connect the external terminals of the same group with the same polarity. In FIG. 6, the external terminal may be additionally printed by additionally printing the conductive material in the row direction. You can connect it very much.

The above-described embodiments and the accompanying drawings are merely illustrative of preferred embodiments, and the present invention is intended to be limited by the appended claims. In addition, it will be apparent to those skilled in the art that the present invention may be substituted, modified, and changed in various forms without departing from the technical spirit of the present invention described in the claims.

As described above, the stacked capacitor array according to the present invention may not only arrange a plurality of capacitors horizontally, but also have a structure that is advantageous for miniaturization by adopting a vertical connection structure through conductive via holes, and also arrange conductive via holes. The structure can effectively reduce the ESL.

Claims (11)

A capacitor body formed by stacking a plurality of dielectric layers; A plurality of pairs of first and second internal electrodes respectively formed on the plurality of dielectric layers and alternately disposed to face each other with one dielectric layer interposed therebetween; At least one first external terminal and a plurality of second external terminals formed on at least one of an upper surface and a lower surface of the capacitor body; And, At least one first conductive via hole and a plurality of second conductive via holes formed in a stacking direction of the capacitor body and connected to the first external terminal and the second external terminal, respectively, The at least one first conductive via hole is connected to the first internal electrode, and electrically insulated from the second internal electrode, The plurality of second conductive via holes are divided into k groups (k≥2) including at least one second conductive via hole, and the second internal electrodes are divided into k groups including at least one second internal electrode. The second conductive via holes of each group are connected to the second internal electrodes of each group and electrically insulated from the second internal electrodes and the first internal electrodes of another group, The first and second conductive via holes are stacked capacitor array, characterized in that the magnetic field induced by the current flowing in the internal electrode connected to each other to cancel each other. delete The method of claim 1, And the second conductive via holes of each group adjacent to the specific first conductive via holes are arranged at the same spacing as the specific first conductive via holes. The method of claim 1, The first capacitor via hole is a plurality of stacked capacitor array, characterized in that. The method of claim 4, wherein And the first and second conductive via holes are arranged at respective corner positions of a substantially square shape. The method of claim 5, The first conductive via holes are disposed at two corners facing each other diagonally among the corners. And a second group of second conductive via holes in each of the other two corners. The method of claim 1, And the number of at least one group of second conductive via holes is different from the number of second conductive via holes in another group. The method of claim 1, And the second internal electrodes of the groups do not overlap each other. The method of claim 1, The second internal electrode of each group of the stacked capacitor array, characterized in that at least one internal electrode is overlapped in at least two groups. The method of claim 1, And the second internal electrodes of each group have the same number. The method of claim 1, And the number of the second internal electrodes of the at least one group is different from the number of the second internal electrodes of the other group.

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