KR100674823B1 - Wiring connection structure of multilayered chip capacitor array - Google Patents

Abstract

The present invention relates to a wiring connection structure of a stacked capacitor array, comprising: a mother substrate having at least two power supply lines and a ground line; And a stacked capacitor array package mounted on the mother substrate and including a wiring board including a micro processing unit (MPU) chip and a stacked capacitor array mounted below the wiring board, wherein the power supply line and the ground line At least one of them provides a wiring connection structure of a stacked capacitor array, which is connected to a terminal of an MPU chip through a conductive via hole of the stacked capacitor array.

Multi-Layered Chip Capacitor Array, Equivalent Series Inductance (ESL), Decoupling Capacitor, Micro Processing Unit (MPU)

Description

WIRING CONNECTION STRUCTURE OF MULTILAYERED CHIP CAPACITOR ARRAY}

1A and 1B are exploded and schematic perspective views showing a stacked capacitor array according to a conventional example, respectively.

2A and 2B are schematic perspective and side cross-sectional views of a stacked capacitor array to which the wiring connection structure of the present invention is applied.

3 shows a wiring connection structure of a stacked capacitor array according to an embodiment of the present invention.

4 shows a wiring connection structure of a stacked capacitor array according to another embodiment of the present invention.

<Code Description of Main Parts of Drawing>

20: stacked capacitor array 21: capacitor body

22a, 22b: second internal electrode 23a, 23b: first internal electrode

24a and 24b: second conductive via holes 25: first conductive via holes

26a, 26b: second external terminal 27: first external terminal

31, 51: wiring board 35, 55: MPU chip

41,61: Mosquito Board

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a stacked capacitor array, and more particularly, to a wiring connection structure employable in a stacked capacitor array including a plurality of capacitor portions and having external terminals formed on upper and lower surfaces of each capacitor portion.

In general, a multi-layered chip capacitor has a structure in which internal electrodes are inserted between a plurality of dielectric layers. These MLCCs are widely used as components of various electronics because of their small size, high capacity, and easy mounting.

Recently, in order to miniaturize components and to easily mount, there is a need for a stacked capacitor array in which two or more capacitors having the same or different capacitances are implemented in one chip.

1A and 1B are exploded and schematic perspective views showing a stacked capacitor array according to a conventional example, respectively.

Referring to the exploded perspective view of FIG. 1A, two first internal electrodes 12a and 12b and two second internal electrodes 13a and 13b are formed in each of the plurality of dielectric layers 11a and 11b. The first and second internal electrodes 12a, 12b, 13a, and 13b have leads 14a, 14b, 15a, and 15b drawn from one side thereof. The dielectric layers 11a and 11b on which the first and second internal electrodes 12a, 12b, 13a, and 13b shown in FIG. 1A are formed are stacked to form the capacitor body 11 as shown in FIG. 1B. In addition, as shown in FIG. 1B, external terminals 16a, 16b, 17a, and 17b connected to the leads 14a, 14b, 15a, and 15b are formed to complete the stacked capacitor 10.

In such a structure, the first and second internal electrodes 12a and 13a on one side and the first and second internal electrodes 12b and 13b on the other side serve as independent capacitors. The conventional stacked capacitor array 10 illustrated in Figs. 1A and 1B has a disadvantage in that miniaturization is difficult when configuring three or more capacitors by configuring other capacitors in a horizontal arrangement.

In addition, the conventional stacked capacitor array 10 has a relatively large equivalent series inductance (ESL), and therefore, there is a problem that it is not suitable as a decoupling capacitor connected between a semiconductor chip and a power supply, especially in a power supply circuit such as an LSI.

As a method of reducing a general equivalent series inductance, a structure in which a plurality of leads are drawn out and arranged so that leads of different polarities cross each other is disclosed in US Patent 5,880,925, but a conventional stacked capacitor array in which a plurality of internal electrodes are arranged horizontally Not suitable for adoption. In other words, when the lead is doubled on one side of one internal electrode in the stacked capacitor array shown in FIG. 1A, the lead number is increased by the product according to the number of capacitors, so that the lead is increased for sufficient ESL reduction in a limited space. There is a structural problem that makes it difficult.

Therefore, the conventional stacked capacitor array is not only difficult to miniaturize due to structural limitations, but also has a disadvantage in that there is a limitation in changing a lead structure for reducing ESL, and to improve this, Korean Patent Application No. 2004-89314 (Applicant) : Samsung Electro-Mechanics Co., Ltd., filed date: Nov. 4, 2004, proposed a new stacked chip capacitor array having a conductive via hole connected to an internal electrode and an external terminal connected to a conductive via hole on the upper or lower surface of a capacitor. .

However, according to the structural change for reducing the ESL, a wiring connection structure suitable for the stacked capacitor array is required. That is, in order to use the stacked capacitor array disclosed in the above document, the interconnection structure of the wiring board package and the mother board such as the PC board is appropriately changed along with the internal structure of the wiring board package having the array structure and the MPU chip. To be required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the related art, and an object thereof is to provide a wiring connection structure suitable for a stacked capacitor array having low ESL characteristics, including conductive via holes formed in the stacking direction and external terminals provided on the upper or lower surface of the capacitor body. To provide.

In order to achieve the above technical problem, the present invention

A mother substrate having at least two power supply lines and a ground line; And a stacked capacitor array package mounted on the mother substrate and including a wiring board including a micro processing unit (MPU) chip and a stacked capacitor array mounted below the wiring board, wherein the stacked capacitor array includes a plurality of stacked capacitor arrays. A capacitor body formed by stacking two dielectric layers, a plurality of pairs of first and second internal electrodes alternately disposed to face each other with one dielectric layer interposed therebetween, an upper surface of the capacitor body, and And a plurality of first and second external terminals formed on at least one surface of the lower surface, and a plurality of first and second conductive via holes formed in the stacking direction of the capacitor body and connected to the first and second external terminals, respectively. And the plurality of first conductive via holes are connected to the first internal electrode and electrically disconnected from the second internal electrode. The plurality of second conductive via holes are divided into at least two groups including at least one second conductive via hole, and the plurality of second internal electrodes are included in at least two groups including at least one second internal electrode. The second conductive via hole of each group is connected to the second internal electrode of each group, and is electrically insulated from the second internal electrode and the first internal electrode of another group, and the ground line is connected to the first internal electrode. Connected to an external terminal line, wherein the at least two power lines are respectively connected to a second external terminal connected to the at least two groups of second conductive via holes, and at least one of the ground line and the at least two power lines is the stacked type A wiring connection structure of a stacked capacitor array, which is connected to the MPU chip through a first or second conductive via hole of a capacitor. To provide.

Preferably, first and second external terminals connected to at least one of the ground line, at least one of the at least two power lines, and the first or second conductive via hole connecting the MPU chip are formed on upper and lower surfaces of the capacitor body. Can be.

At least two power lines of the printed circuit board may each be connected to the MPU chip through at least two groups of second conductive via holes, and in addition, the ground line of the printed circuit board may be connected to the MPU chip through the first conductive via holes. Can be connected to.

In addition, the first and second external terminals of the stacked capacitor array are formed at least on the upper surface of the capacitor, and the arrangement and the spacing thereof are formed to be substantially the same as the terminal arrangement and the spacing of the MPU chip. The structure can be simplified.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A and 2B are schematic perspective and side cross-sectional views of a stacked capacitor array in accordance with one embodiment of the present invention. This embodiment illustrates a stacked capacitor array comprising two capacitors having the same capacitance.

Referring to FIG. 2A, the stacked capacitor array 20 according to the present embodiment includes a capacitor body 21, and a first external terminal 27 and two groups of second external terminals 26a and 26b on an upper surface thereof. Is formed. The first external terminal 27 is connected to the negative polarity and is shared by two capacitors, and the second external terminal 26a of one group is provided as a positive terminal of one capacitor, and The second external terminal 26b may be provided as a positive terminal of another capacitor. In FIG. 2A, only the upper surface of the capacitor body is illustrated, but external terminals 26a, 26b and 27 corresponding to the upper surface may also be formed on the lower surface thereof (see FIG. 2B).

In the present embodiment, the connection between the first and second external terminals 27, 26a and 26b and the first and second internal electrodes 23a, 23b, 22a and 22b is formed in a conductive via hole in a vertical direction as shown in FIG. 2B. Implemented by (25, 24a, 24b). FIG. 2B may be understood as a cross-sectional view taken along the line AA ′ of the stacked capacitor array 20 of FIG. 2A.

As shown in FIG. 2B, the main body 21 of the stacked capacitor array 20 is formed by stacking a plurality of dielectric layers 21a to 21e, and the first and second internal electrodes are disposed on the dielectric layers 21a to 21e. 23a, 23b, 22a, and 22b are alternately arranged to face each other with one dielectric layer interposed therebetween.

In addition, the first conductive via hole 25 is connected to the two first internal electrodes 23a and 23b to electrically connect the first external terminal 27 to the first internal electrodes 23a and 23b. . However, the first conductive via hole 25 is electrically insulated from the two second internal electrodes 22a and 22b through an open area.

One second conductive via hole 24a is connected to one second internal electrode 22a as indicated by C to electrically connect the second internal electrode 22a to the second external terminal 26a. The first internal electrodes 23a and 23b and the other second internal electrodes 22b are electrically insulated through the open region as indicated by O. Similarly, another second conductive via hole 24b is connected to the other second internal electrode 22b to electrically connect the second internal electrode 22b with the second external terminal 26b. The first internal electrodes 23a and 23b and the other second internal electrodes 22a are electrically insulated through the open area.

In FIG. 2B, the connection structure of the conductive via hole connected to the outermost terminal of the front row along the A-A 'direction and the internal electrode therethrough has been described. Similarly, the connection of the outer terminal of the other row to the inner electrode using the conductive via hole is similar. Has a structure.

That is, the first external terminal 27 is electrically connected to the second internal electrodes 22a and 22b while being connected to the first internal electrodes 23a and 23b as in the first conductive via hole 25 shown in FIG. 2B. Each of the second external terminal 26a related to the first (+) polarity and the second external terminal 26b related to the second (+) polarity have a separated structure, and each of the second internal electrode 22a or the lowest It is formed to be electrically connected only to the other second internal electrode 22b.

The stacked capacitor array shown in Figs. 2A and 2B requires a new wiring connection structure to be applied as an actual decoupling capacitor. That is, a wiring connection structure suitable for the first external terminal 27 related to the (-) polarity and the second external terminals 26a and 26b related to the first and second (+) polarities is required. It is desirable to have a structure in which parasitic inductance components are minimized by having a shortened wiring path using first and / or second conductive via holes penetrating the stacked capacitor array.

3 shows a wiring connection structure that satisfies this requirement. The stacked capacitor array used in this embodiment can be understood as the stacked capacitor array shown in Figs. 2A and 2B.

Referring to FIG. 3, the interconnection structure 60 of the stacked capacitor array includes a mother substrate 61 such as a PC board and a stacked capacitor array package 50. The stacked capacitor array package 50 includes a wiring board 51 having internal circuit structures 53a, 53b, 54a, 54b, 54c, 57a, 57b, 57c, 58a, 58b, and 58c, and microprocessing mounted thereon. Unit (MPU) 55. In addition, the wiring board 51 may include a cavity region C provided below, and the stacked capacitor array 20 may be mounted in the cavity region C.

First and second power supply lines PWL1 and PWL2 and a ground line GND are installed on the mother substrate 61. The ground line GND provided through the mother substrate 61 is connected to the second external terminal 27 provided on the bottom surface of the stacked capacitor array 20 by connecting means such as soldering S. The ground line GND connected to the first external terminal 27 is connected to the first external terminal 27 formed on the upper surface through the first conductive via hole 25 of the capacitor array 20, and the wiring board 51. It is connected to the terminal 56 of the MPU chip through the internal circuit (54c, 57c, 58c) of.

The first and second power supply lines PWL1 and PWL2 are connected to the MPU chip through the internal circuit structures 53a, 53b, 54a, 54b, 57a, 57b, 58a and 58b of the wiring board connected to the socket structures 52a and 52b. It is connected to the terminal 56 of the 55 and the terminals 26a and 26b of the stacked capacitor 20 and the MPU chip 55 through the internal circuit structures 54a, 54b, 57a, 57b, 58a and 58b. The stacked capacitors 20 are also connected to each other.

As such, the connection structure between the stacked capacitor array 20 and the ground line GND of the MPU chip 55 is connected to the MPU chip 55 and the mother substrate 61 through the first conductive via hole 25. Can be shortened. Therefore, the manufacturing process of the wiring board 51 can be simplified, and the parasitic inductance component can be reduced by shortening the connection line path with the ground line GND.

3 illustrates an array 20 including two capacitor portions, that is, a capacitor array 20 in which a second external terminal is formed of two groups 26a and 26b, but according to the present invention. The connection structure 60 may similarly be applied to a stacked capacitor array including three or more capacitor parts. More specifically, the power supply line of the mother substrate 61 may be additionally installed according to the number of capacitor parts (the number of groups of the second external terminals), and an appropriate wiring connection structure may be implemented by applying the connection method described in FIG. have.

As such, by connecting the MPU chip with a plurality of power supply lines through the stacked capacitor array, the capacity of the capacitor for the variable current can be appropriately selected.

In the present embodiment, only the ground line GND is connected through the first conductive via hole 25 structure. However, at least one of the first and second power lines PWL1 and PWL2 may be additionally or selectively selected. The second conductive via holes 24a and 24b may be connected to the MPU chip 55.

Further, the first and second power lines PWL1 and PWL2 are preferably omitted so that the circuits 53a and 53b of the wiring board 51 associated with the first and second power lines PWL1 and PWL2 may be omitted. And the ground line GND may be connected to each other through the first and second conductive via holes 25, 24a, and 24b of the stacked capacitor array 20. This embodiment is shown in FIG.

Referring to FIG. 4, the interconnection structure 40 of the stacked capacitor array includes a mother substrate 41 such as a PC board and a stacked capacitor array package 30. The stacked capacitor array package 30 includes a wiring board 31 having vertical connection structures 37a, 37b, and 37c, such as conductive via holes, and a micro processing unit (MPU) 35 mounted on an upper surface thereof. In addition, a cavity region C that can be mounted below the wiring board 31 may be provided, and the stacked capacitor array 20 may be mounted in the cavity region C.

The mother substrate 41 is provided with first and second power supply lines PWL1 and PWL2 and a ground line GND. The first and second power supply lines PWL1 and PWL2 and the ground line GND, which are provided through the mother substrate 41, are both external terminals 26a, 26b, and 27 provided on the bottom surface of the stacked capacitor array 20. ) Is connected by a connecting means S, such as soldering. More specifically, the ground line GND is connected to the first external terminal 27 associated with the negative polarity, and the first power supply line PWL1 is connected to the second external group of the first polarity associated with the first (+) polarity. The second power supply line PWL2 is connected to a second external terminal 26b of another group associated with the second (+) polarity.

Therefore, all the lines PWL1, PWL2, and GND of the mother substrate are formed through the first and second conductive via holes 25, 24a, and 24b of the capacitor array 20, respectively. 27, 26a, and 26b, and the external terminals 27, 26a, and 26b on the upper surface of each terminal of the MPU chip 35 through the vertical connection structures 37a, 37b, and 37c of the wiring board 31, respectively. Connected to 36.

As such, the connection path between the MPU chip 35 and the mother substrate 31 is shortened through the first and second conductive via holes 24a, 24b, and 25 of the stacked capacitor array 20 to manufacture the wiring board 41. The process can be simplified and the parasitic inductance component can be reduced by shortening the connection line path.

In addition, in the present embodiment, since the first and second external terminals 27, 26a, and 26b of the stacked capacitor array have substantially the same arrangement and spacing as the terminal 36 of the MPU chip 35, The internal circuit of the wiring board 31 may be formed of only the vertical connection structures 37a, 37b, and 37c such as conductive via holes. Therefore, the internal circuit path of the wiring board 31 can be further simplified, thereby effectively reducing the parasitic inductance component.

The above-described embodiments and the accompanying drawings are merely illustrative of preferred embodiments, and the present invention is intended to be limited by the appended claims. In addition, it will be apparent to those skilled in the art that the present invention may be substituted, modified, and changed in various forms without departing from the technical spirit of the present invention described in the claims.

As described above, according to the present invention, a variable current is provided by providing a wiring connection structure in which at least one of a power supply line or a ground line is directly connected to an MPU chip through a conductive via hole of a stacked capacitor array having external terminals formed on upper and lower surfaces thereof. Not only can the capacity of the decoupling capacitor be selectively adjusted according to the supply, but also the wiring connection can be simplified to effectively reduce the parasitic inductance component.

Claims (5)

A mother substrate having at least two power supply lines and a ground line; And, A stacked capacitor array package mounted on the mother substrate and including a wiring board having a micro processing unit (MPU) chip and a stacked capacitor array mounted below the wiring board, The stacked capacitor array, A capacitor body formed by stacking a plurality of dielectric layers, a plurality of pairs of first and second internal electrodes alternately disposed to face each other with a dielectric layer interposed therebetween, and a top surface of the capacitor body And a plurality of first and second external terminals formed on at least one surface of the lower surface, and a plurality of first and second conductive via holes formed in a stacking direction of the capacitor body and connected to the first and second external terminals, respectively. And the plurality of first conductive via holes are connected to the first internal electrodes, and electrically insulated from the second internal electrodes, and the plurality of second conductive via holes include at least two second conductive via holes. Each of the plurality of second internal electrodes is divided into at least two groups including at least one second internal electrode. A second conductive via hole of the group is connected to the second internal electrode of each group and electrically insulated from the second internal electrode and the first internal electrode of another group, The ground line is connected to the first external terminal, and the at least two power lines are respectively connected to a second external terminal connected to the at least two groups of second conductive via holes, And at least one of the at least two power lines and the ground line is connected to the MPU chip through associated first or second conductive via holes of the stacked capacitor. The method of claim 1, Multilayer capacitors, characterized in that the first and second external terminals associated with at least one of the at least two power lines and ground lines and the first or second conductive via holes connecting the MPU chip are formed on the upper and lower surfaces of the capacitor body. Array wiring structure. The method of claim 1, And at least two power lines of the printed circuit board are connected to the MPU chip through at least two groups of second conductive via holes, respectively. The method of claim 3, And a ground line of the printed circuit board is connected to the MPU chip through the first conductive via hole. The method of claim 1, And the arrangement and spacing of the first and second external terminals of the stacked capacitor array are substantially the same as the arrangement and spacing of the terminals of the MPU chip.

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