JP4635749B2 - Multilayer capacitor - Google Patents

Description

  The present invention relates to a capacitor configured by alternately laminating a plurality of internal electrodes via a dielectric layer, and more particularly to a multilayer capacitor used as a decoupling capacitor connected to a power supply circuit.

  Conventionally, a multilayer capacitor in which internal electrodes are stacked via a dielectric layer is known. 17 and 18 show an example of the configuration of a conventional general multilayer capacitor. The multilayer capacitor includes a capacitor body 101 having a substantially rectangular parallelepiped shape, a positive electrode terminal electrode 102 formed on a first outer side surface portion in the longitudinal direction of the capacitor body 101, and a second electrode facing the first outer side surface. And a negative electrode terminal electrode 103 formed on the outer side surface portion. In the capacitor body 101, as shown in FIG. 18, a plurality of sets of internal electrodes, each of which includes an internal positive electrode 111 and an internal negative electrode 112, are interposed via a dielectric layer 113 made of, for example, a ceramic dielectric. Are stacked. The internal positive electrode 111 and the internal negative electrode 112 have a substantially rectangular shape and are stacked so as to alternately face each other in the stacking direction. One end of the internal positive electrode 111 is exposed to the first external side surface of the capacitor body 101 and is electrically connected to the positive terminal electrode 102. One end of the internal negative electrode 112 is exposed to the second external side surface of the capacitor body 101 and is electrically connected to the negative terminal electrode 103.

  By the way, a capacitor usually has an equivalent series resistance (ESR) and an equivalent series inductance (ESL) in addition to a capacitance component, thereby forming a resonance circuit and functioning as a capacitor in a band higher than the resonance frequency. No longer. Since the resonance frequency becomes higher as the value of ESL is smaller, it is desired to reduce ESL in the capacitor. In particular, a decoupling capacitor used in a power supply circuit of a semiconductor integrated circuit is required to have a low ESL corresponding to high-speed operation.

  Patent Documents 1 and 2 disclose techniques for reducing ESL in multilayer capacitors. With reference to FIG. 19, FIG. 20, and FIG. 21, the low ESL capacitor with the low ESL will be described. This low ESL capacitor includes a substantially rectangular parallelepiped capacitor body 201, and a positive electrode terminal electrode 202 and a negative electrode terminal electrode 203 formed on the first and second external side surfaces of the capacitor body 201 facing in the short direction. I have. The positive electrode terminal electrode 202 and the negative electrode terminal electrode 203 are alternately arranged within each side surface. A plurality of sets of internal electrodes, each of which includes an internal positive electrode 211 and an internal negative electrode 212, are stacked inside the capacitor main body 201 via a dielectric layer 213 made of, for example, a ceramic dielectric. The internal positive electrode 211 and the internal negative electrode 212 are laminated so as to alternately oppose each other in the vertical direction. Note that in FIG. 19, only one set of internal electrodes is illustrated for the sake of simplicity, but a plurality of sets of internal electrodes may be stacked.

  As shown in FIG. 20, the internal positive electrode 211 has a substantially rectangular shape as a whole, and a plurality of convex positive-side extraction electrodes 221 that are electrically connected to the positive-side terminal electrode 202 are provided on two sides facing each other in the short-side direction. Is formed. Similarly, as shown in FIG. 21, the internal negative electrode 212 has a substantially rectangular shape as a whole, and convex negative electrode side extraction electrodes 222 that are electrically connected to the negative electrode terminal electrode 203 are provided on two sides facing each other in the short direction. A plurality are formed. The positive electrode-side extraction electrode 221 and the negative electrode-side extraction electrode 222 are formed at positions where they are alternately arranged in the horizontal plane when viewed from above and below with the internal positive electrode 211 and the internal negative electrode 212 facing each other. Has been. The end of the positive electrode lead electrode 221 is exposed to the first and second external side surfaces of the capacitor body 201 and is electrically connected to the positive electrode terminal electrode 202. Similarly, the negative electrode side extraction electrode 222 has an end portion exposed to the first and second external side surfaces of the capacitor body 201 and is electrically connected to the negative electrode side terminal electrode 203.

With such a configuration, in the internal positive electrode 211, as shown in FIG. 20, the current i flows inward from the end side of the positive electrode 221. On the other hand, in the internal negative electrode 212, on the contrary, as shown in FIG. 21, the current i flows from the inner side to the end 222 side of the negative electrode. In this way, the direction in which the current i flows is reversed between the internal positive electrode 211 and the internal negative electrode 212. As a result, the direction of the magnetic field generated by the current i in the internal positive electrode 211 and the direction of the magnetic field generated by the current i in the internal negative electrode 212 are reversed, and these magnetic fields cancel each other. Thereby, ESL can be reduced.
JP 2001-185441 A JP 2003-168621 A

  However, in this low ESL capacitor, the occurrence of ESL does not occur only in the internal electrodes 211 and 212, but actually occurs also in the external terminal electrodes 202 and 203. For this reason, if the ESL countermeasure is taken only for the internal electrodes 211 and 212, the effect of reducing the ESL is insufficient.

  With reference to FIGS. 22A, 22B, and 23, ESL in the terminal electrodes 202 and 203 will be described. FIG. 23 schematically shows the arrangement of the terminal electrodes 202 and 203 viewed from the upper surface direction. Similarly to the direction in which the current flows in the internal electrodes 211 and 212 described with reference to FIGS. 20 and 21, the direction in which the current i flows is opposite in the positive terminal electrode 202 and the negative terminal electrode 203. The magnetic fields generated from each other cancel each other (see FIG. 22B). Here, when attention is paid to the portions of the terminal electrodes 202 and 203 as shown in FIG. 23, a virtual ground plane GND is formed between the positive terminal electrode 202 and the negative terminal electrode 203. In other words, it can be said that the ESL is reduced by the effect of the virtual ground plane GND formed near the terminal electrodes 202 and 203. However, in this structure, since the facing area between the terminal electrodes 202 and 203 is small with respect to the virtual ground plane GND, the effect of reducing the ESL at the terminal electrode portion is reduced. Therefore, if the facing area between the terminal electrodes 202 and 203 can be increased, it is considered that ESL can be further reduced in the portions of the terminal electrodes 202 and 203.

  The present invention has been made in view of such problems, and an object thereof is to provide a multilayer capacitor capable of greatly reducing ESL in a terminal electrode portion.

  A multilayer capacitor according to the present invention includes a capacitor body having at least one set of first internal electrodes and second internal electrodes stacked alternately via dielectric layers and dielectric layers, and provided outside the capacitor body. A first terminal electrode of at least one layer conducted to the first internal electrode, and a second terminal electrode of at least one layer provided outside the capacitor body and conducted to the second internal electrode; At least one insulator layer that insulates the first terminal electrode and the second terminal electrode is provided. And the 1st terminal electrode and the 2nd terminal electrode are laminated | stacked alternately so that it may partially oppose through an insulator layer.

  In the multilayer capacitor according to the present invention, the first terminal electrode and the second terminal electrode are alternately laminated so as to partially face each other with the insulator layer interposed therebetween. The area of the terminal electrode facing the virtual ground plane increases. Thereby, the magnetic field generated in the first terminal electrode and the magnetic field generated in the second terminal electrode sufficiently cancel each other, and ESL is reduced.

In the multilayer capacitor according to the present invention, the capacitor body is formed in a substantially rectangular parallelepiped shape, the first internal electrode is provided with a first extraction electrode that is electrically connected to the first terminal electrode, and the second internal electrode Is formed with a second extraction electrode that is electrically connected to the second terminal electrode, and an end portion of the first extraction electrode and an end portion of the second extraction electrode are disposed on at least one outer side surface of the capacitor body, It is formed so as to be expressed alternately in the surface of the outer side surface . And the 1st terminal electrode and the 2nd terminal electrode are laminated | stacked alternately so that it may partially oppose through an insulator in an external side surface .

Here, in the multilayer capacitor according to the present invention, only the first terminal electrode is laminated on the first region corresponding to the end portion of the first extraction electrode on the outer side surface, and the end of the second extraction electrode is formed. Only the second terminal electrode may be stacked on the second region corresponding to the portion. Then, on the region other than the first and second regions on the outer side surface, the first terminal electrode and the second terminal electrode are laminated so as to partially or entirely face each other through an insulator. You may do it.

  The first terminal electrode, the second terminal electrode, and the insulator layer are each composed of a plurality of layers, and each of the first terminal electrode and the second terminal electrode is an upper surface or a lower surface of the capacitor body from the outer side surface side. You may have the upper surface electrode part or lower surface electrode part extended in at least one of these. The first terminal electrode in the lowermost layer among the first terminal electrodes in the plurality of layers is directly connected to the end portion of the first extraction electrode on the outer side surface, and the first terminal electrode in the upper layer than that is connected to the first terminal electrode. The terminal electrode may be electrically connected to the end portion of the first extraction electrode via the upper surface electrode portion or the lower surface electrode portion. Similarly, the second terminal electrode in the lowermost layer among the second terminal electrodes of the plurality of layers is directly conducted to the end portion of the second extraction electrode on the outer side surface, and the second terminal electrode in the upper layer is higher than that. The two terminal electrodes may be electrically connected to the end portion of the second extraction electrode via the upper surface electrode portion or the lower surface electrode portion.

  According to the multilayer capacitor of the present invention, the first terminal electrode and the second terminal electrode are alternately laminated so as to partially face each other via the insulator layer. The facing area with respect to the virtual ground plane between the second terminal electrode can be increased, and thereby the ESL in the terminal electrode portion can be greatly reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[First Embodiment]

First, the multilayer capacitor according to the first embodiment of the invention will be described. FIG. 1 shows the overall configuration of the multilayer capacitor in accordance with the present embodiment. This multilayer capacitor is used, for example, as a decoupling capacitor in a power supply circuit. This multilayer capacitor includes a capacitor body 1 having a substantially rectangular parallelepiped shape, and a positive terminal electrode 2 and a negative terminal electrode 3 formed on the first and second external side surfaces of the capacitor body 1 facing in the short direction. ing.
Here, in the present embodiment, the positive terminal electrode 2 corresponds to a specific example of the “first terminal electrode” in the present invention, and the negative terminal electrode 3 corresponds to the “second terminal electrode” in the present invention. This corresponds to a specific example.

The positive electrode side terminal electrode 2 and the negative electrode side terminal electrode 3 are alternately stacked in a direction orthogonal to the side surface so as to partially face each other as will be described later. The structure is such that they are alternately arranged in the plane. In FIG. 1, the thickness of the positive terminal electrode 2, the negative terminal electrode 3, and the insulator layer 4 is omitted to simplify the illustration. In FIG. 1, only the structure of the first external side surface is shown. However, in the structure of the second external side surface, the arrangement relationship between the positive terminal electrode 2 and the negative terminal electrode 3 in the surface is reversed. It is basically the same.
In FIG. 1, the structure is such that two positive electrode terminals 2 and two negative electrode electrodes 3 are alternately arranged on the outermost surface of one side surface. The number is not particularly limited to this, and may be larger or smaller. Further, the surface on which the terminal electrode is formed is not limited to the surface facing the short direction, and may be the surface facing the longitudinal direction. Moreover, the terminal electrode may be formed only on one side surface, and may be formed on three or more side surfaces. In this case, the shape of the internal electrode in the capacitor body 1 is also changed accordingly.

Inside the capacitor body 1, at least one set of internal electrodes is laminated with the internal positive electrode 11 and the internal negative electrode 12 as shown in FIGS. 2 and 3 as one set. The internal positive electrode 11 and the internal negative electrode 12 are laminated so as to alternately oppose each other through a dielectric layer (not shown) made of, for example, a ceramic dielectric.
Here, in the present embodiment, the internal positive electrode 11 corresponds to a specific example of the “first internal electrode” in the present invention, and the internal negative electrode 12 is a specific example of the “second internal electrode” in the present invention. It corresponds to an example.

As shown in FIG. 2, the internal positive electrode 11 has a substantially rectangular shape as a whole, and a plurality of convex positive-side extraction electrodes 21 that are electrically connected to the positive-side terminal electrode 2 are provided on two sides facing in the short direction. Is formed. The positive electrode side extraction electrodes 21 are provided in a number corresponding to the number of positive electrode side terminal electrodes 2 formed on the outermost surface of the side surface of the capacitor body 1. Similarly, the internal negative electrode 12 has a generally rectangular shape as shown in FIG. 3, and convex negative electrode side extraction electrodes 22 that are electrically connected to the negative electrode terminal electrode 3 are provided on two sides facing in the short direction. A plurality are formed. The negative electrode side extraction electrodes 22 are provided in a number corresponding to the number of the negative electrode side terminal electrodes 3 formed on the outermost surface. The positive electrode-side extraction electrode 21 and the negative electrode-side extraction electrode 22 are formed at positions where they are alternately arranged in the horizontal plane when viewed from above and below with the internal positive electrode 11 and the internal negative electrode 12 facing each other. Has been.
Here, in the present embodiment, the positive electrode side extraction electrode 21 corresponds to a specific example of the “first extraction electrode” in the present invention, and the negative electrode side extraction electrode 22 corresponds to the “second extraction electrode” in the present invention. This corresponds to a specific example.

  The end portion of the positive electrode side extraction electrode 21 and the end portion of the negative electrode side extraction electrode 22 correspond to the arrangement of the outermost positive electrode side terminal electrode 2 and the negative electrode side terminal electrode 3 in the first and second portions of the capacitor body 1. It is formed so that it may express alternately on the outer side surface. The end of the positive electrode-side extraction electrode 21 is exposed to the first and second external side surfaces of the capacitor body 1, so that it is electrically connected to the positive electrode-side terminal electrode 2. Similarly, the negative electrode-side extraction electrode 22 is electrically connected to the negative electrode-side terminal electrode 3 by exposing the end portion to the first and second external side surfaces of the capacitor body 1.

  In the capacitor body 1, in the internal positive electrode 11, a current i flows inward from the end side of the positive electrode 21 as shown in FIG. 2. On the other hand, in the internal negative electrode 12, conversely, as shown in FIG. 3, a current i flows from the inside to the end 22 side of the negative electrode. In this manner, the direction in which the current i flows is reversed between the internal positive electrode 11 and the internal negative electrode 12. As a result, the direction of the magnetic field generated by the current i in the internal positive electrode 11 and the direction of the magnetic field generated by the current i in the internal negative electrode 12 are reversed, and these magnetic fields cancel each other. Thereby, the ESL at the internal electrode in the capacitor body 1 is reduced.

  Next, referring to FIGS. 4A to 4E, the structure of the terminal electrode portion including the positive electrode terminal electrode 2, the negative electrode terminal electrode 3, and the insulator layer 4 will be described in detail together with the formation process. explain. In the following, the structure of the capacitor body 1 on the first external side surface will be described as an example, but the structure of the second external side surface and the formation process thereof are substantially the same.

  FIG. 4A shows the first external side surface of the capacitor body 1 before the terminal electrode is formed. As shown in FIG. 4A, the end portion of the positive electrode side extraction electrode 21 and the end portion of the negative electrode side extraction electrode 22 are formed so as to alternately appear in the first and second planes. . FIG. 4A shows an example in which two sets of internal electrodes are stacked. That is, in this example, two internal positive electrodes 11 and two internal negative electrodes 12 are alternately stacked.

  First, as a first step, the negative terminal electrode 3 is formed on the first external side surface by a printing method or the like (FIG. 4B). In this case, the negative terminal electrode 3 is not formed in the first region corresponding to the end of the positive electrode 21 so that the negative terminal electrode 3 does not conduct to the positive electrode 21. Further, the negative electrode terminal electrode 3 is formed on a region including at least the second region corresponding to the end of the negative electrode lead electrode 22 so that the negative electrode terminal electrode 3 is directly conducted to the negative electrode electrode 22. . Preferably, as shown in FIG. 4B, the negative terminal electrode 3 is formed over the entire region excluding the first region.

  Next, as a second step, the first insulator layer 4A is stacked by a printing method or the like (FIG. 4C). The first insulator layer 4A is for preventing the positive terminal electrode 2 and the negative terminal electrode 3 from conducting. As shown in FIG. 4C, the first insulator layer 4A includes a first region corresponding to the end portion of the positive electrode side extraction electrode 21 and a second region corresponding to the end portion of the negative electrode side extraction electrode 22. It is formed in a region between the regions.

  Next, as a third step, the positive electrode terminal electrode 2 is stacked by a printing method or the like (FIG. 4D). In this case, the second region corresponding to the end portion of the negative electrode side extraction electrode 22 has a positive electrode side so that the positive electrode side terminal electrode 2 does not conduct to the negative electrode side extraction electrode 22 via the lower layer negative electrode side terminal electrode 3. The terminal electrode 2 is not formed. Further, the positive terminal electrode 2 is formed on a region including at least a first region corresponding to the end of the positive electrode 21 so that the positive terminal electrode 2 is electrically connected to the positive electrode 21. Preferably, as shown in FIG. 4D, the positive electrode terminal 2 is formed over the entire region except for the second region.

  Next, as a fourth step, the second insulator layer 4B is stacked by a printing method or the like (FIG. 4E). The second insulator layer 4B is formed in a region excluding the first region corresponding to the end portion of the positive electrode side extraction electrode 21 and the second region corresponding to the end portion of the negative electrode side extraction electrode 22.

  In the above steps, the order of the step of forming the negative electrode terminal electrode 3 and the step of forming the positive electrode terminal electrode 2 may be reversed. 4B to 4E may be performed a plurality of times to form a multilayered structure.

  Finally, the positive terminal electrode 2 and the negative terminal electrode 3 are alternately arranged in the plane through the second insulator layer 4B on the outermost surface of the first outer side surface by the above steps. It becomes a structure like this. Further, only the positive terminal electrode 2 is laminated in a direction perpendicular to the side surface on the first region corresponding to the end portion of the positive electrode 21 on the first outer side surface. Further, only the negative electrode terminal electrode 3 is laminated in a direction perpendicular to the side surface on the second region corresponding to the end of the negative electrode extraction electrode 22. In addition, on the region other than the first and second regions on the first external side surface, the positive electrode terminal electrode 2 and the negative electrode terminal electrode 3 are partially or entirely disposed through the first insulator layer 4A. Therefore, they are laminated so as to face each other.

FIG. 5 is a partially enlarged view of a horizontal cross section of the terminal electrode portion after the above steps. In order to obtain a larger ESL reduction effect in the terminal electrode portion, it is necessary to shorten the distance of each terminal electrode to the virtual ground plane GND and increase the facing area of each terminal electrode. In the multilayer capacitor in accordance with the present embodiment, the positive electrode terminal electrode 2 and the negative electrode terminal electrode 3 are alternately laminated so as to partially face each other through the first insulator layer 4A through the above steps. Thereby, the opposing area with respect to the virtual ground plane GND between the positive electrode terminal electrode 2 and the negative electrode terminal electrode 3 can be enlarged. Moreover, since the space | interval between the positive electrode terminal electrode 2 and the negative electrode terminal electrode 3 is prescribed | regulated by the thickness of 4 A of 1st insulator layers, the distance of each terminal electrode with respect to the virtual ground surface GND can be shortened. Thereby, the magnetic field generated in the positive terminal electrode 2 and the magnetic field generated in the negative terminal electrode 3 sufficiently cancel each other, and ESL in the terminal electrode portion can be greatly reduced.
[Second Embodiment]

  Next, a multilayer capacitor according to a second embodiment of the present invention will be described. Note that components that are substantially the same as those of the multilayer capacitor according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.

FIG. 6 shows a configuration example of the multilayer capacitor according to the present embodiment. In this multilayer capacitor, the structure of the capacitor body 1 is the same as that of the multilayer capacitor according to the first embodiment (FIG. 1), but the structure of the terminal electrode portion is different. In this multilayer capacitor, the positive electrode terminal electrode 2, the negative electrode terminal electrode 3, and the insulator layer 4 are each composed of a plurality of layers as will be described later. Further, the positive electrode terminal electrode 2 of each layer has an upper electrode portion 31 and a lower electrode portion extending from the outer side surface to the upper surface and the lower surface of the capacitor body 1. Similarly, the negative electrode terminal electrode 3 of each layer has an upper electrode portion 32 and a lower electrode portion extending from the outer side surface to the upper surface and the lower surface of the capacitor body 1.
6 shows only the upper surface electrode portions 31 and 32, the structure of the lower surface electrode portion is basically the same. In addition, the structure which has only any one among an upper surface electrode part and a lower surface electrode part may be sufficient.

  Next, FIG. 7 (A) to FIG. 7 (C) and FIG. 8 (A) to FIG. 8 (D) and FIG. 9 (A) to FIG. 9 (C) and FIG. 10 (A) to FIG. ), The structure of the terminal electrode portion in the present embodiment will be described in detail together with the formation process thereof. In the following, the structure of the capacitor body 1 on the first external side surface will be described as an example, but the structure of the second external side surface and the formation process thereof are substantially the same. 7A to FIG. 7C and FIG. 8A to FIG. 8D are process diagrams viewed from the first external side surface direction, and FIG. 9A to FIG. FIG. 10C and FIG. 10A to FIG. 10D are process diagrams in which the first external side surface portion is viewed from the perspective direction. In these drawings, the thickness of each layer is omitted to simplify the illustration.

  First, as the first step, the first negative electrode terminal 3A as the lowest layer is formed on the first external side surface of the capacitor body 1 by a printing method or the like (FIGS. 7A and 9A). ). In this case, the negative terminal electrode 3 </ b> A is not formed in the first region corresponding to the end of the positive electrode 21 so that the negative terminal electrode 3 </ b> A does not conduct to the positive electrode 21. Further, the negative electrode terminal electrode 3A is formed on a region including at least the second region corresponding to the end of the negative electrode lead electrode 22 so that the negative electrode terminal electrode 3A is directly connected to the negative electrode lead electrode 22. . In addition, upper surface electrode portion 32A and lower surface electrode portion of the first layer are formed so as to extend from the second region to the upper surface and the lower surface. Preferably, as shown in FIGS. 7A and 9A, the negative terminal electrode 3A is formed over the entire region except the first region. However, in the side surface portion, the connecting portion between the upper electrode portion 32A and the lower surface electrode portion of the first layer is formed in a convex shape as shown in the figure, and the portions other than the connecting portion are formed in a concave shape. This is to prevent the negative electrode terminal electrode 3A in the first layer from conducting to the upper surface electrode portions 31A and 31B and the lower surface electrode portions on the positive electrode side terminal electrodes 2A and 2B, which are higher than the first layer.

  Next, as a second step, the first insulator layer 4A is stacked and formed by a printing method or the like (FIGS. 7B and 9B). The first insulator layer 4A is for preventing electrical conduction between the first positive electrode terminal electrode 2A to be formed next and the lower negative electrode terminal electrode 3A. As shown in FIGS. 7B and 9B, the first insulator layer 4A is formed on the entire side surface region excluding the first region corresponding to the end portion of the positive electrode-side extraction electrode 21.

  Next, as a third step, the positive electrode terminal electrode 2A of the first layer is stacked by a printing method or the like (FIGS. 7C and 9C). In this case, the positive terminal electrode 2A is formed on substantially the entire region of the side surface. Also, the first-layer upper surface electrode portion 31A and the lower surface electrode portion are formed so as to extend from the first region corresponding to the end portion of the positive electrode side extraction electrode 21 to the upper surface and the lower surface. However, in the side surface portion, the connection portion between the upper surface electrode portion 31A and the lower surface electrode portion of the first layer is formed in a convex shape as shown in the figure, and the portions other than the connection portion are formed in a concave shape. This is to prevent the positive electrode terminal electrode 2A in the first layer from conducting to the upper electrode portion 32B and the lower electrode portion on the negative electrode terminal electrode 3B, which is an upper layer.

  Next, as a fourth step, the second insulator layer 4B is stacked by a printing method or the like (FIGS. 8A and 10A). The second insulator layer 4B is for preventing the second negative electrode terminal electrode 3B to be formed next from conducting to the lower positive electrode terminal electrode 2A. As shown in FIGS. 8A and 10A, the second insulator layer 4B is formed over the entire side region.

  Next, as a fifth step, the second negative electrode terminal electrode 3B is stacked by a printing method or the like (FIGS. 8B and 10B). In this case, the negative electrode terminal electrode 3B is formed on substantially the entire side surface portion. Further, the second-layer upper surface electrode portion 32B and the lower surface electrode portion are formed so as to extend from the second region corresponding to the end portion of the negative electrode side extraction electrode 22 to the upper surface and the lower surface. However, in the side surface portion, the connecting portion between the upper electrode portion 32B and the lower surface electrode portion in the second layer is formed in a convex shape as shown in the figure, and further, the portions other than the connecting portion are formed in a concave shape. This is to prevent the second-layer negative electrode terminal electrode 3B from conducting to the upper electrode portion 31B and the lower electrode portion on the positive electrode terminal electrode 2B, which is an upper layer.

  Next, as a sixth step, the third insulator layer 4C is stacked by a printing method or the like (FIGS. 8C and 10C). The third insulator layer 4 </ b> C is formed in the entire region excluding the second region corresponding to the end portion of the negative electrode side extraction electrode 22.

  Next, as a seventh step, the second positive electrode terminal electrode 2B is stacked by a printing method or the like (FIGS. 8D and 10D). In this case, the positive terminal electrode 2 </ b> B is formed only in the first region corresponding to the end of the positive electrode 21. Also, the second-layer upper surface electrode portion 31B and the lower surface electrode portion are formed so as to extend from the first region to the upper surface and the lower surface.

  In the above steps, the order of the step of forming the negative electrode terminal electrode 3 and the step of forming the positive electrode terminal electrode 2 may be reversed.

  Finally, the positive electrode terminal electrode 2A in the lowermost layer among the multiple layers of positive electrode terminal electrodes 2 is directly conducted to the end portion of the positive electrode extraction electrode 21 on the first outer side surface by the above steps. The positive electrode terminal electrode 2B in the upper layer is then conducted to the end of the positive electrode extraction electrode 21 through the upper surface electrode portions 31A and 31B and the lower surface electrode portion. Also, the negative electrode terminal electrode 3A in the lowest layer among the negative electrode terminals 3 of the plurality of layers is directly conducted to the end portion of the negative electrode lead electrode 22 on the first outer side surface and is in an upper layer than that. The negative electrode terminal electrode 3B is conducted to the end of the negative electrode lead electrode 22 through the upper surface electrode portions 32A and 32B and the lower surface electrode portion.

According to the multilayer capacitor in accordance with the present embodiment, the positive electrode terminal electrode 2 and the negative electrode terminal electrode 3 are composed of a plurality of layers with the insulator layer 4 interposed therebetween, and the upper terminal electrodes 31 and 32 are formed as upper terminal electrodes. Since it is connected to the lowermost terminal electrode through the lower surface electrode portion and indirectly connected to the positive electrode side extraction electrode 21 and the negative electrode side extraction electrode 22, the positive electrode side terminal electrode 2 and the negative electrode on the side surface portion The area facing the side terminal electrode 3 can be further increased as compared with the multilayer capacitor according to the first embodiment. Thereby, ESL in a terminal electrode part can be reduced more significantly.
[Third Embodiment]

Next, a multilayer capacitor according to a third embodiment of the present invention will be described.
FIG. 11 shows the overall configuration of the multilayer capacitor in accordance with the present embodiment. This multilayer capacitor includes a capacitor body 1A having a substantially rectangular parallelepiped shape as shown in FIG. The multilayer capacitor further includes a positive terminal electrode 61, a negative terminal electrode 62, a first insulator layer 63A, and a second insulator layer 63B stacked on the outer peripheral surface of the capacitor body 1A. The positive terminal electrode 61, the negative terminal electrode 62, the first insulator layer 63A, and the second insulator layer 63B are alternately arranged in a direction orthogonal to the outer peripheral surface so as to partially face each other as will be described later. Are stacked. Here, in the present embodiment, the positive terminal electrode 61 corresponds to a specific example of the “first terminal electrode” in the present invention, and the negative terminal electrode 62 corresponds to the “second terminal electrode” in the present invention. This corresponds to a specific example.
The first insulator layer 63A is not shown in FIG. 1 because it is formed in the lower layer. In FIG. 1, the thickness of the positive terminal electrode 61, the negative terminal electrode 62, and the second insulator layer 63B is omitted to simplify the illustration.

  On the outermost surface of the multilayer capacitor, a positive electrode terminal electrode 61 is formed so as to be exposed on the first outer side surface portion in the longitudinal direction of the capacitor body 1A. Further, on the outermost surface, the negative electrode terminal electrode 62 is formed so as to be exposed to the second external side surface portion facing the first external side surface. Further, on the outermost surface, the second insulator layer 63B is formed so as to be exposed in a region between the positive terminal electrode 61 and the negative terminal electrode 62.

Inside the capacitor body 1A, as shown in FIG. 12, a plurality of sets of internal electrodes, each of which includes an internal positive electrode 51 and an internal negative electrode 52, are interposed via a dielectric layer 53 made of, for example, a ceramic dielectric. Are stacked. The internal positive electrode 51 and the internal negative electrode 52 have a substantially rectangular shape and are stacked so as to alternately face each other in the stacking direction. One end of the internal positive electrode 51 is exposed to the first external side surface of the capacitor body 1A and is electrically connected to the positive terminal electrode 61. One end of the internal negative electrode 52 is exposed to the second external side surface of the capacitor body 1A and is electrically connected to the negative terminal electrode 62.
Here, in the present embodiment, the internal positive electrode 51 corresponds to a specific example of the “first internal electrode” in the present invention, and the internal negative electrode 52 is a specific example of the “second internal electrode” in the present invention. It corresponds to an example.

  Next, with reference to the drawings, the structure of the terminal electrode portion on the outer peripheral surface of the capacitor body 1A will be described in detail together with the formation process. 13A, FIG. 14A, FIG. 15A, and FIG. 16A are process diagrams viewed from the top surface, and FIG. 13B, FIG. 14B, and FIG. FIGS. 16B and 16B are process diagrams viewed from a vertical cross section (cross section taken along line AA in FIGS. 13A, 14A, 15A, and 16A). . For convenience of explanation, the thickness of each layer is exaggerated with respect to the thickness of the capacitor body 1A in each process drawing.

  First, as a first step, the positive terminal electrode 61 is formed on the outer peripheral surface of the capacitor body 1A by a printing method or the like (FIGS. 13A and 13B). In this case, a region other than the second external side surface portion (the negative side terminal electrode 62 is exposed so that the positive side terminal electrode 61 does not conduct to one end of the internal negative electrode 52 exposed on the second external side surface. In a region other than the region to be formed).

  Next, as a second step, the first insulator layer 63A is stacked by a printing method or the like (FIGS. 14A and 14B). The first insulator layer 63A is for preventing the negative electrode terminal electrode 62 to be formed next and the lower positive electrode terminal electrode 61 from conducting. The first insulator layer 63A includes a first outer side surface region (region where the positive terminal electrode 61 is exposed) and a second outer side surface region (region where the negative terminal electrode 62 is exposed). Form the entire region between.

  Next, as a third step, the negative terminal electrode 62 is formed by a printing method or the like (FIGS. 15A and 15B). In this case, the negative electrode terminal electrode 62 is formed in a region other than the first external side surface portion (a region other than the region where the positive electrode terminal electrode 61 is exposed) so that the negative electrode terminal electrode 62 does not conduct to the positive electrode terminal electrode 61.

  Next, as a fourth step, the second insulator layer 63B is stacked by a printing method or the like (FIGS. 16A and 16B). The second insulator layer 63B includes a first external side surface region (region where the positive terminal electrode 61 is exposed) and a second external side surface region (region where the negative terminal electrode 62 is exposed). Form the entire region between.

  In the above steps, the order of the step of forming the positive electrode terminal electrode 61 and the step of forming the negative electrode terminal electrode 62 may be reversed. Further, the above-described steps may be performed a plurality of times to form a multilayered structure.

  By the above steps, finally, only the positive terminal electrode 61 is laminated on the first region including the first outer side surface on the outer peripheral surface of the capacitor body 1A, and the second outer side surface is included. Only the negative terminal electrode 62 is laminated on the second region. Further, on the outer peripheral surface of the capacitor body 1A, the positive terminal electrode 61 and the negative terminal electrode 62 are entirely disposed on the region other than the first and second regions through the first insulator layer 63A. It will be laminated so as to face each other.

  According to the multilayer capacitor in accordance with the present embodiment, the positive terminal electrode 61 and the negative terminal electrode 62 are entirely connected via the first insulator layer 63A on the region other than the first and second regions. Thus, the ESL at the terminal electrode portion in the multilayer capacitor having a general structure can be greatly reduced.

  In addition, this invention is not limited to said each embodiment, A various deformation | transformation implementation is possible. For example, in each of the above embodiments, an example in which two sets of internal electrodes are stacked, that is, a configuration example in which two internal positive electrodes and two internal negative electrodes are alternately stacked has been shown. The number of stacked electrodes may be larger than this.

1 is an external view showing the overall configuration of the multilayer capacitor in accordance with a first embodiment of the present invention. It is a top view which shows the structure of the internal positive electrode in the multilayer capacitor which concerns on the 1st Embodiment of this invention. It is a top view which shows the structure of the internal negative electrode in the multilayer capacitor which concerns on the 1st Embodiment of this invention. It is process drawing for demonstrating the formation process of the terminal electrode part in the multilayer capacitor which concerns on the 1st Embodiment of this invention. It is sectional drawing of the horizontal direction of a terminal electrode part. It is an external view which shows the whole structure of the multilayer capacitor which concerns on the 2nd Embodiment of this invention. It is process drawing seen from the side surface for demonstrating the formation process of the terminal electrode part in the multilayer capacitor which concerns on the 2nd Embodiment of this invention. FIG. 8 is a process diagram following FIG. 7. It is process drawing seen from the perspective direction corresponding to FIG. It is process drawing seen from the perspective direction corresponding to FIG. It is an external view which shows the whole structure of the multilayer capacitor which concerns on the 3rd Embodiment of this invention. It is sectional drawing of the lamination direction of the capacitor | condenser main body in the multilayer capacitor which concerns on the 3rd Embodiment of this invention. It is a 1st process drawing for demonstrating the formation process of the terminal electrode part in the multilayer capacitor which concerns on the 3rd Embodiment of this invention, (A) is a process drawing seen from the upper surface direction, (B) These are process drawings seen from a vertical cross section. FIGS. 13A and 13B are second process diagrams following FIG. 13A, FIG. 13A is a second process diagram viewed from the top surface direction, and FIG. 13B is a second process diagram viewed from the vertical cross section. FIG. 14A and 14B are third process diagrams, FIG. 14A is a third process diagram viewed from the top surface direction, and FIG. 14B is a third process diagram viewed from the vertical cross section. FIG. 15A and 15B are fourth process diagrams, FIG. 15A is a fourth process diagram seen from the top surface direction, and FIG. 15B is a fourth process diagram seen from the vertical cross section. FIG. It is an external view which shows the whole structure of the conventional multilayer capacitor. It is sectional drawing of the lamination direction of the conventional multilayer capacitor. It is an external view which shows the basic composition of the conventional low ESL capacitor | condenser. It is a top view which shows the structure of one internal electrode in the conventional low ESL capacitor | condenser. It is a top view which shows the structure of the other internal electrode in the conventional low ESL capacitor | condenser. It is a figure which shows the structure of the conventional low ESL capacitor | condenser, (A) is the figure seen from the upper surface direction, (B) is the figure seen from the side surface direction. It is a figure for demonstrating the problem in the conventional low ESL capacitor | condenser.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Capacitor body, 2 ... Positive electrode side terminal electrode, 3 ... Negative electrode side terminal electrode, 4 ... Insulator layer, 11 ... Internal positive electrode, 12 ... Internal negative electrode, 21 ... Positive electrode side extraction electrode, 22 ... Negative electrode side extraction electrode .

Claims (3)

A substantially rectangular parallelepiped capacitor body having a dielectric layer and at least one pair of first internal electrode and second internal electrode stacked alternately via the dielectric layer;
A first terminal electrode of at least one layer provided outside the capacitor body and electrically connected to the first internal electrode;
A second terminal electrode of at least one layer provided outside the capacitor body and connected to the second internal electrode;
Comprising at least one insulator layer that insulates the first terminal electrode and the second terminal electrode;
The first internal electrode is formed with a first extraction electrode that is electrically connected to the first terminal electrode, and the second internal electrode is electrically connected to the second terminal electrode. A lead electrode is formed,
The end portion of the first extraction electrode and the end portion of the second extraction electrode are formed so as to alternately appear within the surface of the external side surface on at least one external side surface of the capacitor body,
The multilayer capacitor, wherein the first terminal electrode and the second terminal electrode are alternately laminated so as to partially face each other via the insulator layer on the outer side surface. Only the first terminal electrode is stacked on the first region corresponding to the end portion of the first extraction electrode on the outer side surface, and the second region corresponding to the end portion of the second extraction electrode. Only the second terminal electrode is laminated on the region of
The first terminal electrode and the second terminal electrode are partially or entirely opposed to each other through the insulator on a region other than the first and second regions on the outer side surface. The multilayer capacitor according to claim 1 , wherein the multilayer capacitor is laminated. Each of the first terminal electrode, the second terminal electrode and the insulator layer is composed of a plurality of layers,
Each of the first terminal electrode and the second terminal electrode has an upper surface electrode portion or a lower surface electrode portion extending from the outer side surface side to at least one of the upper surface or the lower surface of the capacitor body,
The first terminal electrode in the lowermost layer among the first terminal electrodes of the plurality of layers is directly connected to the end portion of the first extraction electrode on the outer side surface, and the first terminal electrode in the upper layer than the first terminal electrode. The terminal electrode is conducted to the end of the first extraction electrode via the upper surface electrode portion or the lower surface electrode portion,
The second terminal electrode in the lowermost layer among the second terminal electrodes of the plurality of layers is directly connected to the end portion of the second extraction electrode on the outer side surface, and the second terminal electrode in the upper layer than the second terminal electrode. The multilayer capacitor according to claim 1 , wherein the terminal electrode is electrically connected to an end portion of the second extraction electrode via the upper surface electrode portion or the lower surface electrode portion.

Images