JPH07249541A - Composite ceramic capacitor - Google Patents
Composite ceramic capacitorInfo
- Publication number
- JPH07249541A JPH07249541A JP6040951A JP4095194A JPH07249541A JP H07249541 A JPH07249541 A JP H07249541A JP 6040951 A JP6040951 A JP 6040951A JP 4095194 A JP4095194 A JP 4095194A JP H07249541 A JPH07249541 A JP H07249541A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic capacitor
- composite ceramic
- stack
- electrodes
- external electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Ceramic Capacitors (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、複数の積層セラミック
コンデンサを並列に組立てた複合セラミックコンデンサ
に関する。更に詳しくはＤＣ−ＤＣコンバータ用のリッ
プルフィルタ、ＡＣライン過渡フィルタに利用され、又
はスイッチ、リレー、ソリッドステートリレー等におけ
る誘電負荷を抑えるスナバコンデンサ等に利用される複
合セラミックコンデンサに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite ceramic capacitor in which a plurality of laminated ceramic capacitors are assembled in parallel. More specifically, the present invention relates to a composite ceramic capacitor used as a ripple filter for a DC-DC converter, an AC line transient filter, or a snubber capacitor for suppressing a dielectric load in a switch, a relay, a solid state relay or the like.
【０００２】[0002]
【従来の技術】従来、複数の同形同大の積層セラミック
コンデンサをその両端の外部電極を同一方向に揃えて積
重ね、外部電極同士を導通するように一対のリードフレ
ームを外部電極に接着することにより構成される複合セ
ラミックコンデンサが開示されている（例えば、特開平
３−２７２１２２）。この複合セラミックコンデンサに
よれば、小型で高い共振状態を実現し、かつ２０〜５０
μＦの高い静電容量を得ることができる。しかし、この
複合セラミックコンデンサは、市販の積層セラミックコ
ンデンサを積重ねるに過ぎないため、安価に製作できる
けれども、その反面低い直列インダクタンスや高い自己
共振周波数を示さない欠点があった。2. Description of the Related Art Conventionally, a plurality of monolithic ceramic capacitors of the same shape and size are stacked with the external electrodes on both ends aligned in the same direction, and a pair of lead frames are bonded to the external electrodes so that the external electrodes are electrically connected to each other. Is disclosed (for example, Japanese Patent Laid-Open No. 3-272122). According to this composite ceramic capacitor, a small size and a high resonance state are realized, and 20 to 50
A high capacitance of μF can be obtained. However, this composite ceramic capacitor can be manufactured at low cost because it is merely a stack of commercially available monolithic ceramic capacitors, but on the other hand, it has the drawback of not exhibiting low series inductance and high self-resonant frequency.
【０００３】本出願人は、これらの点を改良した複合セ
ラミックコンデンサを特許出願した（特願平５−１９９
３９４）。この複合セラミックコンデンサは一対のリー
ドフレームを手指を組合せたような（interdigitated）
形状にして外部電極に接着したものである。この複合セ
ラミックコンデンサによれば、量産可能な積層セラミッ
クコンデンサを用いて安価で、低い直列インダクタンス
と高い自己共振周波数を示すことができ、しかも小型で
表面実装可能であって、大容量値が得られる特長があ
る。The applicant of the present invention has filed a patent application for a composite ceramic capacitor improved in these points (Japanese Patent Application No. 5-199).
394). This composite ceramic capacitor is an interdigitated combination of a pair of lead frames.
It is shaped and adhered to the external electrode. According to this composite ceramic capacitor, it is possible to produce a monolithic ceramic capacitor that can be mass-produced at a low cost, exhibit a low series inductance and a high self-resonant frequency, can be surface-mounted in a small size, and obtain a large capacitance value. There are features.
【０００４】[0004]
【発明が解決しようとする課題】しかし、上記複合セラ
ミックコンデンサは「相互インダクタンス」についての
議論が十分になされていなかった。この相互インダクタ
ンスは低インピーダンスのフィルタコンデンサの構成と
作用に重要である。この種の積層チップコンデンサは外
部電極と内部電極とからなる導体と同サイズの導体に近
似できる。図１２に示すように、特開平３−２７２１２
２号公報に示される複合セラミックコンデンサ１が一対
のリードフレーム１ａ及び１ｂを介して印刷回路用銅張
積層基板２に実装された場合に、基板表面の線路３、リ
ードフレーム１ａ、外部電極１ｃ、内部電極（図示せ
ず）、外部電極１ｄ、リードフレーム１ｂ、線路４及び
スルーホール５を通って基板裏面のアース用線路６にリ
ップル電流が流れ、電流ループＸが形成される。これに
よりコンデンサ１はソレノイドとして作用し、フレミン
グの左手の法則に基づき電流ループＸによりコンデンサ
１に磁力線Ｙを生じる。However, the "mutual inductance" of the above composite ceramic capacitor has not been sufficiently discussed. This mutual inductance is important for the construction and operation of low impedance filter capacitors. This type of multilayer chip capacitor can be approximated to a conductor having the same size as the conductor composed of the external electrode and the internal electrode. As shown in FIG. 12, JP-A-3-27212
When the composite ceramic capacitor 1 shown in Japanese Patent Publication No. 2 is mounted on a copper clad laminated board 2 for a printed circuit via a pair of lead frames 1a and 1b, a line 3 on the surface of the board, a lead frame 1a, an external electrode 1c, A ripple current flows through the internal electrode (not shown), the external electrode 1d, the lead frame 1b, the line 4 and the through hole 5 to the earth line 6 on the back surface of the substrate, forming a current loop X. As a result, the capacitor 1 acts as a solenoid, and a magnetic field line Y is generated in the capacitor 1 by the current loop X based on Fleming's left-hand rule.
【０００５】また図１３に示すように、複合セラミック
コンデンサ１の外部電極１ｃ及び１ｄが基板２の表面に
形成された一対の線路７ａ及び７ｂにそれぞれリードフ
レーム８ａ及び８ｂを介して実装された場合で、図１４
に示すように電源のバイパス用に回路構成された場合に
は、入力側でコンデンサ１を通ってバイパスされた高周
波リップル電流ｘ1が流れ、出力側で誘導されたリップ
ル電流ｘ2が流れる。この結果、これらの電流ｘ1及びｘ
2により、図１３に示すようにコンデンサ１の入出力側
でそれぞれ磁力線ｙ1及びｙ2を生じる。図１４において
図１３と同一符号は同一構成部品を表す。図１２及び図
１３に示される複合セラミックコンデンサ１の直列自己
インダクタンス（等価直列インダクタンス＝ＥＳＬ）は
次の一般式で表される。Further, as shown in FIG. 13, when the external electrodes 1c and 1d of the composite ceramic capacitor 1 are mounted on a pair of lines 7a and 7b formed on the surface of the substrate 2 via lead frames 8a and 8b, respectively. Then, in FIG.
When the circuit is configured for bypassing the power supply as shown in (1), a high frequency ripple current x 1 bypassed through the capacitor 1 on the input side flows, and a ripple current x 2 induced on the output side flows. As a result, these currents x 1 and x
2 , the magnetic lines of force y 1 and y 2 are generated on the input and output sides of the capacitor 1 as shown in FIG. 14, the same reference numerals as those in FIG. 13 represent the same components. The series self-inductance (equivalent series inductance = ESL) of the composite ceramic capacitor 1 shown in FIGS. 12 and 13 is represented by the following general formula.
【０００６】[0006]
【数１】 [Equation 1]
【０００７】ただし、μ0は真空の透磁率、Ｌは一対の
リードフレームの間隔、Ｂは線路間の間隔、ｌは基板と
コンデンサとの隙間、ｈはコンデンサの全体の厚さ及び
ｗはコンデンサの幅である。従来の図１２又は図１３に
示される複合セラミックコンデンサは、上記式（１）の
Ｂ又はｌが比較的大きく、直列自己インダクタンスを小
さくできなかった。Where μ 0 is the magnetic permeability of the vacuum, L is the distance between the pair of lead frames, B is the distance between the lines, l is the gap between the substrate and the capacitor, h is the total thickness of the capacitor, and w is the capacitor. Is the width of. In the conventional composite ceramic capacitor shown in FIG. 12 or FIG. 13, B or l in the above formula (1) is relatively large, and the series self-inductance cannot be reduced.
【０００８】本発明の目的は、量産可能な積層セラミッ
クコンデンサを用いて安価で、低い直列自己インダクタ
ンスと高い自己共振周波数を示すことができる複合セラ
ミックコンデンサを提供することにある。また本発明の
別の目的は、小型で表面実装可能であって、大容量値が
得られる複合セラミックコンデンサを提供することにあ
る。An object of the present invention is to provide a composite ceramic capacitor which can be manufactured inexpensively and which can exhibit a low series self-inductance and a high self-resonance frequency by using a mass-produced monolithic ceramic capacitor. Another object of the present invention is to provide a composite ceramic capacitor that is small in size, surface mountable, and has a large capacitance value.
【０００９】[0009]
【課題を解決するための手段】図１及び図２に示すよう
に、本発明は、セラミック誘電体１０ａと内部電極１０
ｂが交互に積層して焼成され、相対向するチップ両端に
内部電極１０ｂが交互に現れたベアチップ１０ｃと、こ
のベアチップ１０ｃの両端に内部電極１０ｂに導通する
ように焼付けられた一対の第１及び第２外部電極１０
ｄ，１０ｅとを備えた積層セラミックコンデンサ１０を
第１及び第２外部電極１０ｄ，１０ｅをそれぞれ同一方
向に揃えて複数積重ねて積重ね体１１が形成され、この
積重ね体１１の外部電極同士を導通するように外部電極
１０ｄ，１０ｅに一対のリードフレーム１２，１３がそ
れぞれ接着された複合セラミックコンデンサ１５の改良
である。As shown in FIGS. 1 and 2, the present invention provides a ceramic dielectric 10a and an internal electrode 10.
b are alternately laminated and fired, and the bare chips 10c in which the internal electrodes 10b appear alternately at both ends of the chips facing each other, and the pair of first and second burned chips which are electrically conductive to the internal electrodes 10b at both ends of the bare chip 10c. Second external electrode 10
A plurality of stacked ceramic capacitors 10 each including d and 10e are stacked with the first and second external electrodes 10d and 10e aligned in the same direction to form a stacked body 11, and the external electrodes of the stacked body 11 are electrically connected to each other. This is an improvement of the composite ceramic capacitor 15 in which the pair of lead frames 12 and 13 are bonded to the external electrodes 10d and 10e, respectively.
【００１０】このリードフレーム１２は第１水平部１６
と第１垂直部１８とを備え、リードフレーム１３は第２
水平部１７と第２垂直部１９とを備える。第１及び第２
水平部１６，１７は互いに絶縁されて第１又は第２外部
電極１０ｄ，１０ｅが全面に形成されない積重ね体１１
の底面に沿ってかつこの底面の両側に突出して配設され
る。第１垂直部１８は第１水平部１６に、また第２垂直
部１９は第２水平部１７にそれぞれ垂直に設けられ、第
１垂直部１８は第１外部電極１０ｄに、また第２垂直部
１９は第２外部電極１０ｅにそれぞれ接続される。そし
て第１水平部１６は第２外部電極１０ｅに絶縁され、第
２水平部１７は第１外部電極１０ｄに絶縁されるように
それぞれ設けられる。また第１垂直部１８は第２水平部
１７に絶縁して設けられ、第２垂直部１９は第１水平部
１６に絶縁して設けられる。The lead frame 12 has a first horizontal portion 16
And the first vertical portion 18, and the lead frame 13 has a second
The horizontal part 17 and the second vertical part 19 are provided. First and second
The horizontal portions 16 and 17 are insulated from each other and the first or second external electrode 10d or 10e is not formed on the entire surface of the stack 11
Along the bottom surface of the base plate and on both sides of the bottom surface. The first vertical portion 18 is provided vertically to the first horizontal portion 16, the second vertical portion 19 is provided vertically to the second horizontal portion 17, and the first vertical portion 18 is provided to the first external electrode 10d and the second vertical portion. 19 are connected to the second external electrodes 10e, respectively. The first horizontal portion 16 is provided so as to be insulated from the second external electrode 10e, and the second horizontal portion 17 is provided so as to be insulated from the first external electrode 10d. The first vertical portion 18 is provided so as to be insulated from the second horizontal portion 17, and the second vertical portion 19 is provided so as to be insulated from the first horizontal portion 16.
【００１１】[0011]
【作用】図２に示すように、積重ね体１１とリードフレ
ーム１２，１３とをはんだ付けにより一体化して複合セ
ラミックコンデンサ１５を作製した後、リードフレーム
１２，１３の第１及び第２水平部１６,１７を基板２１
上に設けられた一対の線路２２及び２３にそれぞれはん
だ付けする。水平部１６，１７が線路２２，２３に密着
し、前記式（１）のｌ（基板とコンデンサとの隙間）及
びＢ（線路間の間隔）は極めて小さくなるため、複合セ
ラミックコンデンサ１５の直列インダクタンスは小さく
なる。As shown in FIG. 2, the stack 11 and the lead frames 12 and 13 are integrated by soldering to form a composite ceramic capacitor 15, and then the first and second horizontal portions 16 of the lead frames 12 and 13 are formed. Substrate 21
Solder to the pair of lines 22 and 23 provided above. Since the horizontal parts 16 and 17 are in close contact with the lines 22 and 23 and l (gap between the substrate and the capacitor) and B (gap between the lines) in the formula (1) are extremely small, the series inductance of the composite ceramic capacitor 15 is reduced. Becomes smaller.
【００１２】[0012]
【実施例】次に、本発明の実施例を図面に基づいて詳し
く説明する。 ＜実施例１＞図１に示すように、この例では全て同一構
成の４つの積層セラミックコンデンサ１０を用いて４端
子構造の複合セラミックコンデンサ１５を作製した。即
ち、この複合セラミックコンデンサ１５は４つの積層セ
ラミックコンデンサ１０がコンデンサ間に接着剤（図示
せず）を介して積重ねられかつ接合される。この積重ね
体１１は直方体を形成する。それぞれの積層セラミック
コンデンサ１０はセラミック誘電体１０ａと内部電極１
０ｂが交互に積層して焼成され、相対向するチップ両端
に内部電極１０ｂが交互に現れたベアチップ１０ｃと、
このベアチップ１０ｃの両端に内部電極１０ｂに導通す
るように焼付けられた一対の第１外部電極１０ｄ及び第
２外部電極１０ｅとを備える。４つの積層セラミックコ
ンデンサ１０は第１外部電極１０ｄ及び第２外部電極１
０ｅをそれぞれ同一方向に揃えて積重ねられる。Embodiments of the present invention will now be described in detail with reference to the drawings. <Example 1> As shown in FIG. 1, in this example, a composite ceramic capacitor 15 having a four-terminal structure was produced using four monolithic ceramic capacitors 10 having the same structure. That is, in this composite ceramic capacitor 15, four laminated ceramic capacitors 10 are stacked and bonded to each other via an adhesive (not shown). The stacked body 11 forms a rectangular parallelepiped. Each monolithic ceramic capacitor 10 includes a ceramic dielectric 10a and an internal electrode 1.
0b are alternately laminated and fired, and the bare chips 10c in which the internal electrodes 10b appear alternately on both ends of the opposing chip,
Both ends of the bare chip 10c are provided with a pair of a first external electrode 10d and a second external electrode 10e that are baked so as to be electrically connected to the internal electrode 10b. The four monolithic ceramic capacitors 10 include a first external electrode 10d and a second external electrode 1
0e are stacked in the same direction.
【００１３】積重ね体１１の外部電極同士を導通するよ
うに外部電極１０ｄ及び１０ｅに一対のリードフレーム
１２及び１３がそれぞれ接着される。リードフレーム１
２は第１水平部１６と第１垂直部１８とを備え、リード
フレーム１３は第２水平部１７と第２垂直部１９とを備
える。第１及び第２水平部１６，１７はそれぞれ厚さ２
００μｍ程度のフレキシブルな両面銅張板であって、上
部銅張層１６ａ，１７ａ、絶縁層１６ｂ，１７ｂ及び下
部銅張層１６ｃ，１７ｃからなる。絶縁層１６ｂ，１７
ｂはエポキシ樹脂又はポリイミド樹脂の層からなる。水
平部１６，１７は僅かな間隔をあけて互いに平行に外部
電極１０ｄ，１０ｅが全面に形成されない積重ね体１１
の底面に沿って、かつこの底面の両側に突出して配設さ
れる。A pair of lead frames 12 and 13 are bonded to the external electrodes 10d and 10e so that the external electrodes of the stack 11 are electrically connected to each other. Lead frame 1
2 includes a first horizontal portion 16 and a first vertical portion 18, and the lead frame 13 includes a second horizontal portion 17 and a second vertical portion 19. The first and second horizontal portions 16 and 17 each have a thickness of 2
It is a flexible double-sided copper clad plate having a thickness of about 00 μm and is composed of upper copper clad layers 16a and 17a, insulating layers 16b and 17b, and lower copper clad layers 16c and 17c. Insulating layers 16b and 17
b consists of a layer of epoxy resin or polyimide resin. The horizontal portions 16 and 17 have a slight gap and are parallel to each other.
Along the bottom surface of the base plate and on both sides of the bottom surface.
【００１４】垂直部１８は水平部１６に、また垂直部１
９は水平部１７にそれぞれ垂直にはんだ付けされ、垂直
部１８は外部電極１０ｄに、また垂直部１９は外部電極
１０ｅにそれぞれはんだ付けされる。垂直部１８の下端
が対向する水平部１７及び垂直部１９の下端が対向する
水平部１６には、それぞれ上部銅張層１６ａ及び１７ａ
が設けられず、絶縁層露出部１６ｄ及び１７ｄが形成さ
れる。露出部１６ｄは外部電極１０ｅに接触しないよう
に、また露出部１７ｄは外部電極１０ｄに接触しない広
さを有する。The vertical portion 18 is connected to the horizontal portion 16 and the vertical portion 1
9 is soldered vertically to the horizontal portion 17, the vertical portion 18 is soldered to the external electrode 10d, and the vertical portion 19 is soldered to the external electrode 10e. The upper copper clad layers 16a and 17a are respectively provided in the horizontal portion 17 where the lower ends of the vertical portions 18 face each other and the horizontal portion 16 where the lower ends of the vertical portions 19 face each other.
Is not provided, and insulating layer exposed portions 16d and 17d are formed. The exposed portion 16d has a width not to contact the external electrode 10e, and the exposed portion 17d has a width not to contact the external electrode 10d.
【００１５】図２に示すように、このように作製された
複合セラミックコンデンサ１５は基板２１の表面に僅か
な間隔で互いに平行に形成された一対の線路２２及び２
３にはんだ２４により接続される。具体的には水平部１
６,１７が線路２２及び２３にそれぞれはんだ付けされ
る。４端子構造のコンデンサ１５に線路２２から流れる
リップル電流は水平部１７、垂直部１９、外部電極１０
ｅ、内部電極１０ｂ（図１）、外部電極１０ｄ、垂直部
１８及び水平部１６を通って線路２３に流れる。積重ね
体１１で発生する磁界が互いに相殺され、しかも水平部
１６，１７が線路２２，２３に密着し、前記式（１）の
ｌ（基板とコンデンサとの隙間）及びＢ（線路間の間
隔）は極めて小さくなるため、複合セラミックコンデン
サ１５の直列自己インダクタンスは小さくなる。As shown in FIG. 2, the composite ceramic capacitor 15 thus manufactured has a pair of lines 22 and 2 formed on the surface of the substrate 21 in parallel with each other at a slight interval.
3 is connected by solder 24. Specifically, horizontal part 1
6, 17 are soldered to the lines 22 and 23, respectively. The ripple current flowing from the line 22 to the capacitor 15 having the four-terminal structure is the horizontal portion 17, the vertical portion 19, the external electrode 10
e, the internal electrode 10b (FIG. 1), the external electrode 10d, the vertical portion 18 and the horizontal portion 16, and then flows to the line 23. The magnetic fields generated in the stack 11 cancel each other out, and the horizontal portions 16 and 17 are in close contact with the lines 22 and 23, and l (the gap between the substrate and the capacitor) and B (the gap between the lines) in the above formula (1). Is extremely small, the series self-inductance of the composite ceramic capacitor 15 is small.
【００１６】なお、リードフレームの水平部１６及び１
７を両面銅張板により形成する以外に、図３に示すよう
に垂直部１８及び１９の下端に対向する部分に絶縁層１
６ｅ及び１７ｅを設けてもよい。The horizontal portions 16 and 1 of the lead frame are
In addition to forming 7 by a double-sided copper clad plate, as shown in FIG. 3, the insulating layer 1 is formed on the portions facing the lower ends of the vertical portions 18 and 19.
6e and 17e may be provided.
【００１７】＜実施例２＞図４〜図６は別の実施例を示
す。この例では２端子構造の複合セラミックコンデンサ
３５について説明する。リードフレーム３２は水平部３
６と垂直部３８を有し、リードフレーム３３は水平部３
７と垂直部３９を有する。図５に示すように略Ｌ字状の
２枚の薄い導電板Ｍ及びＮが略十字状になるように配置
され、導電板間に絶縁層３４を介して重ね合わされる。
図５の一点鎖線で示す折畳み線ｍ，ｎで導電板Ｍ及びＮ
はそれぞれ折畳まれ、図４及び図６に示すように積重ね
体１１に密着する。垂直部３８に外部電極１０ｄが、ま
た垂直部３９に外部電極１０ｅがそれぞれはんだ付けさ
れる。図６に示すように水平部３６は外部電極１０ｄに
は接続するが、外部電極１０ｅには接続しないようにそ
の広さが決められる。水平部３６及び３７が積重ね体１
１の底面に沿ってかつ積重ね体１１の片側に突出して配
設される。<Embodiment 2> FIGS. 4 to 6 show another embodiment. In this example, a composite ceramic capacitor 35 having a two-terminal structure will be described. The lead frame 32 is the horizontal part 3
6 and a vertical portion 38, and the lead frame 33 has a horizontal portion 3
7 and a vertical portion 39. As shown in FIG. 5, two thin L-shaped conductive plates M and N are arranged so as to have a substantially cross shape, and are stacked between the conductive plates with an insulating layer 34 interposed therebetween.
The fold lines m and n shown by the alternate long and short dash line in FIG.
Are folded and are brought into close contact with the stack 11 as shown in FIGS. 4 and 6. The external electrode 10d is soldered to the vertical portion 38, and the external electrode 10e is soldered to the vertical portion 39. As shown in FIG. 6, the horizontal portion 36 is connected to the external electrode 10d, but its width is determined so as not to be connected to the external electrode 10e. The horizontal portions 36 and 37 are the stack 1
It is arranged so as to project along the bottom surface of the stack 1 and to one side of the stack 11.
【００１８】このような構成の複合セラミックコンデン
サ３５は、図１２に示した線路３及び４を有する銅張積
層基板２にその水平部３６及び３７が接続するように実
装される。この場合に前記式（１）のＢ及びｌは極めて
小さくなり、直列自己インダクタンスを小さくできる。
水平部３６から流れ込むリップル電流は積層セラミック
コンデンサ１０でその流れる方向が９０度曲がり、更に
９０度曲がって水平部３７に流れるため、磁界を生じな
い。The composite ceramic capacitor 35 having such a structure is mounted so that the horizontal portions 36 and 37 thereof are connected to the copper clad laminate 2 having the lines 3 and 4 shown in FIG. In this case, B and l in the equation (1) are extremely small, and the series self-inductance can be small.
The ripple current flowing from the horizontal portion 36 is bent in the laminated ceramic capacitor 10 by 90 degrees in the flowing direction and further bent by 90 degrees to flow in the horizontal portion 37, so that no magnetic field is generated.
【００１９】＜実施例３＞図７及び図８は更に別の実施
例を示す。この例では積重ね体１１を横置きにした４端
子構造の複合セラミックコンデンサ４５について説明す
る。コンデンサ４５は６個の積層セラミックコンデンサ
１０が重ねられて横置きされる。リードフレーム４２は
水平部４６と垂直部４８を有し、リードフレーム４３は
水平部４７と垂直部４９を有する。図８に示すように略
十字状の２枚の薄い導電板Ｐ及びＱが略キ字状になるよ
うに配置され、導電板間に絶縁層４４を介して重ね合わ
される。図８の一点鎖線で示す折畳み線ｐ，ｑで導電板
Ｐ及びＱはそれぞれ折畳まれ、図７に示すように積重ね
体１１に密着する。垂直部４８に外部電極１０ｄが、ま
た垂直部４９に外部電極１０ｅがそれぞれはんだ付けさ
れる。実施例２と同様に水平部４６は外部電極１０ｄに
は接続するが、外部電極１０ｅには接続しないようにそ
の広さが決められる。水平部４６，４７が積重ね体１１
の側面に沿ってかつ積重ね体１１の両側に突出して配設
される。<Embodiment 3> FIGS. 7 and 8 show still another embodiment. In this example, a composite ceramic capacitor 45 having a four-terminal structure in which the stack 11 is placed horizontally will be described. The capacitor 45 is horizontally placed with six laminated ceramic capacitors 10 stacked on each other. The lead frame 42 has a horizontal portion 46 and a vertical portion 48, and the lead frame 43 has a horizontal portion 47 and a vertical portion 49. As shown in FIG. 8, two substantially cross-shaped thin conductive plates P and Q are arranged so as to have a substantially square shape, and are stacked between the conductive plates with an insulating layer 44 interposed therebetween. The conductive plates P and Q are folded along the folding lines p and q shown by the alternate long and short dash lines in FIG. 8, and are brought into close contact with the stack 11 as shown in FIG. The external electrode 10d is soldered to the vertical portion 48, and the external electrode 10e is soldered to the vertical portion 49. Similar to the second embodiment, the horizontal portion 46 is connected to the external electrode 10d, but its width is determined so as not to be connected to the external electrode 10e. The horizontal portions 46 and 47 are the stack 11
Are arranged so as to project along both side surfaces of the stack 11 and on both sides of the stack 11.
【００２０】このような構成の複合セラミックコンデン
サ４５は、図２に示した線路２２及び２３を有する銅張
積層基板２１にその水平部４６及び４７が接続するよう
に実装される。この場合に前記式（１）のＢ及びｌは極
めて小さくなり、直列自己インダクタンスを小さくでき
る。特に内部電極を鉛直方向に配列することにより入出
力間のシールド性を向上することができる。リップル電
流の流れ方は実施例３と同じであるため繰返しの説明を
省略する。The composite ceramic capacitor 45 having such a structure is mounted so that the horizontal portions 46 and 47 thereof are connected to the copper clad laminate 21 having the lines 22 and 23 shown in FIG. In this case, B and l in the equation (1) are extremely small, and the series self-inductance can be small. In particular, by arranging the internal electrodes in the vertical direction, the shield property between the input and the output can be improved. The flow of the ripple current is the same as that of the third embodiment, and thus the repeated description is omitted.
【００２１】＜実施例４＞図９〜図１１は更に別の実施
例を示す。この例では実施例３と同様に積重ね体１１を
横置きにした４端子構造の複合セラミックコンデンサ５
５について説明する。リードフレーム５２は水平部５６
と垂直部５８（５８ａ，５８ｂ，５８ｃ，５８ｄ，５８
ｅ，５８ｆ）を有し、リードフレーム５３は水平部５７
と垂直部５９（５９ａ，５９ｂ，５９ｃ，５９ｄ，５９
ｅ，５９ｆ）を有する。図１０及び図１１に示すように
櫛歯状の垂直部５８及び５９を有する２枚の薄い導電板
Ｒ及びＳがそれぞれの櫛歯を相手の櫛歯の間に位置する
ように配置され、導電板間に絶縁層５４を介して重ね合
わされる。図１０の導電板Ｒ及びＳの櫛歯部分はその付
け根付近でそれぞれ折畳まれ、図９に示すように積重ね
体１１に密着する。<Fourth Embodiment> FIGS. 9 to 11 show still another embodiment. In this example, the composite ceramic capacitor 5 having a four-terminal structure in which the stack 11 is placed horizontally as in the third embodiment.
5 will be described. The lead frame 52 has a horizontal portion 56.
And the vertical portion 58 (58a, 58b, 58c, 58d, 58
e, 58f), and the lead frame 53 has a horizontal portion 57.
And the vertical portion 59 (59a, 59b, 59c, 59d, 59)
e, 59f). As shown in FIGS. 10 and 11, two thin conductive plates R and S having comb-teeth-shaped vertical portions 58 and 59 are arranged so that the respective comb teeth are located between the mating comb teeth, and The plates are stacked with an insulating layer 54 interposed therebetween. The comb teeth of the conductive plates R and S shown in FIG. 10 are folded around the roots thereof and are brought into close contact with the stack 11 as shown in FIG.
【００２２】リードフレーム５２の垂直部５８ａが積重
ね体１１の図の左から１番目の外部電極１０ｄと、垂直
部５８ｂが３番目の外部電極１０ｄと、垂直部５８ｃが
５番目の外部電極１０ｄと、垂直部５８ｄが２番目の外
部電極１０ｅと、垂直部５８ｅが４番目の外部電極１０
ｅと、垂直部５８ｆが６番目の外部電極１０ｅとそれぞ
れはんだ付けされる。またリードフレーム５３の垂直部
５９ａが積重ね体１１の１番目の外部電極１０ｅと、垂
直部５９ｂが３番目の外部電極１０ｅと、垂直部５９ｃ
が５番目の外部電極１０ｅと、垂直部５９ｄが２番目の
外部電極１０ｄと、垂直部５９ｅが４番目の外部電極１
０ｄと、垂直部５９ｆが６番目の外部電極１０ｄとそれ
ぞれはんだ付けされる。The vertical portion 58a of the lead frame 52 is the first external electrode 10d from the left in the figure of the stack 11, the vertical portion 58b is the third external electrode 10d, and the vertical portion 58c is the fifth external electrode 10d. , The vertical portion 58d is the second external electrode 10e, and the vertical portion 58e is the fourth external electrode 10e.
e and the vertical portion 58f are soldered to the sixth external electrode 10e, respectively. Further, the vertical portion 59a of the lead frame 53 is the first external electrode 10e of the stack 11, the vertical portion 59b is the third external electrode 10e, and the vertical portion 59c.
Is the fifth external electrode 10e, the vertical part 59d is the second external electrode 10d, and the vertical part 59e is the fourth external electrode 1
0d and the vertical portion 59f are soldered to the sixth external electrode 10d, respectively.
【００２３】このような構成の複合セラミックコンデン
サ５５は、図２に示した線路２２及び２３を有する銅張
積層基板２１にその水平部５６及び５７が接続するよう
に実装される。この場合に前記式（１）のＢ及びｌは極
めて小さくなり、直列自己インダクタンスを小さくでき
る。特に内部電極を鉛直方向に配列することにより入出
力間のシールド性を向上することができる。リップル電
流の流れ方は隣り合う積層セラミックコンデンサ１０に
流れる電流の向きが逆になるため、いわゆるケーブルの
「ツイストペア」と同様の効果が得られ、より一層直列
自己インダクタンスが減少する。The composite ceramic capacitor 55 having such a structure is mounted so that the horizontal portions 56 and 57 thereof are connected to the copper clad laminate 21 having the lines 22 and 23 shown in FIG. In this case, B and l in the equation (1) are extremely small, and the series self-inductance can be small. In particular, by arranging the internal electrodes in the vertical direction, the shield property between the input and the output can be improved. Since the directions of the currents flowing through the adjacent monolithic ceramic capacitors 10 are opposite to each other, the same effect as the so-called "twisted pair" of the cable is obtained, and the series self-inductance is further reduced.
【００２４】なお、上記例では４つ又は６つの積層セラ
ミックコンデンサを組合せた複合セラミックコンデンサ
について説明したが、積層セラミックコンデンサの数は
これらに限るものではない。In the above example, a composite ceramic capacitor in which four or six monolithic ceramic capacitors are combined has been described, but the number of monolithic ceramic capacitors is not limited to these.
【００２５】[0025]
【発明の効果】以上述べたように、本発明によれば、量
産可能な積層セラミックコンデンサを並列に組立て、特
殊な構造のリードフレームで外部電極同士を接続したの
で、安価であるとともに、前述した式（１）におけるＢ
とｌを小さくし、直列自己インダクタンスを減少するこ
とができる。リードフレームの垂直部の外部電極への接
触の仕方を変えることにより、個々の積層セラミックコ
ンデンサで発生する磁界が互いに相殺されるため、本発
明の複合セラミックコンデンサは低いＥＳＬ（等価直列
インダクタンス）を有するようになる。またリードフレ
ームにより小型の形態で直接プリント回路基板上に表面
実装でき、積層セラミックコンデンサの数だけ容量値を
大きくすることができる。As described above, according to the present invention, mass-produced monolithic ceramic capacitors are assembled in parallel, and the external electrodes are connected to each other by the lead frame having a special structure. B in equation (1)
And l can be reduced to reduce the series self-inductance. By changing the way of contacting the external electrode of the vertical portion of the lead frame, the magnetic fields generated in the individual monolithic ceramic capacitors cancel each other out, so that the composite ceramic capacitor of the present invention has a low ESL (equivalent series inductance). Like Further, the lead frame allows surface mounting in a small form directly on the printed circuit board, and the capacitance value can be increased by the number of laminated ceramic capacitors.
【図１】本発明実施例１の複合セラミックコンデンサを
リードフレームに接着する前の斜視図。FIG. 1 is a perspective view of a composite ceramic capacitor of Example 1 of the present invention before being bonded to a lead frame.
【図２】その組立てた複合セラミックコンデンサを基板
に実装した状態を示す斜視図。FIG. 2 is a perspective view showing a state in which the assembled composite ceramic capacitor is mounted on a substrate.
【図３】実施例１の別の態様のリードフレームに複合セ
ラミックコンデンサを接着する前の斜視図。FIG. 3 is a perspective view before adhering the composite ceramic capacitor to the lead frame of another aspect of the first embodiment.
【図４】本発明実施例２の複合セラミックコンデンサの
斜視図。FIG. 4 is a perspective view of a composite ceramic capacitor according to a second embodiment of the present invention.
【図５】その垂直部を起立する前のリードフレームの斜
視図。FIG. 5 is a perspective view of the lead frame before standing up its vertical portion.
【図６】図４のＡ−Ａ線断面図。6 is a cross-sectional view taken along the line AA of FIG.
【図７】本発明実施例３の複合セラミックコンデンサの
斜視図。FIG. 7 is a perspective view of a composite ceramic capacitor of Example 3 of the present invention.
【図８】その垂直部を起立する前のリードフレームの斜
視図。FIG. 8 is a perspective view of the lead frame before standing up its vertical portion.
【図９】本発明実施例４の複合セラミックコンデンサの
斜視図。FIG. 9 is a perspective view of a composite ceramic capacitor of Example 4 of the present invention.
【図１０】その垂直部を起立する前のリードフレームの
斜視図。FIG. 10 is a perspective view of the lead frame before raising the vertical portion thereof.
【図１１】そのリードフレームを重ね合わせる前の斜視
図。FIG. 11 is a perspective view before stacking the lead frames.
【図１２】従来例の複合セラミックコンデンサを基板に
実装した状態を示す斜視図。FIG. 12 is a perspective view showing a state in which a conventional composite ceramic capacitor is mounted on a substrate.
【図１３】従来例の別の複合セラミックコンデンサを基
板に実装した状態を示す斜視図。FIG. 13 is a perspective view showing a state in which another conventional composite ceramic capacitor is mounted on a substrate.
【図１４】その等価回路構成図。FIG. 14 is an equivalent circuit configuration diagram thereof.
１０ 積層セラミックコンデンサ １０ａ セラミック誘電体 １０ｂ 内部電極 １０ｃ ベアチップ １０ｄ 第１外部電極 １０ｅ 第２外部電極 １１ 積重ね体 １２，１３，３２，３３，４２，４３，５２，５３ リ
ードフレーム １５，３５，４５，５５ 複合セラミックコンデンサ １６，３６，４６，５６ 第１水平部 １７，３７，４７，５７ 第２水平部 １８，３８，４８，５８ 第１垂直部 １９，３９，４９，５９ 第２垂直部 ３４，４４，５４ 絶縁層10 Multilayer Ceramic Capacitor 10a Ceramic Dielectric 10b Internal Electrode 10c Bare Chip 10d First External Electrode 10e Second External Electrode 11 Stacked Body 12, 13, 32, 33, 42, 43, 52, 53 Lead Frame 15, 35, 45, 55 Composite ceramic capacitor 16, 36, 46, 56 First horizontal part 17, 37, 47, 57 Second horizontal part 18, 38, 48, 58 First vertical part 19, 39, 49, 59 Second vertical part 34, 44 , 54 insulating layers
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 9174−5Ｅ Ｈ０１Ｇ 1/14 Ｊ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location 9174-5E H01G 1/14 J
Claims (4)
が交互に積層して焼成され、相対向するチップ両端に前
記内部電極(10b)が交互に現れたベアチップ(10c)と、前
記ベアチップ(10c)の両端に前記内部電極(10b)に導通す
るように焼付けられた一対の第１及び第２外部電極(10
d,10e)とを備えた積層セラミックコンデンサ(10)を前記
第１及び第２外部電極(10d,10e)をそれぞれ同一方向に
揃えて複数積重ねて積重ね体(11)が形成され、 前記積重ね体の外部電極同士を導通するように前記外部
電極(10d,10e)に一対のリードフレームがそれぞれ接着
された複合セラミックコンデンサにおいて、 前記一対のリードフレーム(12,13,32,33,42,43)は、互
いに絶縁されて第１又は第２外部電極(10d,10e)が全面
に形成されない前記積重ね体(11)の底面又は側面に沿っ
てかつ前記底面又は側面の両側又は片側に突出して配設
された第１及び第２水平部(16,17,36,37,46,47)と、前
記第１及び第２水平部に垂直に設けられ前記第１及び第
２外部電極(10d,10e)にそれぞれ接続される第１及び第
２垂直部(18,19,38,39,48,49)とを備え、 前記第１水平部(16,36,46)が前記第２外部電極(10e)に
絶縁され、前記第２水平部(17,37,47)が前記第１外部電
極(10d)に絶縁されるようにそれぞれ設けられ、かつ前
記第１垂直部(18,38,48)が前記第２水平部(17,37,47)に
絶縁して設けられ、前記第２垂直部(19,39,49)が前記第
１水平部(16,36,46)に絶縁して設けられたことを特徴と
する複合セラミックコンデンサ。1. A ceramic dielectric (10a) and internal electrodes (10b)
Are alternately laminated and fired, and the bare chips (10c) in which the internal electrodes (10b) alternately appear at opposite ends of the chips, and the internal electrodes (10b) are electrically connected to both ends of the bare chips (10c). A pair of first and second external electrodes (10
d, 10e) and a plurality of stacked ceramic capacitors (10) having the first and second external electrodes (10d, 10e) aligned in the same direction to form a stacked body (11). In the composite ceramic capacitor in which a pair of lead frames are respectively bonded to the external electrodes (10d, 10e) so as to electrically connect the external electrodes to each other, the pair of lead frames (12, 13, 32, 33, 42, 43) Is arranged along the bottom surface or side surface of the stack (11) which is insulated from each other and on which the first or second external electrode (10d, 10e) is not formed on the entire surface, and protrudes to both sides or one side of the bottom surface or side surface. The first and second horizontal portions (16, 17, 36, 37, 46, 47) and the first and second external electrodes (10d, 10e) provided vertically to the first and second horizontal portions. First and second vertical portions (18, 19, 38, 39, 48, 49) connected to the second external electrode, respectively. (10e), the second horizontal portion (17, 37, 47) is provided so as to be insulated from the first external electrode (10d), and the first vertical portion (18, 38, 48). ) Is insulated from the second horizontal portion (17, 37, 47), and the second vertical portion (19, 39, 49) is insulated from the first horizontal portion (16, 36, 46). A composite ceramic capacitor characterized by being provided.
い積重ね体(11)の底面に沿ってかつ互いに間隔をあけて
第１及び第２水平部(16,17)が前記底面の両側にそれぞ
れ突出して配設された請求項１記載の複合セラミックコ
ンデンサ。2. The first and second horizontal portions (16, 17) are formed on both sides of the bottom surface of the stack (11) on which the external electrodes (10d, 10e) are not formed on the entire surface and are spaced apart from each other. The composite ceramic capacitor according to claim 1, wherein the composite ceramic capacitors are arranged so as to protrude from each other.
い積重ね体(11)の底面部分又は側面部分で第１及び第２
水平部(36,37,46,47)が絶縁層(34,44)を介して重なりか
つ前記底面又は側面の両側又は片側にそれぞれ突出して
配設された請求項１記載の複合セラミックコンデンサ。3. The first and second bottom portions or side portions of the stack (11) in which the external electrodes (10d, 10e) are not formed on the entire surface.
The composite ceramic capacitor according to claim 1, wherein the horizontal portions (36, 37, 46, 47) are overlapped with each other with the insulating layers (34, 44) interposed therebetween and projecting to both sides or one side of the bottom surface or the side surface.
が交互に積層して焼成され、相対向するチップ両端に前
記内部電極(10b)が交互に現れたベアチップ(10c)と、前
記ベアチップ(10c)の両端に前記内部電極(10b)に導通す
るように焼付けられた一対の第１及び第２外部電極(10
d,10e)とを備えた積層セラミックコンデンサ(10)を前記
第１及び第２外部電極(10d,10e)をそれぞれ同一方向に
揃えて複数積重ねて積重ね体(11)が形成され、 前記積重ね体の外部電極同士を導通するように前記外部
電極(10d,10e)に一対のリードフレームがそれぞれ接着
された複合セラミックコンデンサにおいて、 前記一対のリードフレーム(52,53)は、互いに絶縁され
て第１又は第２外部電極(10d,10e)が全面に形成されな
い前記積重ね体(11)の側面に沿ってかつ前記側面の両側
又は片側に突出して配設された第１及び第２水平部(56,
57)と、前記第１及び第２水平部に垂直に設けられた第
１及び第２垂直部(58,59)とを備え、 前記外部電極が全面に形成されない積重ね体(11)の側面
部分で第１及び第２水平部(56,57)が絶縁層(54)を介し
て重なり、 前記第１垂直部(58)が前記積重ね体(11)の奇数番目の第
１外部電極(10d)と前記積重ね体(11)の偶数番目の第２
外部電極(10e)に接続され、かつ前記第２垂直部(59)が
前記積重ね体(11)の偶数番目の第１外部電極(10d)と前
記積重ね体(11)の奇数番目の第２外部電極(10e)に接続
された複合セラミックコンデンサ。4. A ceramic dielectric (10a) and internal electrodes (10b)
Are alternately laminated and fired, and the bare chips (10c) in which the internal electrodes (10b) alternately appear at opposite ends of the chips, and the internal electrodes (10b) are electrically connected to both ends of the bare chips (10c). A pair of first and second external electrodes (10
d, 10e) and a plurality of stacked ceramic capacitors (10) having the first and second external electrodes (10d, 10e) aligned in the same direction to form a stacked body (11). In the composite ceramic capacitor in which a pair of lead frames are adhered to the external electrodes (10d, 10e) so as to electrically connect the external electrodes, the pair of lead frames (52, 53) are insulated from each other. Alternatively, the first and second horizontal portions (56, 56) arranged along the side surface of the stack (11) in which the second external electrodes (10d, 10e) are not formed on the entire surface and projecting to both sides or one side of the side surface.
57) and first and second vertical portions (58, 59) provided perpendicularly to the first and second horizontal portions, and the side portions of the stack (11) in which the external electrodes are not formed on the entire surface. And the first and second horizontal portions (56, 57) overlap each other with the insulating layer (54) interposed therebetween, and the first vertical portion (58) includes the odd-numbered first external electrodes (10d) of the stack (11). And the even second of the stack (11)
The second vertical portion (59) is connected to the external electrode (10e), and the second vertical portion (59) is an even-numbered first external electrode (10d) of the stack (11) and an odd-numbered second external of the stack (11). A composite ceramic capacitor connected to the electrode (10e).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6040951A JPH07249541A (en) | 1994-03-11 | 1994-03-11 | Composite ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6040951A JPH07249541A (en) | 1994-03-11 | 1994-03-11 | Composite ceramic capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07249541A true JPH07249541A (en) | 1995-09-26 |
Family
ID=12594814
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6040951A Withdrawn JPH07249541A (en) | 1994-03-11 | 1994-03-11 | Composite ceramic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07249541A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001297938A (en) * | 2000-04-13 | 2001-10-26 | Nissin Electric Co Ltd | Laminated ceramic capacitor |
| JP2004165309A (en) * | 2002-11-12 | 2004-06-10 | Mitsubishi Electric Corp | Capacitor unit and semiconductor power converter having the same |
| JP2006100507A (en) * | 2004-09-29 | 2006-04-13 | Shizuki Electric Co Inc | Capacitor connecting structure |
| JP2007019156A (en) * | 2005-07-06 | 2007-01-25 | Tdk Corp | Laminated capacitor |
| US7304833B1 (en) | 2006-03-28 | 2007-12-04 | Tdk Corporation | Solid electrolytic capacitor |
| JP2018158518A (en) * | 2017-03-23 | 2018-10-11 | セイコーエプソン株式会社 | Printer and power source unit for printer |
| JP2019502258A (en) * | 2015-12-09 | 2019-01-24 | ケメット エレクトロニクス コーポレーション | Bulk MLCC capacitor module |
| KR20190121157A (en) | 2018-08-29 | 2019-10-25 | 삼성전기주식회사 | Electronic component |
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| US10515761B1 (en) | 2018-08-30 | 2019-12-24 | Samsung Electro-Mechanics Co., Ltd. | Electronic component including a capacitor array |
| CN110648843A (en) * | 2018-06-27 | 2020-01-03 | 株式会社村田制作所 | Laminated ceramic electronic component |
| CN111063544A (en) * | 2018-10-16 | 2020-04-24 | 株式会社村田制作所 | Laminated ceramic electronic component |
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-
1994
- 1994-03-11 JP JP6040951A patent/JPH07249541A/en not_active Withdrawn
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|---|---|---|---|---|
| JP2001297938A (en) * | 2000-04-13 | 2001-10-26 | Nissin Electric Co Ltd | Laminated ceramic capacitor |
| JP2004165309A (en) * | 2002-11-12 | 2004-06-10 | Mitsubishi Electric Corp | Capacitor unit and semiconductor power converter having the same |
| JP2006100507A (en) * | 2004-09-29 | 2006-04-13 | Shizuki Electric Co Inc | Capacitor connecting structure |
| JP2007019156A (en) * | 2005-07-06 | 2007-01-25 | Tdk Corp | Laminated capacitor |
| JP4635749B2 (en) * | 2005-07-06 | 2011-02-23 | Ｔｄｋ株式会社 | Multilayer capacitor |
| US7304833B1 (en) | 2006-03-28 | 2007-12-04 | Tdk Corporation | Solid electrolytic capacitor |
| JP2019502258A (en) * | 2015-12-09 | 2019-01-24 | ケメット エレクトロニクス コーポレーション | Bulk MLCC capacitor module |
| JP2018158518A (en) * | 2017-03-23 | 2018-10-11 | セイコーエプソン株式会社 | Printer and power source unit for printer |
| CN110648843B (en) * | 2018-06-27 | 2022-10-18 | 株式会社村田制作所 | Laminated ceramic electronic component |
| US11527364B2 (en) | 2018-06-27 | 2022-12-13 | Murata Manufacturing Co., Ltd. | Multilayer ceramic electronic component including a plurality of bodies and metal terminals connected to outer electrodes |
| CN110648843A (en) * | 2018-06-27 | 2020-01-03 | 株式会社村田制作所 | Laminated ceramic electronic component |
| KR20190121147A (en) | 2018-08-16 | 2019-10-25 | 삼성전기주식회사 | Electronic component |
| US11004613B2 (en) | 2018-08-16 | 2021-05-11 | Samsung Electro-Mechanics Co., Ltd. | Multilayer capacitor |
| KR20190121156A (en) | 2018-08-29 | 2019-10-25 | 삼성전기주식회사 | Electronic component |
| US10636570B2 (en) | 2018-08-29 | 2020-04-28 | Samsung Electro-Mechanics Co., Ltd. | Electronic component |
| KR20190121157A (en) | 2018-08-29 | 2019-10-25 | 삼성전기주식회사 | Electronic component |
| US10984954B2 (en) | 2018-08-29 | 2021-04-20 | Samsung Electro-Mechanics Co., Ltd. | Capacitor array |
| US10854389B2 (en) | 2018-08-29 | 2020-12-01 | Samsung Electro-Mechanics Co., Ltd. | Electronic component |
| US10636571B2 (en) | 2018-08-29 | 2020-04-28 | Samsung Electro-Mechanics Co., Ltd. | Electronic component |
| US10529496B1 (en) | 2018-08-30 | 2020-01-07 | Samsung Electro-Mechanics Co., Ltd. | Electronic component including a capacitor array |
| US10861648B2 (en) | 2018-08-30 | 2020-12-08 | Samsung Electro-Mechanics Co., Ltd. | Electronic component |
| KR20200025993A (en) | 2018-08-30 | 2020-03-10 | 삼성전기주식회사 | Electronic component |
| US10515761B1 (en) | 2018-08-30 | 2019-12-24 | Samsung Electro-Mechanics Co., Ltd. | Electronic component including a capacitor array |
| KR20190121162A (en) | 2018-08-30 | 2019-10-25 | 삼성전기주식회사 | Electronic component |
| KR20200042860A (en) * | 2018-10-16 | 2020-04-24 | 가부시키가이샤 무라타 세이사쿠쇼 | Multilayer ceramic electronic component |
| CN111063544A (en) * | 2018-10-16 | 2020-04-24 | 株式会社村田制作所 | Laminated ceramic electronic component |
| US11501921B2 (en) | 2018-10-16 | 2022-11-15 | Murata Manufacturing Co., Ltd. | Multilayer ceramic electronic component |
| US12051548B2 (en) | 2019-04-25 | 2024-07-30 | KYOCERA AVX Components Corporation | Low inductance component |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20010605 |