JPH0757971A - Composite ceramic capacitor - Google Patents
Composite ceramic capacitorInfo
- Publication number
- JPH0757971A JPH0757971A JP5199394A JP19939493A JPH0757971A JP H0757971 A JPH0757971 A JP H0757971A JP 5199394 A JP5199394 A JP 5199394A JP 19939493 A JP19939493 A JP 19939493A JP H0757971 A JPH0757971 A JP H0757971A
- Authority
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- Japan
- Prior art keywords
- external electrodes
- ceramic capacitor
- electrodes
- numbered
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、複数の積層セラミック
コンデンサを並列に組立てた複合セラミックコンデンサ
に関する。更に詳しくはＤＣ−ＤＣコンバータ用のリッ
プルフィルタ、ＡＣライン過渡フィルタに利用され、又
はスイッチ、リレー、ソリッドステートリレー等におけ
る誘電負荷を抑えるスナバコンデンサ等に利用される複
合セラミックコンデンサに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite ceramic capacitor in which a plurality of laminated ceramic capacitors are assembled in parallel. More specifically, the present invention relates to a composite ceramic capacitor used as a ripple filter for a DC-DC converter, an AC line transient filter, or a snubber capacitor for suppressing a dielectric load in a switch, a relay, a solid state relay or the like.
【０００２】[0002]
【従来の技術】近年、電源回路や集積回路における開発
には高周波でのリップルを濾波することが要求される。
ＤＣ−ＤＣコンバータは５００Ｈｚから１ＭＨｚの切換
え周波数で設計されている。出力フィルタはこうした周
波数帯域や更に高い周波数帯域で低いインピーダンスを
示し、かつ大きなリップル電流を取り除くことが要求さ
れる。2. Description of the Related Art In recent years, it has been required to filter ripples at high frequencies for development in power supply circuits and integrated circuits.
The DC-DC converter is designed with a switching frequency of 500 Hz to 1 MHz. The output filter exhibits low impedance in these frequency bands and higher frequency bands, and is required to remove a large ripple current.
【０００３】例えば特開平３−２７２１２２号公報に開
示されているような、公知の複合セラミックコンデンサ
だけが小型で高い共振状態を実現し、かつ２０〜５０μ
Ｆの静電容量を有することができる。フィルムコンデン
サや電解コンデンサはこうした目的には適さない。この
複合セラミックコンデンサは複数の積層セラミックコン
デンサをチップコンデンサの形態で接着剤を介して重合
し高容量化している。Only a known composite ceramic capacitor as disclosed in, for example, Japanese Unexamined Patent Publication No. 3-272122 realizes a small size and a high resonance state, and 20 to 50 μm.
It can have a capacitance of F. Film capacitors and electrolytic capacitors are not suitable for this purpose. In this composite ceramic capacitor, a plurality of laminated ceramic capacitors are polymerized in the form of chip capacitors via an adhesive to increase the capacity.
【０００４】即ち、この量産可能な複合セラミックコン
デンサは、図９及び図１０に示すように、ベアチップ１
の両端部に一対の外部電極２，３を形成した複数の積層
セラミックコンデンサ４をそれぞれ外部電極を揃えて接
着剤５を介して重合した後、重合して得られた接合体の
両端部に金属板６，７を接着剤８により接着して接合体
端部に現れる複数の外部電極同士を導通するようにして
いる。この積層セラミックコンデンサ４のベアチップ１
はセラミック誘電体１ａと内部電極１ｂが交互に積層し
て焼成され、相対向するチップ両端に内部電極１ｂが交
互に現れる。外部電極２，３はベアチップ１の両端部に
おいて内部電極１ｂに導通するように焼付けられる。し
かし、上記複合セラミックコンデンサは高い共振周波数
が得られない欠点があった。That is, as shown in FIGS. 9 and 10, this mass-produced composite ceramic capacitor has a bare chip 1
A plurality of monolithic ceramic capacitors 4 each having a pair of external electrodes 2 and 3 formed on both ends thereof are polymerized through the adhesive 5 with the external electrodes aligned, and then the metal is formed on both ends of the bonded body obtained by the polymerization. The plates 6 and 7 are adhered by the adhesive 8 so that the plurality of external electrodes appearing at the end portions of the joined body are electrically connected to each other. Bare chip 1 of this multilayer ceramic capacitor 4
The ceramic dielectrics 1a and the internal electrodes 1b are alternately laminated and fired, and the internal electrodes 1b appear alternately at the opposite ends of the chip. The external electrodes 2 and 3 are baked on both ends of the bare chip 1 so as to be electrically connected to the internal electrodes 1b. However, the above composite ceramic capacitor has a drawback that a high resonance frequency cannot be obtained.
【０００５】従来、低い直列インダクタンスと高い共振
周波数を有する特殊な多層コンデンサが、特公昭５７−
５６２１７号公報、特開昭６０−５３００９号公報、特
開平２−１５９００８号公報及び Proceedings 1990 E.
C.T.C (IEEE)の第２８４頁〜第２８８頁（"A Low Induc
tance Capacitor Technology" J.M.Oberschmidt）に開
示されている。一般的に、共振周波数Ｆ0はＥＳＬ（等
価直列インダクタンス）に関係し、次の式（１）で表さ
れる。Ｌ0は等価直列インダクタンス、Ｃは静電容量で
ある。Conventionally, a special multilayer capacitor having a low series inductance and a high resonance frequency is disclosed in Japanese Patent Publication No.
56217, JP 60-53009 A, JP 2-159008 A and Proceedings 1990 E.
CTC (IEEE) pages 284 to 288 ("A Low Induc
Tance Capacitor Technology "JMOberschmidt). Generally, the resonance frequency F 0 is related to ESL (equivalent series inductance) and is represented by the following equation (1): L 0 is an equivalent series inductance, C Is the capacitance.
【０００６】[0006]
【数１】 [Equation 1]
【０００７】これらの多層コンデンサは、例えば誘電体
と導電性シートを交互に積層して形成される。それぞれ
の導電性シートの周縁には電極用の複数のタブが隣合う
層で重ならないように突設され、積層体の側面にはこれ
らのタブを電極端子として出現させる。複数の導電性シ
ートをシート毎に接地用シートと給電用シートにして、
給電用シートを接地用シートの間に配置する。上記多層
コンデンサはこのように電極端子を配列することによ
り、接地用電極端子が給電用電極端子に接近して設けら
れ、入出力間の誘導を減少できる。また上記多層コンデ
ンサは極めて低いインダクタンスを有するような周波数
の使用に適する。These multilayer capacitors are formed, for example, by alternately laminating dielectrics and conductive sheets. A plurality of tabs for electrodes are projectingly provided on the periphery of each conductive sheet so as not to overlap in adjacent layers, and these tabs are made to appear as electrode terminals on the side surface of the laminated body. A plurality of conductive sheets for each sheet as a grounding sheet and a power feeding sheet,
The power feeding sheet is placed between the grounding sheets. By arranging the electrode terminals in this manner, the above-mentioned multilayer capacitor is provided with the grounding electrode terminal close to the power feeding electrode terminal, and the induction between the input and output can be reduced. Also, the multilayer capacitor is suitable for use in frequencies having extremely low inductance.
【０００８】[0008]
【発明が解決しようとする課題】しかし、特公昭５７−
５６２１７号公報等に示される多層コンデンサは特殊な
チップを製作しなければならず、その設計と構造に起因
して、また少量の特注品であるため非常に高価になる欠
点があった。また特開平３−２７２１２２号公報に示さ
れる複合セラミックコンデンサは、市販の積層セラミッ
クコンデンサを積重ねるに過ぎないため、上記多層コン
デンサより格段に安価に製作できるけれども、その反面
上記多層コンデンサのような低い直列インダクタンスや
高い自己共振周波数を示さない欠点があった。However, the Japanese Patent Publication No. 57-
The multilayer capacitor disclosed in Japanese Laid-Open Patent Publication No. 56217, for example, has a drawback in that a special chip has to be manufactured, and due to its design and structure, and because it is a small amount of a custom-made product, it becomes very expensive. The composite ceramic capacitor disclosed in Japanese Patent Laid-Open No. 3-272122 can be manufactured at a much lower cost than the above-mentioned multilayer capacitor because it is merely a stack of commercially available multilayer ceramic capacitors, but on the other hand, it is as low as the above-mentioned multilayer capacitor. It has the drawback of not showing series inductance or high self-resonant frequency.
【０００９】本発明の目的は、量産可能な積層セラミッ
クコンデンサを用いて安価で、低い直列インダクタンス
と高い自己共振周波数を示すことができる複合セラミッ
クコンデンサを提供することにある。また本発明の別の
目的は、小型で表面実装可能であって、大容量値が得ら
れる複合セラミックコンデンサを提供することにある。
更に本発明の別の目的は、接続抵抗が小さく、大電流が
流れても過熱することのない複合セラミックコンデンサ
を提供することにある。It is an object of the present invention to provide a composite ceramic capacitor which is inexpensive and can exhibit a low series inductance and a high self-resonant frequency by using a mass-produced monolithic ceramic capacitor. Another object of the present invention is to provide a composite ceramic capacitor that is small in size, surface mountable, and has a large capacitance value.
Still another object of the present invention is to provide a composite ceramic capacitor which has a small connection resistance and does not overheat even when a large current flows.
【００１０】[0010]
【課題を解決するための手段】図１に示すように、本発
明は、セラミック誘電体１０ａと内部電極１０ｂが交互
に積層して焼成され、相対向するチップ両端に内部電極
１０ｂが交互に現れたベアチップ１０ｃと、このベアチ
ップ１０ｃの両端に内部電極１０ｂに導通するように焼
付けられた一対の第１及び第２外部電極１０ｄ，１０ｅ
とを備えた積層セラミックコンデンサ１０を第１及び第
２外部電極１０ｄ，１０ｅをそれぞれ同一方向に揃えて
複数積重ねて形成され、外部電極同士を導通するように
外部電極１０ｄ，１０ｅに一対のリードフレーム１２，
１３がそれぞれ接着された複合セラミックコンデンサ１
５の改良である。As shown in FIG. 1, according to the present invention, ceramic dielectrics 10a and internal electrodes 10b are alternately laminated and fired, and internal electrodes 10b appear alternately at opposite ends of a chip. A bare chip 10c and a pair of first and second external electrodes 10d and 10e baked on both ends of the bare chip 10c so as to be electrically connected to the internal electrodes 10b.
A plurality of laminated ceramic capacitors 10 each including the first and second external electrodes 10d and 10e are formed in the same direction and are stacked, and a pair of lead frames are formed on the external electrodes 10d and 10e so that the external electrodes are electrically connected to each other. 12,
Composite ceramic capacitor 1 in which 13 are bonded together
It is an improvement of 5.
【００１１】その特徴ある構成は、複数の積層セラミッ
クコンデンサ１０，１０間に第１外部電極同士及び第２
外部電極同士を絶縁するように絶縁性シート１１が設け
られ、一対のリードフレーム１２，１３のうち一方１２
が積重ねた複数の積層セラミックコンデンサ１０の奇数
番目の第１外部電極１０ｄと偶数番目の第２外部電極１
０ｅに接続され、一対のリードフレーム１２，１３のう
ち他方１３が積重ねた複数の積層セラミックコンデンサ
１０の偶数番目の第１外部電極１０ｄと奇数番目の第２
外部電極１０ｅに接続されたことにある。The characteristic structure is that the first external electrodes are connected to each other and the second
The insulating sheet 11 is provided so as to insulate the external electrodes from each other, and one of the pair of lead frames 12 and 13 is provided.
An odd-numbered first external electrode 10d and an even-numbered second external electrode 1 of a plurality of laminated ceramic capacitors 10
0e and the other of the pair of lead frames 12 and 13 is laminated on the other 13 of the plurality of laminated ceramic capacitors 10 having even-numbered first external electrodes 10d and odd-numbered second external electrodes 10d.
It is connected to the external electrode 10e.
【００１２】図３に示すように、本発明の別の複合セラ
ミックコンデンサ２０は、セラミック誘電体１０ａと内
部電極１０ｂが交互に積層して焼成され、相対向するチ
ップ両端に内部電極１０ｂが交互に現れたベアチップ１
０ｃと、このベアチップ１０ｃの両端に内部電極１０ｂ
に導通するように焼付けられた一対の第１及び第２外部
電極１０ｄ，１０ｅとを備えた積層セラミックコンデン
サ１０が第１及び第２外部電極１０ｄ，１０ｅをそれぞ
れ同一方向に揃えて複数互いに間隔をあけて並べられ、
外部電極同士を導通するように外部電極１０ｄ，１０ｅ
に一対のリードフレーム２２、２３がそれぞれ接着され
る。その特徴ある構成は、一対のリードフレーム２２，
２３のうち一方２２が並べられた複数の積層セラミック
コンデンサ１０の奇数番目の第１外部電極１０ｄと偶数
番目の第２外部電極１０ｅに接続され、一対のリードフ
レーム２２，２３のうち他方２３が並べられた複数の積
層セラミックコンデンサ１０の偶数番目の第１外部電極
１０ｄと奇数番目の第２外部電極１０ｅに接続されたこ
とにある。As shown in FIG. 3, in another composite ceramic capacitor 20 of the present invention, ceramic dielectrics 10a and internal electrodes 10b are alternately laminated and fired, and internal electrodes 10b are alternately arranged at opposite ends of the chip. Bare chip 1
0c and internal electrodes 10b on both ends of the bare chip 10c.
A multilayer ceramic capacitor 10 having a pair of first and second external electrodes 10d and 10e baked so as to be electrically connected to each other has a plurality of first and second external electrodes 10d and 10e aligned in the same direction and spaced from each other. Lined up open,
External electrodes 10d and 10e so that the external electrodes are electrically connected to each other
A pair of lead frames 22 and 23 are bonded to each other. The characteristic structure is that the pair of lead frames 22,
One of the lead frames 22, 23 is connected to the odd-numbered first external electrodes 10d and the even-numbered second external electrodes 10e of the plurality of laminated ceramic capacitors 10, and the other 23 of the pair of lead frames 22, 23 is aligned. It is connected to the even-numbered first external electrodes 10d and the odd-numbered second external electrodes 10e of the plurality of laminated ceramic capacitors 10 thus formed.
【００１３】[0013]
【作用】本発明の複合セラミックコンデンサ１５（２
０）のＥＳＬ（等価直列インダクタンスＬ0）が低くな
る理由は明確ではないが、次のように推量される。本発
明の構造のように複数の積層セラミックコンデンサ１０
の同一方向に揃えられた第１外部電極１０ｄと第２外部
電極１０ｅに対してリードフレーム１２，１３（２２，
２３）を交互に接続することにより、リードフレーム
１２，１３（２２，２３）の外部電極１０ｄ，１０ｅに
接触する面積が、図１０に示す従来のリードフレーム
６，７の外部電極２，３に接触する面積より小さくなる
こと、及びそれぞれの積層セラミックコンデンサ１０
で発生する磁界が互いに相殺されること等の理由から全
体的にみた場合に、本発明の複合セラミックコンデンサ
１５（２０）は低いＥＳＬ（等価直列インダクタンスＬ
0）を有するようになる。このＥＳＬが低くなると、前
述した式（１）より共振周波数Ｆ0は高くなる。The composite ceramic capacitor 15 (2 of the present invention
The reason why ESL (equivalent series inductance L 0 ) of 0 ) is low is not clear, but it is presumed as follows. A plurality of laminated ceramic capacitors 10 having the structure of the present invention
With respect to the first external electrode 10d and the second external electrode 10e aligned in the same direction, the lead frames 12, 13 (22,
By alternately connecting 23), the areas of the lead frames 12, 13 (22, 23) in contact with the external electrodes 10d, 10e are the same as those of the conventional lead frames 6, 7 shown in FIG. Being smaller than the contact area, and each monolithic ceramic capacitor 10
When viewed as a whole for the reason that the magnetic fields generated in 1) cancel each other out, the composite ceramic capacitor 15 (20) of the present invention has a low ESL (equivalent series inductance L).
0 ). When the ESL becomes low, the resonance frequency F 0 becomes high according to the above-mentioned formula (1).
【００１４】[0014]
【実施例】次に、本発明の実施例を図面に基づいて詳し
く説明する。 ＜実施例１＞図１及び図２に示すように、この例では全
て同一構成の５つの積層セラミックコンデンサ１０を用
いて複合セラミックコンデンサ１５を作製した。即ち、
この複合セラミックコンデンサ１５は５つの積層セラミ
ックコンデンサ１０がコンデンサ間に接着剤付きのガラ
スエポキシ樹脂フィルム１１を介装して積重ねられかつ
接合される。それぞれの積層セラミックコンデンサ１０
は長さ５．７ｍｍ、幅５．０ｍｍ、厚さ２．０で、静電
容量が１０μＦの市販品（品番ＫＣ８０Ｅ１Ｅ１０６
Ｍ、三菱マテリアル製）である。その接合体は直方体を
形成し、その静電容量は５０μＦである。それぞれの積
層セラミックコンデンサ１０はセラミック誘電体１０ａ
と内部電極１０ｂが交互に積層して焼成され、相対向す
るチップ両端に内部電極１０ｂが交互に現れたベアチッ
プ１０ｃと、このベアチップ１０ｃの両端に内部電極１
０ｂに導通するように焼付けられた一対の第１外部電極
１０ｄ及び第２外部電極１０ｅとを備える。５つの積層
セラミックコンデンサ１０は第１外部電極１０ｄ及び第
２外部電極１０ｅをそれぞれ同一方向に揃えて積重ねら
れる。Embodiments of the present invention will now be described in detail with reference to the drawings. <Example 1> As shown in FIGS. 1 and 2, in this example, a composite ceramic capacitor 15 was manufactured using five monolithic ceramic capacitors 10 having the same structure. That is,
In this composite ceramic capacitor 15, five laminated ceramic capacitors 10 are stacked and bonded with a glass epoxy resin film 11 with an adhesive interposed between the capacitors. Each monolithic ceramic capacitor 10
Is a commercially available product with a length of 5.7 mm, a width of 5.0 mm, a thickness of 2.0, and a capacitance of 10 μF (product number KC80E1E106
M, manufactured by Mitsubishi Materials). The joined body forms a rectangular parallelepiped, and its capacitance is 50 μF. Each monolithic ceramic capacitor 10 has a ceramic dielectric 10a.
And the internal electrodes 10b are alternately laminated and fired, and the bare chips 10c in which the internal electrodes 10b alternately appear on both ends of the chip facing each other, and the internal electrodes 1 on both ends of the bare chip 10c.
0b includes a pair of a first external electrode 10d and a second external electrode 10e that are baked so as to be conductive. The five monolithic ceramic capacitors 10 are stacked with the first external electrode 10d and the second external electrode 10e aligned in the same direction.
【００１５】５つの積層セラミックコンデンサ１０は樹
脂フィルム１１により隣接する第１外部電極同士及び第
２外部電極同士が電気的に絶縁される。これらの外部電
極同士を導通するように外部電極１０ｄ及び１０ｅに一
対のリードフレーム１２及び１３がそれぞれ接着され
る。リードフレーム１２及び１３はそれぞれフレーム本
体１２ａ，１３ａ、アーム部１２ｂ，１３ｂ、押さえ部
１２ｃ，１３ｃ及び実装部１２ｄ，１３ｄを備える。フ
レーム本体１２ａ及び１３ａはそれぞれ外部電極１０ｄ
及び１０ｅが両端にしか存在しない積層セラミックコン
デンサ１０の側面に接する。フレーム本体１２ａ及び１
３ａは両端の外部電極に接触しないように幅が狭く形成
される。押さえ部１２ｃ及び１３ｃはそれぞれフレーム
本体１２ａ及び１３ａから直角に折れ曲がって接合体の
最上の積層セラミックコンデンサ１０を押さえるための
ものである。実装部１２ｄ及び１３ｄはそれぞれ図示し
ないプリント回路基板上のランドにはんだ付けするため
のものである。In the five monolithic ceramic capacitors 10, the first external electrodes and the second external electrodes adjacent to each other are electrically insulated by the resin film 11. A pair of lead frames 12 and 13 are adhered to the external electrodes 10d and 10e so that these external electrodes are electrically connected to each other. The lead frames 12 and 13 include frame bodies 12a and 13a, arm portions 12b and 13b, holding portions 12c and 13c, and mounting portions 12d and 13d, respectively. The frame bodies 12a and 13a are respectively provided with external electrodes 10d.
And 10e are in contact with the side surface of the monolithic ceramic capacitor 10 which exists only at both ends. Frame bodies 12a and 1
The width of 3a is formed so as not to contact the external electrodes on both ends. The holding portions 12c and 13c are bent at right angles from the frame bodies 12a and 13a, respectively, and hold down the uppermost monolithic ceramic capacitor 10 of the joined body. The mounting portions 12d and 13d are for soldering to lands on a printed circuit board (not shown).
【００１６】アーム部１２ｂ及び１３ｂはそれぞれフレ
ーム本体１２ａ及び１３ａから直角に折れ曲がって延び
る。アーム部１２ｂは接合体の奇数番目、即ち第１番目
と第３番目と第５番目の第１外部電極１０ｄと、偶数番
目、即ち第２番目と第４番目の第２外部電極１０ｅに接
続される。アーム部１３ｂは接合体の偶数番目、即ち第
２番目と第４番目の第１外部電極１０ｄと、奇数番目、
即ち第１番目と第３番目と第５番目の第２外部電極１０
ｅに接続される。これらの接続はリフローはんだによる
はんだ付けで行われる。The arm portions 12b and 13b extend at right angles from the frame bodies 12a and 13a, respectively. The arm portion 12b is connected to the odd-numbered, ie, the first, third, and fifth first external electrodes 10d and the even-numbered, that is, the second and fourth second external electrodes 10e of the joined body. It The arm part 13b is an even-numbered part of the joined body, that is, the second and fourth first external electrodes 10d and odd-numbered parts,
That is, the first, third, and fifth second external electrodes 10
connected to e. These connections are made by reflow soldering.
【００１７】＜比較例１＞図９及び図１０に示すよう
に、５つの積層セラミックコンデンサ４を用いて複合セ
ラミックコンデンサ９を作製した。各積層セラミックコ
ンデンサ４は実施例１と同一のものを用いた。５つの積
層セラミックコンデンサ４をそれぞれ外部電極２，３を
揃えてエポキシ樹脂接着剤５を介して重合した後、重合
して得られた接合体の両端部にリードフレームとなる断
面Ｌ字状に曲げられた金属板６，７をはんだ８付けして
接合体端部に現れる複数の外部電極同士を導通するよう
にした。<Comparative Example 1> As shown in FIGS. 9 and 10, a composite ceramic capacitor 9 was produced using five laminated ceramic capacitors 4. The same monolithic ceramic capacitors 4 as in Example 1 were used. The five laminated ceramic capacitors 4 are polymerized by aligning the external electrodes 2 and 3 via the epoxy resin adhesive 5, and then bent at both ends of the bonded body obtained by the polymerization so as to have an L-shaped cross section serving as a lead frame. The metal plates 6 and 7 thus prepared were soldered to each other so that the plurality of external electrodes appearing at the end portions of the joined body were electrically connected to each other.
【００１８】＜比較試験と評価＞実施例１の複合セラミ
ックコンデンサ１５と比較例１の複合セラミックコンデ
ンサ９の各高周波特性をインピーダンス／ゲインフェー
ズアナライザ（ＨＰ４１９４Ａ、ＹＨＰ社製）を用いて
測定した。図５に示すような芯線１６とシールド１７の
間が５０Ωのケーブル１９に、図６及び図７に示すよう
に実施例１と比較例１の複合セラミックコンデンサを個
別にはんだ付けした。１８は絶縁体である。この複合セ
ラミックコンデンサをはんだ付けした回路は図８に示す
等価回路で表される。この回路はバイパス又はローパス
フィルタモードを示す。この回路により実施例１と比較
例１の複合セラミックコンデンサの挿入損失をそれぞれ
測定した。その結果を表１に示す。<Comparative Test and Evaluation> The high frequency characteristics of the composite ceramic capacitor 15 of Example 1 and the composite ceramic capacitor 9 of Comparative Example 1 were measured using an impedance / gain phase analyzer (HP4194A, manufactured by YHP). The composite ceramic capacitors of Example 1 and Comparative Example 1 were individually soldered to a cable 19 having a 50 Ω between the core wire 16 and the shield 17 as shown in FIG. 5 as shown in FIGS. 6 and 7. 18 is an insulator. A circuit to which this composite ceramic capacitor is soldered is represented by an equivalent circuit shown in FIG. This circuit exhibits a bypass or low pass filter mode. The insertion loss of the composite ceramic capacitors of Example 1 and Comparative Example 1 was measured by this circuit. The results are shown in Table 1.
【００１９】[0019]
【表１】 [Table 1]
【００２０】表１から明らかなように、実施例１の複合
セラミックコンデンサ１５は比較例１の複合セラミック
コンデンサ９と比べて、ＥＳＬが４分の１程度であっ
て、共振周波数Ｆ0は約２倍に高くなっていることが判
る。As is clear from Table 1, the composite ceramic capacitor 15 of Example 1 has an ESL of about 1/4 and the resonance frequency F 0 of about 2 as compared with the composite ceramic capacitor 9 of Comparative Example 1. You can see that it is twice as high.
【００２１】＜実施例２＞図３及び図４に示すように、
実施例１と同一の５つの積層セラミックコンデンサ１０
が第１及び第２外部電極１０ｄ，１０ｅをそれぞれ同一
方向に揃えて複数互いに間隔をあけて一列に並べられ
る。これらの積層セラミックコンデンサ１０の上下に一
対のリードフレーム２２及び２３が接着され、複合セラ
ミックコンデンサ２０が作製される。リードフレーム２
２及び２３はそれぞれフレーム本体２２ａ，２３ａ及び
アーム部２２ｂ，２３ｂを備える。リードフレーム２２
は更に押さえ部２２ｃ及び実装部２２ｄを、またリード
フレーム２３は更に実装部２３ｄを備える。フレーム本
体２２ａ及び２３ａは一対の外部電極１０ｄ，１０ｅに
接触しない幅を有し、それぞれ接着剤２１（フレーム本
体２２ａ用の接着剤は図示しない）により積層セラミッ
クコンデンサ１０の外部電極が形成されない部分に接着
される。押さえ部２２ｃは両端の積層セラミックコンデ
ンサ１０を押さえるためのものであり、実装部２２ｄ，
２３ｄは図示しないプリント回路基板上のランドにはん
だ付けするためのものである。<Embodiment 2> As shown in FIGS. 3 and 4,
Five monolithic ceramic capacitors 10 identical to those of Example 1
The first and second external electrodes 10d and 10e are aligned in the same direction, and a plurality of the first and second external electrodes 10d and 10e are arranged in a line at intervals. A pair of lead frames 22 and 23 are bonded to the upper and lower sides of these monolithic ceramic capacitors 10 to fabricate a composite ceramic capacitor 20. Lead frame 2
2 and 23 include frame bodies 22a and 23a and arm portions 22b and 23b, respectively. Lead frame 22
Further includes a holding portion 22c and a mounting portion 22d, and the lead frame 23 further includes a mounting portion 23d. The frame bodies 22a and 23a have a width that does not come into contact with the pair of external electrodes 10d and 10e, and are provided with adhesives 21 (adhesives for the frame body 22a are not shown) at portions where the external electrodes of the monolithic ceramic capacitor 10 are not formed. To be glued. The holding portion 22c is for holding the monolithic ceramic capacitors 10 at both ends, and the mounting portion 22d,
23d is for soldering to a land on a printed circuit board (not shown).
【００２２】アーム部２２ｂは並べられた５つの積層セ
ラミックコンデンサ１０の奇数番目、即ち図の左から１
番目と第３番目と第５番目の第１外部電極１０ｄと、偶
数番目、即ち第２番目と第４番目の第２外部電極１０ｅ
に接続される。アーム部２３ｂは並べられた５つの積層
セラミックコンデンサ１０の偶数番目、即ち第２番目と
第４番目の第１外部電極１０ｄと、奇数番目、即ち第１
番目と第３番目と第５番目の第２外部電極１０ｅに接続
される。これらの接続はリフローはんだによるはんだ付
けで行われる。この複合セラミックコンデンサ２０の高
周波特性を、実施例１と同様に測定したところ、実施例
１とほぼ同等の数値を示した。The arm portion 22b is an odd number of the five laminated ceramic capacitors 10 arranged, that is, 1 from the left in the figure.
The first, third and fifth first external electrodes 10d and the even, ie, second and fourth second external electrodes 10e.
Connected to. The arm portion 23b is an even-numbered, ie, second and fourth, first external electrode 10d of the five laminated ceramic capacitors 10 arranged side by side, and an odd-numbered, ie, first, external electrode.
The second, third, and fifth outer electrodes 10e are connected. These connections are made by reflow soldering. When the high frequency characteristics of this composite ceramic capacitor 20 were measured in the same manner as in Example 1, the values were substantially the same as those in Example 1.
【００２３】なお、上記例では５つの積層セラミックコ
ンデンサを組合せた複合セラミックコンデンサについて
説明したが、積層セラミックコンデンサの数は５つに限
らず４個以下でも６個以上でもよい。In the above example, a composite ceramic capacitor in which five monolithic ceramic capacitors are combined has been described, but the number of monolithic ceramic capacitors is not limited to five and may be four or less or six or more.
【００２４】[0024]
【発明の効果】以上述べたように、本発明によれば、量
産可能な積層セラミックコンデンサを並列に組立て、特
殊な構造のリードフレームで外部電極同士を接続したの
で、安価であるとともに、リードフレームのそれぞれの
外部電極に接触する面積が、図１０に示す従来のリード
フレームの外部電極に接触する面積より小さいため、或
いは個々の積層セラミックコンデンサで発生する磁界が
互いに相殺されるため、本発明の複合セラミックコンデ
ンサは低いＥＳＬ（等価直列インダクタンスＬ0）を有
するようになり、結果として前述した式（１）より共振
周波数Ｆ0は高くなる。またリードフレームにより小型
の形態で直接プリント回路基板上に表面実装でき、積層
セラミックコンデンサの数だけ容量値を大きくすること
ができる。更に接触抵抗が低いため接続抵抗が小さく、
大電流を流しても過熱することがない利点もある。As described above, according to the present invention, mass-produced monolithic ceramic capacitors are assembled in parallel and external electrodes are connected to each other by a lead frame having a special structure. Since the area of each of the external electrodes contacting the external electrodes is smaller than the area of the conventional lead frame shown in FIG. 10 contacting the external electrodes, or the magnetic fields generated in the individual laminated ceramic capacitors cancel each other, The composite ceramic capacitor comes to have a low ESL (equivalent series inductance L 0 ), and as a result, the resonance frequency F 0 becomes higher according to the above-mentioned formula (1). Further, the lead frame allows surface mounting in a small form directly on the printed circuit board, and the capacitance value can be increased by the number of laminated ceramic capacitors. Furthermore, since the contact resistance is low, the connection resistance is low,
It also has the advantage of not overheating even when a large current is passed.
【図１】本発明の実施例複合セラミックコンデンサのリ
ードフレームを接着する前の斜視図。FIG. 1 is a perspective view of a composite ceramic capacitor according to an embodiment of the present invention before a lead frame is bonded.
【図２】その組立斜視図。FIG. 2 is an assembled perspective view thereof.
【図３】本発明の別の実施例複合セラミックコンデンサ
のリードフレームを接着する前の斜視図。FIG. 3 is a perspective view of a composite ceramic capacitor according to another embodiment of the present invention before a lead frame is bonded.
【図４】その組立斜視図。FIG. 4 is an assembled perspective view thereof.
【図５】複合セラミックコンデンサの挿入損失を測定す
るためのケーブルの回路構成図。FIG. 5 is a circuit configuration diagram of a cable for measuring insertion loss of a composite ceramic capacitor.
【図６】そのケーブルに複合セラミックコンデンサを接
続した回路構成図。FIG. 6 is a circuit configuration diagram in which a composite ceramic capacitor is connected to the cable.
【図７】そのケーブルに複合セラミックコンデンサを接
続した斜視図。FIG. 7 is a perspective view in which a composite ceramic capacitor is connected to the cable.
【図８】その等価回路構成図。FIG. 8 is an equivalent circuit configuration diagram thereof.
【図９】従来例の複合セラミックコンデンサの中央縦断
面図。FIG. 9 is a central vertical sectional view of a conventional composite ceramic capacitor.
【図１０】そのリードフレームを接着する前の斜視図。FIG. 10 is a perspective view before bonding the lead frame.
【符号の説明】 １０ 積層セラミックコンデンサ １０ａ セラミック誘電体 １０ｂ 内部電極 １０ｃ ベアチップ １０ｄ 第１外部電極 １０ｅ 第２外部電極 １１ ガラスエポキシ樹脂フィルム（絶縁性シート） １２，１３，２２，２３ リードフレーム １５，２０ 複合セラミックコンデンサ[Explanation of Codes] 10 Multilayer Ceramic Capacitor 10a Ceramic Dielectric 10b Internal Electrode 10c Bare Chip 10d First External Electrode 10e Second External Electrode 11 Glass Epoxy Resin Film (Insulating Sheet) 12, 13, 22, 23 Lead Frame 15, 20 Composite ceramic capacitors
Claims (3)
が交互に積層して焼成され、相対向するチップ両端に前
記内部電極(10b)が交互に現れたベアチップ(10c)と、前
記ベアチップ(10c)の両端に前記内部電極(10b)に導通す
るように焼付けられた一対の第１及び第２外部電極(10
d,10e)とを備えた積層セラミックコンデンサ(10)を前記
第１及び第２外部電極(10d,10e)をそれぞれ同一方向に
揃えて複数積重ねて形成され、 前記外部電極同士を導通するように前記外部電極(10d,1
0e)に一対のリードフレーム(12,13)がそれぞれ接着され
た複合セラミックコンデンサ(15)において、 前記複数の積層セラミックコンデンサ(10,10)間に前記
第１外部電極(10d)同士及び第２外部電極(10e)同士を絶
縁するように絶縁性シート(11)が設けられ、 前記一対のリードフレーム(12,13)のうち一方(12)が前
記積重ねた複数の積層セラミックコンデンサ(10)の奇数
番目の前記第１外部電極(10d)と偶数番目の前記第２外
部電極(10e)に接続され、 前記一対のリードフレーム(12,13)のうち他方(13)が前
記積重ねた複数の積層セラミックコンデンサ(10)の偶数
番目の前記第１外部電極(10d)と奇数番目の前記第２外
部電極(10e)に接続されたことを特徴とする複合セラミ
ックコンデンサ。1. A ceramic dielectric (10a) and internal electrodes (10b)
Are alternately laminated and fired, and the bare chips (10c) in which the internal electrodes (10b) alternately appear at opposite ends of the chips, and the internal electrodes (10b) are electrically connected to both ends of the bare chips (10c). A pair of first and second external electrodes (10
d, 10e) is formed by stacking a plurality of laminated ceramic capacitors (10) having the first and second external electrodes (10d, 10e) aligned in the same direction, respectively, and electrically connecting the external electrodes. The external electrode (10d, 1
In a composite ceramic capacitor (15) in which a pair of lead frames (12, 13) are respectively bonded to (0e), the first external electrodes (10d) and the second external electrodes (10d) are provided between the plurality of multilayer ceramic capacitors (10, 10). An insulating sheet (11) is provided so as to insulate the external electrodes (10e) from each other, and one (12) of the pair of lead frames (12, 13) includes a plurality of laminated ceramic capacitors (10). A plurality of stacked layers that are connected to the odd-numbered first external electrodes (10d) and the even-numbered second external electrodes (10e), and the other (13) of the pair of lead frames (12, 13) is stacked. A composite ceramic capacitor, characterized in that it is connected to an even-numbered first external electrode (10d) and an odd-numbered second external electrode (10e) of a ceramic capacitor (10).
ポキシ樹脂フィルムである請求項１記載の複合セラミッ
クコンデンサ。2. The composite ceramic capacitor according to claim 1, wherein the insulating sheet (11) is a glass epoxy resin film with an adhesive.
が交互に積層して焼成され、相対向するチップ両端に前
記内部電極(10b)が交互に現れたベアチップ(10c)と、前
記ベアチップ(10c)の両端に前記内部電極(10b)に導通す
るように焼付けられた一対の第１及び第２外部電極(10
d,10e)とを備えた積層セラミックコンデンサ(10)が前記
第１及び第２外部電極(10d,10e)をそれぞれ同一方向に
揃えて複数互いに間隔をあけて並べられ、 前記外部電極同士を導通するように前記外部電極(10d,1
0e)に一対のリードフレーム(22,23)がそれぞれ接着され
た複合セラミックコンデンサ(20)であって、 前記一対のリードフレーム(22,23)のうち一方(22)が前
記並べられた複数の積層セラミックコンデンサ(10)の奇
数番目の前記第１外部電極(10d)と偶数番目の前記第２
外部電極(10e)に接続され、 前記一対のリードフレーム(22,23)のうち他方(23)が前
記並べられた複数の積層セラミックコンデンサ(10)の偶
数番目の前記第１外部電極(10d)と奇数番目の前記第２
外部電極(10e)に接続されたことを特徴とする複合セラ
ミックコンデンサ。3. A ceramic dielectric (10a) and internal electrodes (10b)
Are alternately laminated and fired, and the bare chips (10c) in which the internal electrodes (10b) alternately appear at opposite ends of the chips, and the internal electrodes (10b) are electrically connected to both ends of the bare chips (10c). A pair of first and second external electrodes (10
d, 10e) and a monolithic ceramic capacitor (10) having the first and second external electrodes (10d, 10e) aligned in the same direction and arranged with a space between each other to electrically connect the external electrodes. So that the external electrodes (10d, 1
0e) is a composite ceramic capacitor (20) in which a pair of lead frames (22, 23) are respectively bonded, one of the pair of lead frames (22, 23) (22) is a plurality of the arranged The odd-numbered first external electrodes (10d) and the even-numbered second electrodes of the multilayer ceramic capacitor (10)
The even-numbered first external electrodes (10d) of the plurality of laminated ceramic capacitors (10) connected to the external electrodes (10e) and the other (23) of the pair of lead frames (22, 23) are arranged. And the odd numbered second
A composite ceramic capacitor characterized by being connected to an external electrode (10e).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5199394A JPH0757971A (en) | 1993-08-11 | 1993-08-11 | Composite ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5199394A JPH0757971A (en) | 1993-08-11 | 1993-08-11 | Composite ceramic capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0757971A true JPH0757971A (en) | 1995-03-03 |
Family
ID=16407057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5199394A Withdrawn JPH0757971A (en) | 1993-08-11 | 1993-08-11 | Composite ceramic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0757971A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004129053A (en) * | 2002-10-04 | 2004-04-22 | Mitsubishi Electric Corp | Dc blocking circuit and communication equipment |
| JP2004165309A (en) * | 2002-11-12 | 2004-06-10 | Mitsubishi Electric Corp | Capacitor unit and semiconductor power converter having the same |
| JP2005072111A (en) * | 2003-08-21 | 2005-03-17 | Murata Mfg Co Ltd | Lead-type capacitor and manufacturing method therefor |
| KR100706454B1 (en) * | 2003-06-16 | 2007-04-10 | 엔이씨 도낀 가부시끼가이샤 | Chip-type solid electrolytic capacitor and method of producing the same |
| JP2008118137A (en) * | 2006-10-31 | 2008-05-22 | Avx Corp | Low-profile electrolytic capacitor assembly |
| JP2012070632A (en) * | 2012-01-06 | 2012-04-05 | Hitachi Automotive Systems Ltd | Power conversion equipment |
| CN110875141A (en) * | 2018-08-29 | 2020-03-10 | 三星电机株式会社 | Electronic assembly |
-
1993
- 1993-08-11 JP JP5199394A patent/JPH0757971A/en not_active Withdrawn
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004129053A (en) * | 2002-10-04 | 2004-04-22 | Mitsubishi Electric Corp | Dc blocking circuit and communication equipment |
| JP2004165309A (en) * | 2002-11-12 | 2004-06-10 | Mitsubishi Electric Corp | Capacitor unit and semiconductor power converter having the same |
| KR100706454B1 (en) * | 2003-06-16 | 2007-04-10 | 엔이씨 도낀 가부시끼가이샤 | Chip-type solid electrolytic capacitor and method of producing the same |
| JP2005072111A (en) * | 2003-08-21 | 2005-03-17 | Murata Mfg Co Ltd | Lead-type capacitor and manufacturing method therefor |
| JP4507527B2 (en) * | 2003-08-21 | 2010-07-21 | 株式会社村田製作所 | Lead type capacitor and manufacturing method thereof |
| JP2008118137A (en) * | 2006-10-31 | 2008-05-22 | Avx Corp | Low-profile electrolytic capacitor assembly |
| JP2012070632A (en) * | 2012-01-06 | 2012-04-05 | Hitachi Automotive Systems Ltd | Power conversion equipment |
| CN110875141A (en) * | 2018-08-29 | 2020-03-10 | 三星电机株式会社 | Electronic assembly |
| CN110875141B (en) * | 2018-08-29 | 2021-11-26 | 三星电机株式会社 | Electronic assembly |
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| JPH0224264Y2 (en) |
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| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20001031 |