JP3998033B2 - Multilayer capacitor and its mounting structure - Google Patents

Description

  The present invention relates to a multilayer capacitor and its mounting structure, and particularly to a multilayer capacitor and its mounting structure that are advantageously applied in a high-frequency circuit.

  As a decoupling capacitor used in a power supply circuit for an MPU (microprocessing unit) or the like in a high frequency region such as several GHz, a laminated layer having a structure as described in, for example, Japanese Patent Application Laid-Open No. 11-144996 (Patent Document 1). Capacitors are known. According to this multilayer capacitor, the current flow from the positive electrode to the negative electrode is shortened by making the adjacent terminals opposite in polarity while having a multi-terminal structure, and the current flow is diversified. The magnetic flux is canceled in the opposite direction, thereby reducing ESL (equivalent series inductance).

  However, the multilayer capacitor described in Patent Document 1 has a problem that the impedance characteristic becomes steep because ESR (equivalent series resistance) also decreases as ESL decreases.

  On the other hand, in Japanese Patent Laid-Open No. 2001-284170 (Patent Document 2), each of the internal electrodes provided to form a capacitance in the capacitor body is drawn to the surface of the capacitor body and is connected to the external terminal electrode. It has been proposed to increase the ESR of a multilayer capacitor by simply providing one lead portion that is electrically connected.

However, according to the structure described in Patent Document 2, although ESR can be increased, there is a problem in that the ESL increases and the characteristics on the high frequency side deteriorate.
JP-A-11-144996 JP 2001-284170 A

  Accordingly, an object of the present invention is to provide a multilayer capacitor capable of achieving high ESR while achieving low ESL.

  Another object of the present invention is to provide a multilayer capacitor mounting structure capable of sufficiently exhibiting the low ESL characteristic of the multilayer capacitor with low ESL as described above.

  A multilayer capacitor according to the present invention includes a capacitor body having a multilayer structure including a plurality of stacked dielectric layers. In order to solve the technical problem described above, the present invention is characterized in that the multilayer capacitor is configured as follows.

  That is, the capacitor body provided in the multilayer capacitor constitutes the first and second capacitor portions.

  The first capacitor unit includes at least one pair of first and second internal electrodes facing each other through a predetermined dielectric layer so as to form a capacitance, and the first internal electrode includes a capacitor A plurality of first lead portions that are drawn to the outer surface of the main body are formed, and a plurality of second lead portions that are drawn to the outer surface of the capacitor main body are formed on the second internal electrode.

On the other hand, the second capacitor unit includes at least one pair of third and fourth internal electrodes facing each other through a predetermined dielectric layer so as to form a capacitance, and the third internal electrode includes A plurality of third lead portions that are drawn to the outer surface of the capacitor body are formed, and a plurality of fourth lead portions that are drawn to the outer surface of the capacitor body are formed on the fourth internal electrode. The

On the outer surface of the capacitor body, first, second, third, and fourth external terminal electrodes that are directly electrically connected to the first, second, third, and fourth lead portions , respectively. Is formed.

The number of pairs of third and fourth lead portions for the pair of third and fourth internal electrodes is equal to the number of pairs of first and second lead portions for the pair of first and second internal electrodes. And the first, second, third and fourth external terminal electrodes extend in the stacking direction of the dielectric layers, and the first and second It is characterized by being formed so as to cover both of the second capacitor portions .

  In the multilayer capacitor according to the present invention, typically, the number of at least one of the third and fourth lead portions for each of the third and fourth internal electrodes is one each of the first and second ones. Less than the number of each of the first and second lead portions for the internal electrode.

  In the multilayer capacitor according to the present invention, preferably, the number of each of the third and fourth lead portions for each of the third and fourth internal electrodes is the same for each of the first and second internal electrodes. Less than each of the first and second drawer portions.

  At least one of the first and second external terminal electrodes may be common with at least one of the third and fourth external terminal electrodes.

  The first and second external terminal electrodes are preferably arranged alternately.

In the capacitor body, it is preferable that the first capacitor portion and the second capacitor portion are arranged so as to be aligned in the stacking direction, and the first capacitor portion is positioned at at least one end in the stacking direction. In this case, in the capacitor body, it is more preferable that the second capacitor portion is disposed so as to be sandwiched between the two first capacitor portions in the stacking direction.
In a specific embodiment of the present invention, the capacitor body has a rectangular parallelepiped shape having two main surfaces facing each other and four side surfaces connecting the two main surfaces, and the dielectric layer is formed on the main surface. The external terminal electrodes are formed on the four side surfaces. In this embodiment, when the main surface has an area larger than any of the four side surfaces, it is preferable that the main surface is mounted in a state where one of the main surfaces is directed to the predetermined mounting surface side.
In another specific embodiment of the present invention, the capacitor body has a rectangular parallelepiped shape having two main surfaces facing each other and four side surfaces connecting the two main surfaces, and the external terminal electrodes are connected to each other. It is formed only on two opposite side surfaces. In this embodiment, when the main surface has an area larger than any of the four side surfaces, the main surface is mounted in a state where one of the main surfaces is directed to the predetermined mounting surface side, and the external terminal When the side surface on which the electrode is formed has a larger area than both the main surface and the remaining side surface, either one of the side surfaces on which the external electrode is formed is directed to the predetermined mounting surface side. Preferably it is implemented.

  The present invention is also directed to a multilayer capacitor mounting structure in which the multilayer capacitor according to a preferred embodiment of the arrangement of the first and second capacitor portions in the stacking direction is mounted on a predetermined mounting surface. It is done. The multilayer capacitor mounting structure according to the present invention is characterized in that the multilayer capacitor is mounted in a state in which the capacitor body is directed so that the first capacitor portion is located closer to the mounting surface.

According to the multilayer capacitor according to the present invention, by dividing the capacitor body into a first capacitor section and a second capacitor portion, for a pair third and fourth internal electrodes in the second capacitor portion first The number of pairs of the third and fourth lead portions is smaller than the number of pairs of the first and second lead portions for the pair of first and second internal electrodes in the first capacitor portion. Therefore, the ESL can be further reduced in the first capacitor unit, and as a result, the resonance frequency of the first capacitor unit can be made higher than the resonance frequency of the second capacitor unit. Therefore, the first capacitor portion affects the high frequency side in the composite characteristics of the capacitor body, the ESL characteristics of the first capacitor portion are reflected, and the ESL of the capacitor body can be reduced.

The capacitor body is divided into a first capacitor portion and a second capacitor portion, and the first capacitor portion is made different from the resonance frequency of the first capacitor portion by making the resonance frequency of the first capacitor portion different from the resonance frequency of the second capacitor portion. The ESR of the capacitor body is determined by the composite characteristics of the ESR of the second capacitor portion and the ESR of the second capacitor portion. Here, as described above, certain number of the third and fourth pair of lead portions of the pair third and fourth internal electrodes in the second capacitor portion, the first capacitor portion 1 Since the number of pairs of the first and second lead portions for the first and second internal electrodes of the pair is smaller, higher ESR can be achieved in the second capacitor portion. Therefore, the ESR of the capacitor body can be increased by the second capacitor unit.

  As a result, a multilayer capacitor satisfying both low ESL and high ESR can be obtained.

  In the multilayer capacitor according to the present invention, as described above, in order to make the number of pairs of the third and fourth lead portions smaller than the number of pairs of the first and second lead portions, each of the third and fourth lead portions is provided. The number of each of the third and fourth lead portions for the fourth inner electrode is less than the number of each of the first and second lead portions for each of the first and second inner electrodes. By doing so, it is possible to reliably achieve low ESL by the first capacitor unit and high ESR by the second capacitor unit.

  In the multilayer capacitor according to the present invention, when the first and second external terminal electrodes are alternately arranged, the flow of current from the positive electrode to the negative electrode can be shortened, and the magnetic flux can be canceled more effectively. Therefore, ESL in the first capacitor unit can be further reduced.

  In the capacitor body, the first capacitor portion and the second capacitor portion are arranged so as to be aligned in the stacking direction, and the first capacitor portion is positioned at at least one end in the stacking direction, When the multilayer capacitor is mounted with the capacitor body facing the first capacitor portion closer to the mounting surface, the negative external terminal electrode passes from the positive external terminal electrode through the internal electrode. Since the path of the current flowing to the can be further shortened, the ESL can be reduced in the mounting structure. Therefore, the low ESL characteristic of the multilayer capacitor with low ESL can be sufficiently exhibited.

  In the capacitor body, when the second capacitor portion is arranged so as to be sandwiched between the two first capacitor portions in the stacking direction, in obtaining the mounting structure capable of reducing the ESL as described above, The directionality about the top and bottom can be eliminated.

  1 to 4 show a multilayer capacitor 1 according to a first embodiment of the present invention. Here, FIG. 1 is a perspective view showing an external appearance of the multilayer capacitor 1, and FIG. 2 is a cross-sectional view showing a mounting structure of the multilayer capacitor 1. In FIG. 2, the multilayer capacitor 1 is shown with a cross section taken along line II-II in FIGS. 3 and 4 described later.

The multilayer capacitor 1 includes a rectangular parallelepiped capacitor body 8 having two main surfaces 2 and 3 facing each other and four side surfaces 4, 5, 6 and 7 connecting the main surfaces 2 and 3. Capacitor body 8 has a laminated structure constituted by a plurality of laminated dielectric layers 9 made of, for example, dielectric ceramics, extending in the directions of main surfaces 2 and 3. Moreover, the main surfaces 2 and 3 have an area larger than any of the four side surfaces 4-7.

  As shown in FIG. 2, the capacitor body 8 constitutes first and second capacitor portions 11 and 12. In this embodiment, the first capacitor unit 11 and the second capacitor unit 12 are arranged so as to be arranged in the stacking direction, and the second capacitor unit 12 is stacked in the stacking direction by the two first capacitor units 11. It is arranged to be sandwiched between. As a result, the first capacitor unit 11 is positioned at both ends of the capacitor body 8 in the stacking direction.

  The first capacitor unit 11 includes at least one pair of first and second internal electrodes 13 and 14 facing each other with a predetermined dielectric layer 9 so as to form a capacitance. On the other hand, the second capacitor unit 12 includes at least one pair of third and fourth internal electrodes 15 and 16 that face each other with a predetermined dielectric layer 9 therebetween so as to form a capacitance.

  In this embodiment, in order to obtain a larger capacitance, the number of pairs of the first and second internal electrodes 13 and 14 and the number of pairs of the third and fourth internal electrodes 15 and 16 are plural. The

  FIG. 3 is a plan view showing the internal structure of the first capacitor unit 11, (a) shows a cross section through which the first internal electrode 13 passes, and (b) shows through the second internal electrode 14. A cross section is shown.

  As shown in FIG. 3A, the first inner electrode 13 is formed with a plurality of, for example, seven first lead portions 17 that are drawn to the outer surface of the capacitor body 8, that is, the side surfaces 4 to 7. Yes. As shown in FIG. 3B, the second internal electrode 14 is formed with a plurality of, for example, seven second lead portions 18 that are drawn to the outer surface of the capacitor body 8, that is, the side surfaces 4-7. Has been. Therefore, the number of pairs of the first and second lead portions 17 and 18 for the pair of first and second internal electrodes 13 and 14 is 7.

On each of the side surfaces 4 to 7 of the capacitor body 8, a plurality of, for example, seven first external terminal electrodes 19, and a second lead portion, which are directly electrically connected to the first lead portion 17, respectively. 18, a plurality of, for example, seven second external terminal electrodes 20 that are directly electrically connected to each other are formed. As shown in FIGS. 1 and 2, the first and second external terminal electrodes 19 and 20 extend in the stacking direction of the dielectric layer 9, and the first and second capacitor portions 11. And 12 are formed so as to extend to both of the main surfaces 2 and 3 from the side surfaces 4 to 7.

  Each position on the side surfaces 4 to 7 from which the first lead portion 17 is pulled out is different from each position from which the second lead portion 18 is pulled out. Therefore, the first external terminal electrode 19 is provided. Each position on the side surfaces 4 to 7 is different from each position of the second external terminal electrode 20. The first external terminal electrodes 19 and the second external terminal electrodes 20 are alternately arranged on the side surfaces 4 to 7.

  FIG. 4 is a plan view showing the internal structure of the second capacitor unit 12, (a) shows a cross section through which the third internal electrode 15 passes, and (b) shows through the fourth internal electrode 16. A cross section is shown.

As shown in FIG. 4A, the third inner electrode 15 is formed with a plurality of , for example, two third lead portions 21 that are drawn to the outer surface of the capacitor body 8, that is, the side surfaces 5 and 7. Yes. Further, as shown in FIG. 4B, the fourth inner electrode 16 is formed with a plurality of , for example, two fourth lead portions 22 that are drawn to the outer surface of the capacitor body 8, that is, the side surfaces 5 and 7. Has been. Therefore, the number of pairs of third and fourth lead portions 21 and 22 for the pair of third and fourth inner electrodes 15 and 16 is two.

  In this embodiment, the third lead portion 21 is electrically connected to the first external terminal electrode 19 described above, and the fourth lead portion 22 is electrically connected to the second external terminal electrode 20 described above. It is connected. That is, some of the first external terminal electrodes 19 are common to the third external terminal electrodes to be electrically connected to the third lead portion 21, and some of the second external terminal electrodes 20 are The fourth external terminal electrode to be electrically connected to the fourth lead portion 22 is common.

  As described above, the third and fourth lead portions 21 and 22 are electrically connected to the first and second external terminal electrodes 19 and 20 common to the first and second lead portions 17 and 18, respectively. When connected, in the multilayer capacitor 1 itself, the first capacitor portion 11 and the second capacitor portion 12 can be connected in parallel.

  As in the embodiment described later, the third and fourth external terminal electrodes to be connected to the third and fourth lead portions 21 and 22, respectively, are separated from the first and second external terminal electrodes. It may be provided.

  In the first embodiment described above, the number of pairs of the third and fourth lead portions 21 and 22 for the pair of third and fourth internal electrodes 15 and 16 is one pair of the first and first pairs. Less than the number of pairs of first and second lead portions 17 and 18 for the two internal electrodes 13 and 14. That is, the former is 2 and the latter is 7.

  In particular, in the first embodiment, the number of each of the third and fourth lead portions 21 and 22 for each of the third and fourth inner electrodes 15 and 16 is one first and second, respectively. The number of first and second lead portions 17 and 18 for each of the internal electrodes 13 and 14 is smaller. That is, the former is two and the latter is seven.

  Therefore, the direction of current flow in the first and second internal electrodes 13 and 14 can be varied, and the ESL of the first capacitor unit 11 is changed to the ESL of the second capacitor unit 12 by canceling out the magnetic flux. Can be lower.

  On the other hand, in the third and fourth internal electrodes 15 and 16, as described above, the number of the third and fourth lead portions 21 and 22 is the same as that of the first and second internal electrodes 13 and 14 and less than the number of each of the first and second drawers 17 and 18. Therefore, the influence of the internal electrodes 13 to 16 or the lead parts 17, 18, 21, and 22 on the ESR is not changed between the first capacitor part 11 and the second capacitor part 12, and the material of the internal electrodes 13 to 16 and the like. If the other conditions are the same, the third and fourth internal electrodes 15 and 16 have less current flowing direction than the first and second internal electrodes 13 and 14. The ESR of the second capacitor unit 12 can be made higher than the ESR of the first capacitor unit 11.

  As described above, the multilayer capacitor 1 has the characteristics that the low ESL characteristic of the first capacitor unit 11 works effectively, and the ESR characteristic of the first capacitor unit 11 and the ESR characteristic of the second capacitor unit 12 are as follows. The high ESR characteristic is reflected. Therefore, according to the multilayer capacitor 1, both low ESL and high ESR can be realized.

  FIG. 2 shows a structure in which the multilayer capacitor 1 is mounted on the mounting surface 25 provided by the wiring board 24. Several conductive lands 26 and 27 are provided on the mounting surface 25 of the wiring board 24, and the first and second external terminal electrodes 19 and 20 are soldered to the conductive lands 26 and 27, respectively ( (Not shown) and the like.

  In the mounting structure as described above, the multilayer capacitor 1 is mounted in a state where the capacitor body 8 is directed so that the first capacitor portion 11 is positioned closer to the mounting surface 25.

In the mounting state of the multilayer capacitor 1 as described above, when the first external terminal electrode 19 becomes the positive electrode and the second external terminal electrode 20 becomes the negative electrode, the positive electrode passes through the internal electrodes 13 to 16 to the negative electrode. In consideration of the loop of the flowing current, the higher the frequency, the more the current flowing from the lowermost layer to the two internal electrodes 13 (a) and 14 (a) becomes the ESL value, as indicated by the dashed arrow 28 in FIG. Will have a greater effect. Therefore, as described above, when the first capacitor unit 11 is positioned closer to the mounting surface 25, the ESL can be further reduced in the mounted state of the multilayer capacitor 1.

  As in the first embodiment, when the second capacitor unit 12 is arranged so as to be sandwiched between the two first capacitor units 11 in the stacking direction, the direction of the capacitor body 8 in the vertical direction is improved. Can be eliminated. Therefore, as shown in FIG. 2, even if the main surface 3 is directed to the mounting surface 25 side or not illustrated, the above-described low ESL can be achieved even when the main surface 2 is directed to the mounting surface 25 side. it can.

  FIG. 5 schematically shows an equivalent circuit provided by the multilayer capacitor 1 described above. In FIG. 5, elements corresponding to the elements shown in FIGS. 1 to 4 are similarly denoted by reference numerals so that the correspondence between the elements shown in FIG. 5 and the elements shown in FIGS. It is attached.

  In FIG. 5, one internal electrode is indicated by one line for each of the first to fourth internal electrodes 13 to 16. In the first capacitor unit 11, two pairs of first and second internal electrodes 13 and 14 are illustrated, and a dotted line is displayed between the two pairs of first and second internal electrodes 13 and 14. This suggests that a larger number of first and second internal electrodes 13 and 14 may be provided. Similarly, in the second capacitor unit 12, two pairs of third and fourth internal electrodes 15 and 16 are illustrated, and a dotted line is provided between the two pairs of third and fourth internal electrodes 15 and 16. It is suggested that a larger number of third and fourth internal electrodes 15 and 16 can be provided.

  Note that when FIG. 5 is compared with FIG. 2 described above, the numbers of the first and second internal electrodes 13 and 14 in the first capacitor unit 11 do not match, but in FIG. It should be understood that only representative of the second internal electrodes 13 and 14 are shown.

  As shown in FIG. 5, ESR 29 and ESL 30 are formed for each of the drawer portions 17, 18, 21, and 22 in association with one of the drawer portions.

  FIG. 6 is a diagram illustrating a circuit configuration of an MPU that uses the multilayer capacitor 1 as a decoupling capacitor in order to explain a preferable application of the multilayer capacitor 1 according to this embodiment.

  The MPU includes an MPU chip 101 and a memory 102. The power supply unit 103 supplies power to the MPU chip 101, and the multilayer capacitor 1 is connected to a power supply circuit from the power supply unit 103 to the MPU chip 101 so as to function as a decoupling capacitor. Although not shown, a signal circuit is configured from the MPU chip 101 to the memory 102 side.

  In relation to the MPU described above, the multilayer capacitor 1 used as a decoupling capacitor is not only used for noise absorption and smoothing against fluctuations in the power supply, but also has a function as a quick power supply. Therefore, in the multilayer capacitor 1 used as such a decoupling capacitor, it is desirable that the ESL is as low as possible. In this respect, the multilayer capacitor according to this embodiment can be advantageously used as a decoupling capacitor. .

FIG. 7 is a diagram corresponding to FIG. 4 for explaining the multilayer capacitor 1a as the first reference example, which is outside the scope of the present invention. In FIG. 7, elements corresponding to those shown in FIG. 4 are denoted by the same reference numerals, and redundant description is omitted.

Compared to the case of the first embodiment described above, in the first reference example , the third internal electrode 15 is simply formed with one third lead portion 21 and the fourth internal electrode. 16 is characterized in that only one fourth drawer portion 22 is formed. Other configurations are the same as those in the first embodiment.

According to the first reference example , the number of pairs of the third and fourth lead portions 21 and 22 for the pair of third and fourth internal electrodes 15 and 16 included in the second capacitor 12 is as follows. Since it is only 1, the ESR in the second capacitor unit 12 can be made higher than in the case of the first embodiment.

FIG. 8 is a view corresponding to FIG. 4 for explaining the multilayer capacitor 1b according to the second embodiment of the present invention. In FIG. 8, elements corresponding to those shown in FIG. 4 are denoted by the same reference numerals, and redundant description is omitted.

In the second embodiment, one of the third and fourth internal electrodes 15 and 16 has the same pattern as any one of the first and second internal electrodes 13 and 14 shown in FIG. It is characterized by having. More specifically, as shown in FIG. 8B, the fourth internal electrode 16 has the same pattern as the second internal electrode 14 shown in FIG. Accordingly, seven fourth extraction portions 22 are formed in the fourth internal electrode 16. Other configurations are substantially the same as those in the first embodiment.

In the second embodiment, one fourth inner electrode 16 has seven fourth lead portions 22, but one third inner electrode 15 simply has two third lead portions 21. Since it only has, the number of pairs of the third and fourth drawer portions 21 and 22 is 2, which is less than the number of pairs of the first and second drawer portions 17 and 18, ie seven. . Therefore, the ESR of the second capacitor unit 12 can be made higher than the ESR of the first capacitor unit 11.

Furthermore, according to the second embodiment, the number of at least one of the third and fourth lead portions 21 and 22 for each of the third and fourth inner electrodes 15 and 16 is one each of the first and second inner electrodes 15 and 16. And the condition that the number of the first and second lead portions 17 and 18 for the second inner electrodes 13 and 14 is less than the number of each.

FIG. 9 is a view for explaining a multilayer capacitor 1c according to a third embodiment of the present invention. 9 (a) and 9 (b) correspond to FIGS. 3 (a) and 3 (b), respectively, and FIGS. 9 (c) and 9 (d) respectively correspond to FIGS. 4 (a) and 4 (b). ). 9, elements corresponding to those shown in FIGS. 3 and 4 are denoted by the same reference numerals, and redundant description is omitted.

The third embodiment is characterized in that the third and fourth external terminal electrodes 31 and 32 are separately formed. That is, the external terminal electrodes formed on the short side surfaces 5 and 7 of the capacitor body 8 are not the first and second external terminal electrodes 19 and 20, but the third and fourth external terminal electrodes 31 and 32. As shown in FIGS. 9C and 9D, the third and fourth external terminal electrodes 31 and 32 have a third lead portion 21 and a fourth internal portion of the third internal electrode 15, respectively. The fourth lead portion 22 of the electrode 16 is electrically connected.

  On the other hand, as shown in FIG. 9A, only five first lead portions 17 are formed in the first internal electrode 13, and these first lead portions 17 are formed on the long side of the capacitor body 8. Are pulled out only to the side surfaces 4 and 6 of the first electrode and electrically connected to the first external terminal electrode 19. Further, as shown in FIG. 9B, the second internal electrode 14 is formed with only five second lead portions 18, and these second lead portions 18 are formed on the long side of the capacitor body 8. Are pulled out only to the side surfaces 4 and 6 of the first electrode and electrically connected to the second external terminal electrode 20.

  Other configurations are substantially the same as those in the first embodiment.

According to the third embodiment, as compared with the case of the first embodiment, if the number other than the condition of each of the first and second lead portions 17 and 18 are equal, the first capacitor portion 11 Is estimated to be higher.

FIG. 10 is outside the scope of the present invention, but is for explaining a multilayer capacitor 1d as a second reference example . Here, FIGS. 10 (a) and (b) correspond to FIGS. 3 (a) and (b), respectively, and FIGS. 10 (c) and 10 (d) respectively correspond to FIGS. 4 (a) and (b). ). 10, elements corresponding to those shown in FIGS. 3 and 4 are denoted by the same reference numerals, and redundant description is omitted.

The second reference example is characterized in that no external terminal electrode is formed on the side surfaces 5 and 7 on the short side of the capacitor body 8. That is, the first and second external terminal electrodes 19 and 20 are formed only on the long side surfaces 4 and 6 of the capacitor body 8.

In the second reference example , as shown in FIG. 10C, the third inner electrode 15 is provided with one third lead portion 21, and the third lead portion 21 is formed of the first lead portion 21. Are electrically connected to any one of the external terminal electrodes 19. As shown in FIG. 10D, the fourth internal electrode 16 is provided with one fourth lead portion 22, and the fourth lead portion 22 corresponds to any of the second external terminal electrodes 20. Are electrically connected to each other.

  Other configurations are substantially the same as those in the first embodiment.

The second reference example has the significance of clearly indicating that the present invention can be applied to the multilayer capacitor 1d in which the external terminal electrodes are not formed on the side surfaces 5 and 7 on the short side of the capacitor body 8.

FIG. 11 is a view corresponding to FIG. 3 for explaining the multilayer capacitor 1e according to the fourth embodiment of the present invention. In FIG. 11, elements corresponding to those shown in FIG. 3 are denoted by the same reference numerals, and redundant description is omitted.

In the fourth embodiment, as shown in FIG. 11A, a dummy lead portion 38 is formed on the dielectric layer 9 on which the first internal electrode 13 is formed, while FIG. As shown in FIG. 4, a dummy lead portion 39 is formed on the dielectric layer 9 on which the second internal electrode 14 is formed.

  The dummy lead portions 38 and 39 are located at the peripheral edge portion of the dielectric layer 9. The dummy lead portion 38 is located between each of the plurality of first lead portions 17 and is electrically connected to the second external terminal electrode 20. On the other hand, the dummy lead portion 39 is located between each of the plurality of second lead portions 18 and is electrically connected to the first external electron electrode 19.

  As described above, the formation of the dummy lead portions 38 and 39 can suppress the level difference that may occur in the capacitor body 8 due to the thickness of the internal electrodes 13 and 14, and the external terminal electrodes 19 and 20. The joint strength to the capacitor body 8 can be increased.

FIG. 12 is a view corresponding to FIG. 4 for explaining the multilayer capacitor 1f according to the fifth embodiment of the present invention. In FIG. 12, elements corresponding to those shown in FIG. 4 are denoted by the same reference numerals, and redundant description is omitted.

In the fifth embodiment, as shown in FIG. 12A, a dummy lead portion 40 is formed on the dielectric layer 9 on which the third internal electrode 15 is formed, while FIG. As shown in FIG. 3, a dummy lead portion 41 is formed on the dielectric layer 9 on which the fourth internal electrode 16 is formed.

  The dummy lead portions 40 and 41 are located along the short side of the dielectric layer 9. The dummy lead portion 40 is electrically connected to the second external terminal electrode 20 formed on the side surfaces 5 and 7 on the short side of the capacitor body 8. On the other hand, the dummy lead portion 41 is electrically connected to the first external terminal electrode 19 formed on the side surfaces 5 and 7 on the short side of the capacitor body 8.

  The above-described dummy drawer portions 40 and 41 have substantially the same functions and effects as the dummy drawer portions 38 and 39 shown in FIG.

As a modification of the fifth embodiment shown in FIG. 12, the dummy lead portion can be further located along the long side of the dielectric layer 9. Also in this case, each dummy lead portion is electrically connected to the first and second external terminal electrodes 19 and 20 formed on the side surfaces 4 and 6 on the long side of the capacitor body 8, respectively.

FIG. 13 is a view for explaining a multilayer capacitor 1g according to a sixth embodiment of the present invention. FIG. 13 shows many elements that are common to the elements shown in FIG. 3 or FIG. 4, and in FIG. 13, elements corresponding to the elements shown in FIG. 3 or FIG. A duplicate description will be omitted.

  FIG. 13 shows a dielectric layer 9 provided in the capacitor main body 8 in which no internal electrode is formed. Such a dielectric layer 9 on which no internal electrode is formed is located at the end of the capacitor body 8 in the stacking direction, or at the boundary between the first capacitor part 11 and the second capacitor part 12. .

In the sixth embodiment, as shown in FIG. 13, a plurality of dummy lead portions 42 are formed along the peripheral edge portion of the dielectric layer 9 where the internal electrodes are not formed. The dummy lead portion 42 is electrically connected to the external terminal electrode 19 or 20. The dimensions of the dummy lead portion 42 are substantially the same as the dimensions of the dummy lead portions 38 to 41 described above, and preferably do not overlap with the main portions of the internal electrodes 13 to 16.

  The operational effects of the dummy drawer portion 42 are substantially the same as those of the dummy drawer portions 38 to 41 described above.

The fourth to sixth embodiments relating to the above-described dummy drawer portion may be implemented independently, but preferably, two or more embodiments are combined and most preferably three The embodiments are implemented in combination.

FIG. 14 is a view corresponding to FIG. 3 for explaining the multilayer capacitor 1h according to the seventh embodiment of the present invention. In FIG. 14, elements corresponding to those shown in FIG. 3 are denoted by the same reference numerals, and redundant description is omitted.

  14 (a) and 14 (b) show the first and second internal electrodes 13 and 14 shown in FIGS. 3 (a) and 3 (b), respectively. On the other hand, a dummy internal electrode 45 is shown in FIG. In this embodiment, the dummy internal electrode 45 has the same pattern as the second internal electrode 14 shown in FIG. That is, the dummy internal electrode 45 is formed with a lead portion 46 that is drawn to the side surfaces 4 to 7 of the capacitor body 8, and the lead portion 46 is electrically connected to the second external terminal electrode 20.

  As described above, in order to form the first capacitor unit 11 (see FIG. 2), the first internal electrode 13 shown in FIG. 14A and the second internal electrode shown in FIG. In this embodiment, at least one dummy is adjacent to the second internal electrode 14 at the end in the stacking direction and / or in the middle of the stacked structure. Internal electrodes 45 are stacked.

  As described above, by including the dummy internal electrode 45 in the laminated structure, the capacitance is not increased, but the bonding strength of the second external terminal electrode 20 to the capacitor body 8 can be increased. Therefore, this embodiment does not require a large capacitance, but is advantageously applied when it is desired to ensure the bonding strength of the external terminal electrode 20 while ensuring the number of laminated dielectric layers 9.

As a modification of the seventh embodiment, a dummy internal electrode having the same pattern as the first internal electrode 13 may be formed.

FIG. 15 is a view corresponding to FIG. 4 for explaining the multilayer capacitor 1i according to the eighth embodiment of the present invention. In FIG. 15, elements corresponding to the elements shown in FIG. 4 are denoted by the same reference numerals, and redundant description is omitted.

  15 (a) and 15 (b) show the third and fourth internal electrodes 15 and 16 shown in FIGS. 4 (a) and 4 (b), respectively. FIG. 15C shows a dummy internal electrode 49. In this embodiment, the dummy internal electrode 49 has the same pattern as the fourth internal electrode 16 shown in FIG. That is, the dummy internal electrode 49 is formed with a lead portion 50 that is drawn to the side surfaces 5 and 7 on the short side of the capacitor body 8, and the lead portion 50 is electrically connected to the second external terminal electrode 20. The

  As described above, in order to form the second capacitor unit 12 (see FIG. 2), the third internal electrode 15 shown in FIG. 15A and the fourth internal electrode 16 shown in FIG. Are laminated so as to face each other, at least one dummy internal electrode 49 is laminated so as to be adjacent to the fourth internal electrode 16 at the end in the lamination direction and / or in the middle of the laminated structure. Is done. The operational effect of the dummy internal electrode 49 described above is substantially the same as that of the dummy internal electrode 45 shown in FIG.

As a modification of the eighth embodiment, a dummy internal electrode having the same pattern as the third internal electrode 15 may be formed.

FIG. 16 is a view corresponding to FIG. 3 for illustrating the multilayer capacitor 1j according to the ninth embodiment of the present invention. In FIG. 16, elements corresponding to those shown in FIG. 3 are denoted by the same reference numerals, and redundant description is omitted.

  16 (a) and 16 (b) show the first and second internal electrodes 13 and 14 shown in FIGS. 3 (a) and 3 (b), respectively. On the other hand, a dummy internal electrode 53 is shown in FIG. In this embodiment, the dummy internal electrode 53 has the same pattern as the fourth internal electrode shown in FIG. That is, the dummy internal electrode 53 is formed with a lead portion 54 that extends to the side surfaces 5 and 7 on the short side of the capacitor body 8, and the lead portion 54 is electrically connected to the second external terminal electrode 20. The

  As described above, in order to form the first capacitor unit 11 (see FIG. 2), the first internal electrode 13 shown in FIG. 16A and the second internal electrode 14 shown in FIG. Are laminated so as to face each other, at least one dummy internal electrode 53 is laminated so as to be adjacent to the second internal electrode 14 at the end in the lamination direction and / or in the middle of the laminated structure. Is done.

  The effect of the dummy internal electrode 53 described above is substantially the same as that of the dummy internal electrodes 45 and 49 shown in FIGS. 14 and 15, respectively.

As a modification of the ninth embodiment, a dummy internal electrode having the same pattern as the third internal electrode 15 shown in FIG. 4A may be formed.

FIG. 17 is a view corresponding to FIG. 4 for illustrating the multilayer capacitor 1k according to the tenth embodiment of the present invention. In FIG. 17, elements corresponding to the elements shown in FIG. 4 are denoted by the same reference numerals, and redundant description is omitted.

  17 (a) and 17 (b) show the third and fourth internal electrodes 15 and 16 shown in FIGS. 4 (a) and 4 (b), respectively. On the other hand, a dummy internal electrode 57 is shown in FIG. The dummy internal electrode 57 has the same pattern as the second internal electrode 14 shown in FIG. That is, the dummy internal electrode 57 is formed with a lead portion 58 that extends to the side surfaces 4 to 7 of the capacitor body 8, and the lead portion 58 is electrically connected to the second external terminal electrode 20.

  As described above, in order to form the second capacitor unit 12 (see FIG. 2), the third internal electrode 15 shown in FIG. 17A and the fourth internal electrode 16 shown in FIG. Are laminated so as to face each other, at least one dummy internal electrode 57 is laminated so as to be adjacent to the fourth internal electrode 16 at the end in the lamination direction and / or in the middle of the laminated structure. Is done.

  The effect of the dummy internal electrode 57 described above is substantially the same as that of the dummy internal electrodes 45, 49, and 53 shown in FIGS.

As a modification of the tenth embodiment, a dummy internal electrode having the same pattern as the first internal electrode 13 shown in FIG. 3A may be formed.

The seventh to tenth embodiments described above can be implemented by appropriately combining them. More specifically, the seventh and ninth embodiments relate to the first capacitor unit 11, and the eighth and tenth embodiments relate to the second capacitor unit 12 . Each of the seventh and ninth embodiments can be implemented in any combination with each of the eighth and tenth embodiments.

18 to 21 show a multilayer capacitor 61 according to an eleventh embodiment of the present invention.

  Here, FIG. 18 is a perspective view showing the appearance of the multilayer capacitor 61, and FIG. 19 is a side view schematically showing the arrangement state of the first and second capacitor portions 62 and 63 in the multilayer capacitor 61. FIG. . 18 and 19 show the mounting surface 64. The multilayer capacitor 61 has a multilayer direction in a direction parallel to the mounting surface 64 in the mounted state.

The multilayer capacitor 61 includes a rectangular parallelepiped capacitor body 71 having two main surfaces 65 and 66 facing each other and four side surfaces 67, 68, 69 and 70 connecting the main surfaces 65 and 66. Capacitor main body 71 has a laminated structure including a plurality of laminated dielectric layers 72 (see FIGS. 20 and 21) made of, for example, dielectric ceramics, extending in the directions of main surfaces 65 and 66. The side surfaces 67 and 69 have a larger area than any of the main surfaces 65 and 66 and the remaining side surfaces 68 and 70.

  As shown in FIG. 19, the capacitor main body 71 constitutes first and second capacitor portions 62 and 63. The first capacitor unit 62 and the second capacitor unit 63 are arranged so as to be aligned in the stacking direction parallel to the mounting surface 64, and the second capacitor unit 63 is sandwiched between the two first capacitor units 62. Are arranged to be. As a result, the first capacitor part 62 is positioned at both ends of the capacitor body 71 in the stacking direction.

  FIG. 20 is a plan view of the dielectric layer 72 showing the internal structure of the first capacitor unit 62, (a) shows a cross section through which the first internal electrode 73 passes, and (b) shows the second layer. A cross section through which the internal electrode 74 passes is shown. On the other hand, FIG. 21 is a plan view of the dielectric layer 72 showing the internal structure of the second capacitor unit 63, (a) shows a section through which the third internal electrode 75 passes, and (b) shows the first 4 shows a cross section through which four internal electrodes 76 pass.

  In the first capacitor section 62, at least a pair of first and second internal electrodes 73 and 74 shown in FIG. 20 are opposed to each other through a predetermined dielectric layer 72 so as to form a capacitance. is doing. On the other hand, in the second capacitor unit 63, at least a pair of third and fourth internal electrodes 75 and 76 shown in FIG. 21 are interposed via a predetermined dielectric layer 72 so as to form a capacitance. They are facing each other.

  As shown in FIG. 20A, the first internal electrode 73 is formed with two first lead portions 77 that are drawn to the two opposite side surfaces 67 and 69 of the capacitor body 71, respectively. Yes. As shown in FIG. 20B, each of the second internal electrodes 74 is formed with two second lead portions 78 that are drawn to the side surfaces 67 and 69 facing each other. Yes.

On each of the side surfaces 67 and 69 of the capacitor main body 71, each of the two first external terminal electrodes 79 electrically connected to the first lead portion 77 and the second lead portion 78 are electrically connected. Two second external terminal electrodes 80 connected to each other are formed. First and second external terminal electrodes 79 and 80 are formed so as to extend along the stacking direction of dielectric layer 72 and over both first and second capacitor portions 62 and 63. In addition, as shown in FIG. 18, a part thereof is formed so as to extend from above each of the side surfaces 67 and 69 to a part of each of the main surfaces 65 and 66. The first external terminal electrodes 79 and the second external terminal electrodes 80 are alternately arranged on the side surfaces 67 and 69, respectively.

  As shown in FIG. 21A, the third inner electrode 75 is formed with one third lead portion 81 that is drawn to the opposite side surfaces 67 and 69 of the capacitor body 71. Further, as shown in FIG. 21B, the fourth inner electrode 76 is formed with one fourth lead portion 82 that is led out to the opposite side surfaces 67 and 69 of the capacitor main body 71, respectively. Yes.

  In this embodiment, the third lead portion 81 is electrically connected to the first external terminal electrode 79 described above, and the fourth lead portion 82 is electrically connected to the second external terminal electrode 80 described above. It is connected.

Also in the eleventh embodiment described above, as in the first embodiment, the third and fourth lead portions 81 and 82 for the pair of third and fourth internal electrodes 75 and 76 are also described. The number of pairs is smaller than the number of pairs of first and second lead portions 77 and 78 for the pair of first and second inner electrodes 73 and 74. That is, the former is 2 and the latter is 4.

In the eleventh embodiment, the number of the third and fourth lead portions 81 and 82 for each of the third and fourth inner electrodes 75 and 76 is one first and second, respectively. The number of first and second lead portions 77 and 78 for each of the internal electrodes 73 and 74 is smaller. That is, the former is two and the latter is four.

  Therefore, the direction of current flow in the first and second internal electrodes 73 and 74 can be varied, and the ESL of the first capacitor unit 62 is changed to the ESL of the second capacitor unit 63 by canceling the magnetic flux. Can be lower. On the other hand, in the third and fourth internal electrodes 75 and 76, since the direction of current flow is small, the second capacitor unit 63 can be used if other conditions such as the material of the internal electrodes 73 to 76 are the same. The ESR of the first capacitor unit 62 can be made higher than that of the first capacitor unit 62.

  Therefore, the characteristics of the multilayer capacitor 61 are a combination of the low ESL characteristic of the first capacitor unit 62 and the high ESR characteristic of the second capacitor unit 63. Therefore, both the low ESL and the high ESR can be realized by the multilayer capacitor 61.

FIGS. 22 and 23 are views corresponding to FIG. 19 for illustrating the multilayer capacitors 61a and 61b according to the twelfth and thirteenth embodiments of the present invention, respectively. 22 and FIG. 23, elements corresponding to those shown in FIG. 19 are denoted by the same reference numerals, and redundant description is omitted.

In the case of the multilayer capacitor 61 according to the eleventh embodiment described above, the dielectric layer 72 and the internal electrodes 73 to 76 extend in a direction orthogonal to the mounting surface 64. Therefore, the multilayer capacitor according to the first embodiment. As in the case of the capacitor 1, it is not necessary to consider the influence on the ESL caused by the distance between the mounting surface 64 and the internal electrode. Therefore, with respect to the arrangement of the first and second capacitor portions 62 and 63, the arrangement states as shown in FIGS. 22 and 23 can be adopted without problems in addition to the arrangement state as shown in FIG.

  While the present invention has been described with reference to the illustrated embodiment, various other modifications are possible within the scope of the present invention.

  For example, the position and number of the lead portions formed on the internal electrode or the position and number of the external terminal electrode can be further variously changed.

  Further, the arrangement of the first and second capacitor portions in the capacitor body can be other than the arrangement in the illustrated embodiment, as can be seen from an experimental example described later.

  Further, for example, in the first embodiment, the first and second internal electrodes 13 and 14 are provided only for constituting the first capacitor unit 11, and the third and fourth internal electrodes 15 and 16 are provided. Although provided only for configuring the second capacitor unit 12, the internal electrode located at the boundary between the first capacitor unit and the second capacitor unit is connected to both the first and second capacitor units. In other words, the internal electrode may be provided as an internal electrode serving as both the first or second internal electrode and the third or fourth internal electrode.

  Next, experimental examples carried out to confirm the effects of the present invention will be described.

  In this experimental example, as is well known, a plurality of ceramic green sheets are prepared, an internal electrode having a lead-out portion is formed on a specific ceramic green sheet by printing a conductive paste, and the ceramic on which the internal electrode is formed Each step of laminating a plurality of ceramic green sheets including green sheets, firing the obtained laminate to obtain a capacitor body, and forming external terminal electrodes on the outer surface of the capacitor body by baking a conductive paste After that, multilayer capacitors according to the respective samples shown in Table 1 were produced.

  Regarding the multilayer capacitor according to each sample, the dimensions of the capacitor body are 2.0 mm × 1.25 mm × 0.5 mm, the total number of multilayered internal electrodes is 64, and the capacitance is 0.68 μF, as shown in FIG. As in the case of the embodiment, the number of external terminal electrodes was set to 14. The thickness of the internal electrode was 1 μm, the thickness of the lead portion was 1 μm, and the width of the lead portion was 150 μm.

  In Table 1, A to E shown in the “stacked arrangement state” column respectively correspond to (A) to (E) in FIG. FIG. 24 shows the arrangement state of the first and second capacitor portions in the stacking direction. Note that, in FIG. 24, the part denoted by reference numeral “35” indicates an outer layer portion where no internal electrode is formed. Moreover, in FIG. 24, each lower surface of the illustrated laminated structure faces the mounting surface side.

  In the column of “first capacitor portion” in Table 1, “internal electrode pattern”, “number of stacked layers”, “first number of lead portions”, “second number of lead portions”, and “number of pairs of lead portions” In the “second capacitor portion” column, “internal electrode pattern”, “number of stacked layers”, “third number of lead portions”, “number of fourth lead portions”, and “number of pairs of lead portions” are shown. "It is shown.

  In each “internal electrode pattern” column, the numbers of the drawings illustrating the internal electrode patterns employed in each sample are cited. It should be noted that “FIG. 25” cited in the “Internal electrode pattern” column in the “First capacitor portion” of the sample 11 and “Internal electrode pattern” column in the “Second capacitor portion” of the sample 11 are cited. “FIG. 26”, “FIG. 27” quoted in the column of “Internal electrode pattern” in “First capacitor portion” of sample 12, “Internal electrode pattern” in “Second capacitor portion” of sample 12 For “FIG. 28” cited in the column and “FIG. 29” cited in the “internal electrode pattern” column in the “second capacitor portion” of the sample 13, FIG. 25, FIG. 26, and FIG. The internal electrode pattern as shown in FIGS. 27, 28 and 29 is employed.

  FIG. 25A shows a first internal electrode 13 having seven first lead portions 17, and FIG. 25B shows a second inner electrode having two second lead portions 18. An electrode 14 is shown.

  FIG. 26A shows the third internal electrode 15 having two third lead portions 21, and FIG. 26B shows the fourth internal electrode having seven fourth lead portions 22. An electrode 16 is shown.

  FIG. 27 shows a first internal electrode 13 having two first lead portions 17 and a second internal electrode 14 having two second lead portions 18. In FIG. 27, (1) to (14) indicate the stacking order.

In FIG. 28, the third internal electrode 15 having one third lead portion 21 and the fourth internal electrode 16 having one fourth lead portion 22 are outside the scope of the present invention . Is shown. In FIG. 28, (1) to (14) indicate the stacking order.

In FIG. 29, the third internal electrode 15 having one third lead portion 21 and the fourth internal electrode 16 having one fourth lead portion 22 are outside the scope of the present invention . And third and fourth external terminal electrodes 31 and 32 that are electrically connected to the third and fourth lead portions 21 and 22, respectively, are shown. In FIG. 29, (1) to (14) indicate the stacking order.

  Referring to Table 1 again, the “number of stacked layers” indicates the total number of stacked layers of the first and second internal electrodes in the “first capacitor portion”, and the “number of stacked layers” corresponds to the “second capacitor portion”. Shows the total number of stacked third and fourth internal electrodes. In addition, “upper” and “lower” in the “number of stacked layers” column of “first capacitor unit” indicate “first capacitor unit (upper)” and “first capacitor” in FIG. Part (bottom) ".

  In addition, the “first number of lead parts”, “second number of lead parts”, and “number of pairs of lead parts” in the “first capacitor part” are respectively the numbers of the lead parts for one first internal electrode. Number, the number of drawers for one second internal electrode, and the number of pairs of first and second drawers for a pair of first and second internal electrodes.

  On the other hand, in the “second capacitor portion”, the “third lead portion number”, the “fourth lead portion number”, and the “number of lead portion pairs” respectively indicate the number of lead portions for one third internal electrode. Number, the number of drawers for one fourth internal electrode, and the number of third and fourth drawer pairs for a pair of third and fourth internal electrodes.

  “ESL value” and “ESR value” obtained for each of the samples 1 to 13 designed as shown in Table 1 are shown in Table 2.

In Tables 1 and 2, the sample numbers marked with * are comparative examples outside the scope of the present invention. Samples 6 to 10 and 12 are outside the scope of the present invention as described above in that the number of the third and fourth lead portions is 1, but are shown as reference examples. .

  As shown in Table 1, the sample 1 as a comparative example does not include the second capacitor portion that contributes to high ESR, and as shown in Table 2, although low ESL can be achieved, high ESR is achieved. Cannot be achieved.

As shown in Table 1, the sample 13 as a comparative example in contrast to the sample 1 does not include the first capacitor portion that contributes to lowering the ESL, so that the higher ESR is achieved as shown in Table 2. However, it is not possible to reduce the ESL.

Further, in the sample 11 as a comparative example, as shown in Table 1, the “number of pairs of drawers” in the “second capacitor unit” is equal to the number of pairs of drawers in the “first capacitor unit”. Therefore, the first capacitor portion and the second capacitor portion have the same structure. As a result, as for the ESL value, only an ESL value of 46 pH, which is almost the same as that of the sample 12 with the smallest number of extraction parts in the reference example of the present invention, was obtained. Only 13.3 mΩ which is about the same as 2 is obtained. This is due to the following reason.

  First, for ESL, the number of pairs of lead portions of the first capacitor portion is two pairs, and the number of pairs of lead portions of the second capacitor portion is also two pairs. Only the same level can be obtained. This is because even if the first number of drawers is seven, there are only two pairs.

  On the other hand, with respect to ESR, since the number of lead-out portions of the internal electrodes constituting the first capacitor portion and the second capacitor portion increases, the ESR per layer is greatly reduced as compared with the sample 13. Furthermore, the ESR is further reduced by connecting the ESRs in parallel by the lamination.

  As described above, when the first capacitor portion and the second capacitor portion have the same structure, the ESR cannot be effectively increased.

Further, in addition to the effect of improving the frequency characteristics on the high frequency side, in the samples 2 to 10 and 12 as examples or reference examples within the scope of the present invention, as shown in Table 1, the first and second Since both of the capacitor portions are provided and the “number of pairs of drawer portions” in the “second capacitor portion” is smaller than the “number of pairs of drawer portions” in the “first capacitor portion”, it is shown in Table 2. Thus, both low ESL and high ESR are achieved.

  For samples 2 to 9, the ESL value is almost the same as that of sample 1. This is because, in the high frequency region, the electric field concentrates on the mounting surface side, and the characteristics of the loop as indicated by the broken arrow 28 shown in FIG. 2 are most affected, and the first capacitor portion having a large number of lead portions. In Samples 2 to 9 that are stacked on the mounting surface side, the low ESL value of the first capacitor portion is dominant.

  On the other hand, in the sample 10 in which the second capacitor portion is disposed on the mounting surface side, the ESL value is higher than those of the samples 2 to 9. Even in the configuration of the sample 10, when compared with the sample 13, the ESL value can be lowered by the amount of the first capacitor portion.

  In Samples 2 to 5 in which the number of stacked first capacitor portions is changed in the same stacked arrangement state, the ESL value is almost the same, and therefore the influence of the number of stacked first capacitor portions on the ESL value. You can see that there are few. The same applies to Samples 6 to 9 in a stacked arrangement state different from Samples 2 to 5.

  On the other hand, as for the ESR value, the ESR value becomes higher as the number of stacked second capacitor portions increases with respect to the total number of stacked multilayer capacitors. Further, when Sample 5, Sample 9, Sample 10, and Sample 12 having the same number of stacked second capacitor portions are compared, the third and fourth samples are compared with Sample 5 in which the number of third and fourth lead portions is two. The sample 9, sample 10 and sample 12 having the number of extraction parts of 1 have higher ESR values. Sample 9 and sample 10 have higher ESR values than sample 13. This is because the ESR value of the first capacitor unit and the ESR value of the second capacitor unit are both higher than the ESR value of the sample 13, and as a result, the resonance frequency between the first capacitor unit and the second capacitor unit is increased. This is because the ESR value of the multilayer capacitor becomes higher than the ESR value of the sample 13 due to the difference.

  Comparing between samples 9 and 10, the ESR values are almost the same, and even if the stacked arrangement state is different, the ESR value tends to hardly change if the number of stacked second capacitor parts is the same. I understand.

1 is a perspective view showing an appearance of a multilayer capacitor 1 according to a first embodiment of the present invention. It is sectional drawing which shows the mounting state of the multilayer capacitor | condenser 1 shown in FIG. 1, About the multilayer capacitor | condenser 1, it has shown with the cross section along line II-II of FIG. 3 and FIG. FIG. 3 is a plan view showing an internal structure of a first capacitor unit 11 shown in FIG. 2, (a) shows a cross section through which a first internal electrode 13 passes, and (b) shows that a second internal electrode 14 A cross section through is shown. FIG. 3 is a plan view showing an internal structure of a second capacitor unit 12 shown in FIG. 2, where (a) shows a cross section through which a third internal electrode 15 passes, and (b) shows that a fourth internal electrode 16 A cross section through is shown. It is a figure which shows typically the equivalent circuit which the multilayer capacitor 1 shown in FIG. 1 provides. It is a figure which shows the circuit structure of MPU which uses the multilayer capacitor | condenser 1 shown in FIG. 1 as a decoupling capacitor. FIG. 5 is a view corresponding to FIG. 4 for explaining a multilayer capacitor 1a as a first reference example, which is outside the scope of the present invention. It is a figure corresponding to FIG. 4 for demonstrating the multilayer capacitor 1b by 2nd Embodiment of this invention. 3A and 3B are views for explaining a multilayer capacitor 1c according to a third embodiment of the present invention. FIGS. 3A and 3B correspond to FIGS. 3A and 3B, respectively. ) Corresponds to FIGS. 4A and 4B, respectively. Although this is outside the scope of the present invention, it is for explaining a multilayer capacitor 1d as a second reference example , and (a) and (b) correspond to FIGS. 3 (a) and (b), respectively. , (C) and (d) correspond to FIGS. 4 (a) and (b), respectively. It is a figure corresponding to FIG. 3 for demonstrating the multilayer capacitor 1e by 4th Embodiment of this invention. It is a figure corresponding to FIG. 4 for demonstrating the multilayer capacitor 1f by 5th Embodiment of this invention. It is a top view of the dielectric material layer 9 for demonstrating the multilayer capacitor 1g by 6th Embodiment of this invention. It is a figure corresponding to FIG. 3 for demonstrating the multilayer capacitor 1h by 7th Embodiment of this invention. It is a figure corresponding to FIG. 4 for demonstrating the multilayer capacitor 1i by 8th Embodiment of this invention. It is a figure corresponding to FIG. 3 for demonstrating the multilayer capacitor 1j by 9th Embodiment of this invention. It is a figure corresponding to FIG. 4 for demonstrating the multilayer capacitor 1k by 10th Embodiment of this invention. It is a perspective view which shows the external appearance of the multilayer capacitor 61 by 11th Embodiment of this invention. FIG. 19 is a side view schematically showing an arrangement state of first and second capacitor portions 62 and 63 in the multilayer capacitor 61 shown in FIG. 18. FIG. 20 is a plan view of a dielectric layer 72 showing the internal structure of the first capacitor unit 62 shown in FIG. 19, where (a) shows a cross section through which the first internal electrode 73 passes, and (b) shows the second structure. The cross section through which the internal electrode 74 passes is shown. FIG. 20 is a plan view of the dielectric layer 72 showing the internal structure of the second capacitor unit 63 shown in FIG. 19, (a) showing a cross section through which the third internal electrode 75 passes, and (b) showing the fourth structure. The cross section through which the internal electrode 76 passes is shown. It is a figure corresponding to FIG. 19 for demonstrating the multilayer capacitor 61a by 12th Embodiment of this invention. It is a figure corresponding to FIG. 19 for demonstrating the multilayer capacitor 61b by 13th Embodiment of this invention. It is a figure which shows some examples of the lamination | stacking arrangement | positioning state about the 1st capacitor | condenser part and 2nd capacitor | condenser part which were employ | adopted in the experiment example implemented in order to confirm the effect by this invention. It is a top view which shows the internal electrode pattern in the 1st capacitor | condenser part of the sample 11 produced in the said experiment example. It is a top view which shows the internal electrode pattern in the 2nd capacitor | condenser part of the sample 11 produced in the said experiment example. It is a top view which shows the internal electrode pattern in the 1st capacitor | condenser part of the sample 12 produced in the said experiment example. It is a top view which shows the internal electrode pattern in the 2nd capacitor | condenser part of the sample 12 produced in the said experiment example. It is a top view which shows the internal electrode pattern in the 2nd capacitor | condenser part of the sample 13 produced in the said experiment example.

Explanation of symbols

1, 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1i, 1j, 1k, 61, 61a, 61b Multilayer capacitor 2, 3, 65, 66 Main surface 4-7, 67-70 Side surface 8, 71 Capacitor body 9, 72 Dielectric layer 11, 62 First capacitor part 12, 63 Second capacitor part 13, 73 First internal electrode 14, 74 Second internal electrode 15, 75 Third internal electrode 16 , 76 Fourth internal electrode 17, 77 First lead portion 18, 78 Second lead portion 19, 79 First external terminal electrode 20, 80 Second external terminal electrode 21, 81 Third lead portion 22 , 82 Fourth lead portion 25, 64 Mounting surface 31 Third external terminal electrode 32 Fourth external terminal electrode

Claims (17)

A capacitor body having a laminated structure constituted by a plurality of laminated dielectric layers,
The capacitor body constitutes first and second capacitor parts,
The first capacitor unit includes at least one pair of first and second internal electrodes facing each other through the predetermined dielectric layer so as to form a capacitance,
The first internal electrode has a plurality of first lead portions that are drawn to the outer surface of the capacitor body, and the second inner electrode is drawn to the outer surface of the capacitor body. A plurality of second drawer portions are formed,
The second capacitor unit includes at least one pair of third and fourth internal electrodes facing each other through the predetermined dielectric layer so as to form a capacitance,
The third internal electrode is formed with a plurality of third lead portions that are drawn to the outer surface of the capacitor body, and the fourth inner electrode is drawn to the outer surface of the capacitor body. A plurality of fourth drawer portions are formed,
On the outer surface of the capacitor body, first, second, third, and fourth external terminals that are electrically connected directly to the first, second, third, and fourth lead portions, respectively. Electrodes are formed,
The number of pairs of the third and fourth lead portions for the pair of third and fourth internal electrodes is the first and second for the pair of first and second internal electrodes. Less than the number of pairs of drawers,
The first, second, third, and fourth external terminal electrodes extend along the stacking direction of the dielectric layers and cover both the first and second capacitor portions. Formed,
Multilayer capacitor.   The number of at least one of the third and fourth lead portions for each of the third and fourth inner electrodes is the first and second for each of the first and second inner electrodes. The multilayer capacitor according to claim 1, wherein the number is less than the number of each of the lead portions.   The number of each of the third and fourth lead portions for each of the third and fourth internal electrodes is the first and second of the first and second internal electrodes, respectively. The multilayer capacitor according to claim 1, wherein the number is less than the number of each of the lead portions.   4. The multilayer capacitor according to claim 1, wherein at least one of the first and second external terminal electrodes is common to at least one of the third and fourth external terminal electrodes. 5.   The multilayer capacitor according to claim 1, wherein the first and second external terminal electrodes are alternately arranged.   In the capacitor body, the first capacitor portion and the second capacitor portion are arranged to be aligned in the stacking direction, and the first capacitor portion is positioned at at least one end in the stacking direction. The multilayer capacitor according to claim 1.   The multilayer capacitor according to claim 6, wherein in the capacitor body, the second capacitor portion is disposed so as to be sandwiched between two first capacitor portions in the stacking direction.   The capacitor body has a rectangular parallelepiped shape having two main surfaces opposed to each other and four side surfaces connecting the two main surfaces, and the dielectric layer extends in the direction of the main surface, The multilayer capacitor according to claim 1, wherein the external terminal electrode is formed on four of the side surfaces.   The main surface has an area larger than any of the four side surfaces, and is mounted in a state where any one of the main surfaces is directed to a predetermined mounting surface side. Multilayer capacitor.   The capacitor main body has a rectangular parallelepiped shape having two main surfaces facing each other and four side surfaces connecting the two main surfaces, and the external terminal electrodes are only on the two side surfaces facing each other. The multilayer capacitor according to claim 1, wherein the multilayer capacitor is formed.   The main surface has an area larger than any of the four side surfaces, and is mounted in a state where any one of the main surfaces is directed to a predetermined mounting surface side. Multilayer capacitor.   The side surface on which the external terminal electrode is formed has a larger area than both the main surface and the remaining side surface, and one of the side surfaces on which the external terminal electrode is formed is a predetermined mounting. The multilayer capacitor according to claim 10, wherein the multilayer capacitor is mounted in a state directed toward a surface side.   8. A structure in which the multilayer capacitor according to claim 6 or 7 is mounted on a predetermined mounting surface, wherein the capacitor body is directed so that the first capacitor portion is located closer to the mounting surface. A multilayer capacitor mounting structure in which the multilayer capacitor is mounted. A capacitor main body having a rectangular parallelepiped shape having two main surfaces facing each other and four side surfaces connecting the two main surfaces, and having a multilayer structure in which a plurality of dielectric layers extending in the direction of the main surface are stacked. ,
The capacitor body constitutes first and second capacitor portions arranged so as to be aligned in the stacking direction of the dielectric layers,
The first capacitor unit includes at least one pair of first and second internal electrodes facing each other through the predetermined dielectric layer so as to form a capacitance,
The first internal electrode is formed with a plurality of first extraction portions that are extended to the side surface of the capacitor body, and the second internal electrode is extended to the side surface of the capacitor body. A plurality of second drawer portions are formed,
The second capacitor unit includes at least one pair of third and fourth internal electrodes facing each other through the predetermined dielectric layer so as to form a capacitance,
The third internal electrode is formed with a plurality of third lead portions that are drawn to the side surface of the capacitor body, and the fourth internal electrode is drawn to the side surface of the capacitor body. A plurality of fourth drawer portions are formed,
The first capacitor body extends only on the two side surfaces of the capacitor body facing each other along the stacking direction of the dielectric layers and covers both the first and second capacitor portions . And a second external terminal electrode is formed,
The first external terminal electrode is directly electrically connected to the first lead portion and the third lead portion, and is electrically insulated from the second lead portion and the fourth lead portion. ,
The second external terminal electrode is directly electrically connected to the second lead portion and the fourth lead portion, and is electrically insulated from the first lead portion and the third lead portion. ,
The number of pairs of the third and fourth lead portions for the pair of third and fourth internal electrodes is the first and second for the pair of first and second internal electrodes. Less than the number of drawer pairs,
Multilayer capacitor. The multilayer capacitor according to claim 14 , wherein the first and second external terminal electrodes are alternately arranged. A capacitor main body having a rectangular parallelepiped shape having two main surfaces facing each other and four side surfaces connecting the two main surfaces, and having a multilayer structure in which a plurality of dielectric layers extending in the direction of the main surface are stacked. ,
The capacitor body constitutes first and second capacitor portions arranged so as to be aligned in the stacking direction of the dielectric layers,
The first capacitor unit includes at least one pair of first and second internal electrodes facing each other through the predetermined dielectric layer so as to form a capacitance,
The first internal electrode is formed with a plurality of first extraction portions that are extended to the side surface of the capacitor body, and the second internal electrode is extended to the side surface of the capacitor body. A plurality of second drawer portions are formed,
The second capacitor unit includes at least one pair of third and fourth internal electrodes facing each other through the predetermined dielectric layer so as to form a capacitance,
The third internal electrode is formed with a plurality of third lead portions that are drawn to the side surface of the capacitor body, and the fourth internal electrode is drawn to the side surface of the capacitor body. A plurality of fourth drawer portions are formed,
On two of the sides facing each other of the capacitor body so as to extend along the stacking direction of the dielectric layer, and rests on the both of the first and second capacitor portions, the first and A second external terminal electrode is formed;
On the remaining two side surfaces of the capacitor body facing each other, extending along the stacking direction of the dielectric layer and over both the first and second capacitor portions , First and second external terminal electrodes are formed;
The first external terminal electrode is directly electrically connected to the first lead portion and the third lead portion, and is electrically insulated from the second lead portion and the fourth lead portion. ,
The second external terminal electrode is directly electrically connected to the second lead portion and the fourth lead portion, and is electrically insulated from the first lead portion and the third lead portion. ,
The number of pairs of the third and fourth lead portions for the pair of third and fourth internal electrodes is the first and second for the pair of first and second internal electrodes. Less than the number of drawer pairs,
Multilayer capacitor. The multilayer capacitor according to claim 16 , wherein the first and second external terminal electrodes are alternately arranged.

Images