JP5949476B2 - Multilayer capacitor - Google Patents

Description

  The present invention relates to a multilayer capacitor.

  Conventionally, a capacitor has been widely used in a smoothing circuit of a power supply circuit such as a DC-DC converter. Here, Patent Document 1 discloses a multilayer chip capacitor having two capacitor portions formed in a single capacitor body. This multilayer chip capacitor has a capacitor body having a first capacitor portion and a second capacitor portion arranged along the stacking direction, and four external electrodes formed on the outside of the capacitor body. In this multilayer chip capacitor, by increasing the total number of laminated internal electrodes in the second capacitor unit to be larger than the total number of laminated internal electrodes in the first capacitor unit, the second capacitor unit has a large capacity and low ESR ( Equivalent Series Resistance (Equivalent Series Resistance) and low ESL (Equivalent Series Inductance) are used, and the first capacitor section has a small capacity, high ESR, and high ESL.

  On the other hand, Patent Document 2 discloses a composite multilayer ceramic capacitor in which a small capacity multilayer ceramic capacitor element and a large capacity multilayer ceramic capacitor element having a large ESR are combined. This composite multilayer ceramic capacitor has an ESR of an external electrode of a large-capacity multilayer ceramic capacitor element larger than that of an external electrode in a small-capacity multilayer ceramic capacitor element. Are provided with a gap portion having a predetermined interval or more.

  Further, Patent Document 3 includes a first capacitor portion and a second capacitor portion having a substantially rectangular parallelepiped shape arranged at a predetermined interval (for example, about 50 μm to 200 μm) along the normal direction of the mounting surface of the circuit board. A multilayer capacitor is disclosed. In this multilayer capacitor, the dielectric layer of the first capacitor portion is formed by sintering a multilayer body of ceramic green sheets containing a paraelectric material. In addition, the dielectric layer of the second capacitor unit is formed by sintering a laminate of ceramic green sheets containing a ferroelectric material. Therefore, the capacity of the second capacitor unit is larger than the capacity of the first capacitor unit. Further, the multilayer capacitor and the circuit board are connected by a solder fillet having such a height that the resin electrode layer functions as an ESR component of the second capacitor portion. Thereby, the ESR component according to the thickness of the resin electrode layer is given to the second capacitor unit. Therefore, the second capacitor portion having a large capacitance has a higher ESR than the first capacitor portion.

JP 2009-60114 A JP 2001-185446 A JP 2012-43947 A

  By the way, in the multilayer chip capacitor described in Patent Document 1, as described above, since the ESR of the large-capacity second capacitor unit is low, the impedance is low in the low frequency region. Therefore, for example, when used as a smoothing capacitor for a power supply circuit such as a DC-DC converter, the power supply circuit may oscillate. Further, since the ESR and ESL of the first capacitor portion having a small capacity are high, the noise removal performance in the high frequency region is lowered.

  On the other hand, according to the composite multilayer ceramic capacitor described in Patent Document 2, since the ESR of the large-capacity multilayer ceramic capacitor element is large, the oscillation of the power supply circuit described above can be suppressed. However, in this composite multilayer ceramic capacitor, the large-capacity multilayer ceramic capacitor element and the small-capacity multilayer ceramic capacitor element are arranged above and below, and have a gap portion that is separated from each other by a predetermined distance of 0.15 mm or more. Has been deployed. More specifically, each metal terminal is electrically connected to the external electrode by sandwiching the vicinity of both side surfaces of each laminate with two metal terminals and connecting with solder. Therefore, in the composite multilayer ceramic capacitor described in Patent Document 2, it is difficult to reduce the size and height of parts.

  Similarly, according to the multilayer capacitor described in Patent Document 3, since the ESR of the large-capacity second capacitor portion is large, the above-described oscillation of the power supply circuit can be suppressed. However, in this multilayer capacitor, in order to make it difficult to transmit the deformation stress of the circuit board and the stress due to the electrostrictive vibration of the first capacitor unit to the second capacitor unit, A predetermined interval is provided between the two capacitor portions. Therefore, it is difficult for the multilayer capacitor described in Patent Document 3 to reduce the size and height of parts.

  The present invention has been made to solve the above-described problems, and can improve noise removal performance in a high frequency region while suppressing oscillation of a power supply circuit, and can be reduced in size and height. An object of the present invention is to provide a multilayer capacitor capable of satisfying the requirements.

  A multilayer capacitor according to the present invention includes a plurality of dielectric layers, a dielectric element body formed in a substantially rectangular parallelepiped shape, a pair of power supply electrodes provided on mutually opposing surfaces of the dielectric element body, and the A pair of ground electrodes provided on a surface orthogonal to the surface provided with the pair of power supply electrodes, a resistance layer disposed between the one power supply electrode and the dielectric body, and one through the resistance layer A first internal electrode connected to the other power supply electrode, a second internal electrode connected to the other power supply electrode, and a third internal electrode connected to both the pair of ground electrodes. The first capacitor portion in which the three internal electrodes are alternately stacked with the dielectric layer interposed therebetween is more than the second capacitor portion in which the second internal electrode and the third internal electrode are alternately stacked with the dielectric layer interposed therebetween. It is characterized by a large capacitance.

  According to the multilayer capacitor in accordance with the present invention, the first capacitor part formed by alternately laminating the first internal electrode and the third internal electrode with the dielectric layer interposed therebetween, the second internal electrode, and the third internal electrode And the second capacitor portion formed by alternately stacking the dielectric layers. Here, the first capacitor portion is formed to have a larger capacitance than the second capacitor portion. The first internal electrode constituting the first capacitor unit is connected to one external electrode through the resistance layer. Therefore, the ESR of the first capacitor unit is higher than that of the second capacitor unit. Furthermore, in the multilayer capacitor according to the present invention, since the internal electrode is formed so as to connect both the pair of ground electrodes, there are two paths from the power supply electrode to the ground electrode, and the ESL is further reduced. As a result, in the multilayer capacitor according to the present invention, two capacitor parts having different capacitance and ESR in one dielectric element body, that is, a first capacitor part having a large capacity, a high ESR, and a low ESL, and A second capacitor portion having a small capacity, low ESR, and low ESL is formed. Therefore, for example, when used as a smoothing capacitor for a power supply circuit such as a DC-DC converter, the oscillation of the power supply circuit is suppressed by the large-capacity, high-ESR first capacitor section, and the small-capacity, low-ESR, low-ESL The second capacitor portion reduces noise in the high frequency region.

  On the other hand, as described above, according to the multilayer capacitor according to the present invention, two capacitors having different capacitances and ESR are formed in one dielectric element body. Can be planned. As a result, it is possible to improve noise removal performance in the high frequency region while suppressing oscillation of the power supply circuit, and to reduce the size and height.

  In the multilayer capacitor according to the present invention, the pair of power supply electrodes is provided on the lateral side surface of the dielectric body, and the pair of ground electrodes is provided on the longitudinal side surface of the dielectric body. It is preferable.

  A multilayer capacitor according to the present invention includes a plurality of dielectric layers, a dielectric element body formed in a substantially rectangular parallelepiped shape, a pair of power supply electrodes provided on mutually opposing surfaces of the dielectric element body, and the A pair of ground electrodes provided on a surface orthogonal to a surface provided with the pair of power supply electrodes; a first resistance layer disposed between the one power supply electrode and the dielectric element; and the other power supply electrode A second resistance layer disposed between the first and second dielectric layers, one end connected to one power supply electrode via the first resistance layer, and the other end connected to the other resistance via the second resistance layer A first internal electrode connected to the power supply electrode, at least a part of one end thereof is connected to one power supply electrode without going through the first resistance layer, and at least a part of the other end passed through the second resistance layer Without being connected to the second internal electrode connected to the other power supply electrode and both the pair of ground electrodes. A first capacitor unit including a third internal electrode, wherein the first internal electrode and the third internal electrode are alternately stacked with the dielectric layer interposed therebetween, and the second internal electrode and the third internal electrode are the dielectric layer. It is characterized in that the capacitance is larger than that of the second capacitor portions alternately stacked with the electrode interposed therebetween.

  According to the multilayer capacitor in accordance with the present invention, the same effects as those of the multilayer capacitor described above can be achieved. In other words, it is possible to improve the noise removal performance in the high frequency region while suppressing the oscillation of the power supply circuit, and to reduce the size and height. Furthermore, according to the multilayer capacitor in accordance with the present invention, ESL can be further reduced by using the power supply electrode (first internal electrode, second internal electrode) as a through electrode. Therefore, it is possible to further improve the noise removal performance in the high frequency region.

  In the multilayer capacitor according to the present invention, the widths of the lead portions at both ends of the first internal electrode are formed narrower than the width of the lead portion of the second internal electrode, and the widths of the first resistance layer and the second resistance layer are , Wider than the leading portion of the first internal electrode, narrower than the leading portion of the second internal electrode, and formed from the upper end to the lower end along the stacking direction of the first internal electrode and the second internal electrode. It is preferable that

  In this case, the first internal electrode having a narrow width of the lead portion is connected to both the power supply electrodes via the first resistance layer and the second resistance layer, so that the first internal electrode formed by the first internal electrode is formed. One capacitor portion has a high ESR. On the other hand, since at least a part of the second internal electrode having a wide lead part is directly connected to both power supply electrodes, the second capacitor part formed by the second internal electrode has a low ESR. Therefore, the ESR of the first capacitor unit can be effectively increased as compared with the ESR of the second capacitor unit.

  A multilayer capacitor according to the present invention includes a plurality of dielectric layers, a dielectric element body formed in a substantially rectangular parallelepiped shape, a pair of power supply electrodes provided on mutually opposing surfaces of the dielectric element body, and the A pair of ground electrodes provided on a surface orthogonal to the surface on which the pair of power supply electrodes are provided, a resistance layer disposed between one power supply electrode and the dielectric element body, and one end through the resistance layer The first internal electrode is connected to one power supply electrode and the other end is directly connected to the other power supply electrode, and at least a part of one end is connected to the one power supply electrode without a resistance layer. And a second internal electrode whose other end is directly connected to the other power supply electrode and a third internal electrode connected to both the pair of ground electrodes, the first internal electrode and the third internal electrode, Are stacked alternately with a dielectric layer in between, The poles and the third internal electrode, characterized in that the capacitance is larger than the second capacitor portion are alternately laminated by sandwiching a dielectric layer.

  According to the multilayer capacitor in accordance with the present invention, the same effects as those of the multilayer capacitor described above can be achieved. In other words, it is possible to improve the noise removal performance in the high frequency region while suppressing the oscillation of the power supply circuit, and to reduce the size and height. Moreover, ESL can be further reduced by using the power supply electrodes (first internal electrode, second internal electrode) as through electrodes. Therefore, it is possible to further improve the noise removal performance in the high frequency region. Furthermore, according to the multilayer capacitor in accordance with the present invention, by forming the resistance layer only on one power supply electrode side, it is possible to achieve both the formation of the through electrode of the power supply electrode and the high ESR of the first capacitor portion.

  In the multilayer capacitor according to the present invention, the first internal electrode is formed such that the width of the lead portion connected to one power supply electrode through the resistance layer is narrower than the width of the lead portion of the second internal electrode. The width of the one resistance layer is wider than the width of the lead portion of the first internal electrode, narrower than the width of the lead portion of the second internal electrode, and in the stacking direction of the first internal electrode and the second internal electrode. It is preferable that it is formed from the upper end to the lower end along.

  In this way, since the first internal electrode having a narrow lead portion is connected to one power supply electrode via the resistance layer, the first capacitor portion formed by the first internal electrode has an ESR of Get higher. On the other hand, since at least a part of the second internal electrode having a wide lead part is directly connected to both power supply electrodes, the second capacitor part formed by the second internal electrode has a low ESR. Therefore, the ESR of the first capacitor unit can be effectively increased as compared with the ESR of the second capacitor unit. Further, in this case, since the resistance layer only needs to be formed on one power supply electrode side, the resistance layer can be formed relatively easily, and the production efficiency of the multilayer capacitor is improved and the production cost is reduced. It becomes possible.

  According to the present invention, it is possible to improve noise removal performance in a high-frequency region while suppressing oscillation of the power supply circuit, and to reduce the size and height.

1 is a perspective view of a multilayer capacitor according to a first embodiment. It is sectional drawing along the II-II line of FIG. It is sectional drawing along the III-III line of FIG. It is a figure which shows the equivalent circuit of the multilayer capacitor which concerns on 1st Embodiment. It is a figure which shows the impedance characteristic of the multilayer capacitor which concerns on 1st Embodiment. It is a perspective view of the multilayer capacitor concerning a 2nd embodiment. It is sectional drawing along the VII-VII line of FIG. It is sectional drawing along the VIII-VIII line of FIG. It is sectional drawing along the IX-IX line of FIG.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

(First embodiment)
First, the configuration of the multilayer capacitor 1 according to the first embodiment will be described with reference to FIGS. Here, FIG. 1 is a perspective view showing the appearance of the multilayer capacitor 1. 2 is a cross-sectional view taken along line II-II in FIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III in FIG. FIG. 4 is a diagram showing an equivalent circuit of the multilayer capacitor 1.

  The multilayer capacitor 1 includes a rectangular parallelepiped dielectric element (laminate) 10 and a pair of power supply electrodes (external electrodes) provided on the side surfaces 10b and 10c of the dielectric element 10 facing each other in the short direction. ) 20, 21 and a pair of ground electrodes (external electrodes) 40, 41 provided on the side surfaces 10d, 10e in the longitudinal direction orthogonal to the side surfaces 10b, 10c.

The dielectric body 10 includes a plurality of rectangular dielectric layers 10a and a plurality of first internal electrodes 51, second internal electrodes 52A, 52B, and third internal electrodes 53A, 53B, 53C alternately. It is configured by being laminated. The dielectric layer 10a is formed of, for example, a dielectric ceramic mainly composed of BaTiO ₃ , CaTiO ₃ , SrTiO ₃ , CaZrO ₃ or the like. Note that subcomponents such as a Mn compound, Fe compound, Cr compound, Co compound, and Ni compound may be added to these main components.

  Each of the first internal electrode 51, the second internal electrodes 52A, 52B, and the third internal electrodes 53A, 53B, 53C is formed in a rectangular thin film shape. Each of the first internal electrode 51, the second internal electrodes 52A, 52B, and the third internal electrodes 53A, 53B, 53C is made of, for example, Ni, Cu, Ag, Pd, an Ag—Pd alloy, Au, or the like.

  The first internal electrodes 51 and the third internal electrodes 53C are alternately stacked so as to face each other across the dielectric layer 10a. The first capacitor portion 5 is formed by the first internal electrode 51, the third internal electrode 53C, and the dielectric layer 10a. Similarly, the second internal electrodes 52A and 52B and the third internal electrodes 53A and 53B are alternately stacked so as to face each other with the dielectric layer 10a interposed therebetween. These second internal electrodes 52A and 52B, third internal electrodes 53A and 53B, and dielectric layer 10a form second capacitor portions 6A and 6B.

  The first internal electrode 51 is drawn out to one side surface 10b in the short direction of the dielectric body 10, and the second internal electrodes 52A and 52B are drawn out to the other side surface 10c in the short direction. The third internal electrodes 53A, 53B, 53C are drawn out to both side surfaces 10d, 10e in the longitudinal direction of the dielectric body 10.

  On one side surface 10b in the short direction of the dielectric element body 10, a resistance layer 30 is formed so as to cover all the lead portions 51a of the first internal electrode 51 drawn out to the side surface 10b. Note that no resistive layer is formed on the other short side surface 10c and the long side surfaces 10d and 10e of the dielectric body 10.

  Here, the resistance layer 30 is formed by baking a resistance paste containing a resistance component. As the resistance component, for example, a composite oxide such as In—Sn composite oxide (ITO), La—Cu composite oxide, Sr—Fe composite oxide, or Ca—Sr—Ru composite oxide is used. Further, for example, glass such as B—Si glass or B—Si—Zn glass is added to the resistance layer 30. Furthermore, the resistivity or the like may be adjusted by adding a metal such as Ni, Cu, Mo, Cr, or Nb, or a metal oxide such as Al 2 O 3, TiO 2, ZrO 2, or ZnO 2 to the resistance layer 30.

  As described above, the pair of power supply electrodes 20 and 21 are formed on both side surfaces 10b and 10c of the dielectric element body 10 in the short direction. The power supply electrode 20 is connected to the lead portion 51 a of the first internal electrode 51 through the resistance layer 30. On the other hand, the power supply electrode 21 is directly connected to the entire lead portions 52a and 52b of the second internal electrodes 52A and 52B.

  Further, as described above, a pair of ground electrodes 40 and 41 are formed on both side surfaces 10d and 10e in the longitudinal direction of the dielectric body 10, respectively. Each of the pair of ground electrodes 40, 41 is directly connected to the entire lead portions 53a, 53b, 53c of the third internal electrodes 53A, 53B, 53C.

  Here, each of the power supply electrodes 20 and 21 and the ground electrodes 40 and 41 is preferably composed of a plurality of plating layers. For example, the nickel plating layer having resistance to solder erosion and the nickel plating layer are covered. And a tin plating layer formed.

  The first capacitor part 5 formed by the first internal electrode 51, the third internal electrode 53C, and the dielectric layer 10a connected to the power supply electrode 20 through the resistance layer 30 is directly connected to the power supply electrode 21. The capacitance is larger than the second capacitor portions 6A and 6B formed by the second internal electrodes 52A and 52B, the third internal electrodes 53A and 53B, and the dielectric layer 10a. Therefore, hereinafter, the first capacitor unit 5 is also referred to as a large-capacitance capacitor unit 5, and the second capacitor units 6A and 6B are also referred to as small-capacitance capacitor units 6A and 6B. The capacitances of the first capacitor unit 5 and the second capacitor units 6A and 6B are, for example, the first internal electrode 51, the second internal electrodes 52A and 52B, and the third internal electrodes 53A, 53B, and 53C, respectively. It can be adjusted by changing the area, the number of stacked layers, the thickness of the dielectric layer 10a, the dielectric constant, and the like.

  By being configured as described above, the large-capacity capacitor unit 5 formed by the first internal electrode 51, the third internal electrode 53C, and the dielectric layer 10a has the first internal electrode 51 interposed through the resistance layer 30. Since it is connected to the power supply electrode 20, as shown in FIG. 4, the resistance component R1 is inserted in series with the capacitance component C1, and the value of ESR increases. On the other hand, in the small-capacitance capacitor portions 6A and 6B formed by the second internal electrodes 52A and 52B and the third internal electrodes 53A and 53B, the second internal electrodes 52A and 52B are directly connected to the power supply electrode 21. Therefore, the value of ESR is smaller than that of the large-capacitance capacitor unit 5.

  In addition, since each of the pair of ground electrodes 40 and 41 is directly connected to each of the third internal electrodes 53A, 53B, and 53C, there are two paths from the power supply electrodes 20 and 21 to the ground electrodes 40 and 41. The ESL is reduced in both the large-capacity capacitor unit 5 and the small-capacitance capacitor units 6A and 6B (see FIG. 4).

  As a result of the above configuration, the first capacitor unit (large-capacitance capacitor unit) 5 having a large capacity, a high ESR, and a low ESL, and two Small capacitor, low ESR, and low ESL second capacitor portions (small capacitor portions) 6A and 6B are formed. Here, it is preferable that the first capacitor portion (large-capacity capacitor portion) 5 is adjusted such that the capacitance component is several μ to several tens μF and the ESR is about several hundred m to several thousand mΩ. On the other hand, the second capacitor portions (small-capacitance capacitor portions) 6A and 6B are preferably adjusted to have a capacitance component of several tens of n to several hundreds of nF and an ESR of several tens of mΩ. In the present embodiment, the second capacitor portion (small-capacitance capacitor portion) 6A, the first capacitor portion (large-capacitance capacitor portion) 5, the second capacitor portion (small-capacitance capacitor) are arranged along the stacking direction of the dielectric layer 10a and the like. Part) 6B in this order.

  Here, an example of the impedance characteristic of the multilayer capacitor 1 is shown in FIG. The horizontal axis of the graph shown in FIG. 5 is frequency (Hz), and the vertical axis is impedance (Ω). Here, the capacitance C of the large-capacitance capacitor unit 5 is 10 (μF), the ESR is 500 (mΩ), the ESL is 100 (pH), and the capacitance C of the small-capacitance capacitor units 6A and 6B is 0.1 (μF). ), ESR was 20 (mΩ), and ESL was 100 (pH). As shown in FIG. 5, according to the multilayer capacitor 1 according to the present embodiment, the impedance is relatively large in the frequency region of 0.1 to 10 (MHz), and the impedance is compared in the frequency region of 50 (MHz) or higher. It was confirmed that a small characteristic can be obtained.

  As described above in detail, according to this embodiment, two capacitor parts having different capacitances and ESRs, that is, a large capacity, a high ESR, and a low ESL, are included in one dielectric body 10. One capacitor portion (large-capacity capacitor portion) 5 and second capacitor portions (small-capacitance capacitor portions) 6A and 6B having small capacitance, low ESR, and low ESL are formed. Therefore, for example, when used as a smoothing capacitor for a power supply circuit such as a DC-DC converter, the oscillation of the power supply circuit is suppressed by the first capacitor unit 5 having a large capacity and a high ESR, and a small capacity, a low ESR, and a low capacity. Noise in the high frequency region is reduced by the second capacitor portions 6A and 6B of the ESL. In addition, according to the present embodiment, since the capacitor portions 5, 6A, 6B having different electrostatic capacities (ESC) and ESR are formed in one dielectric element body 10, the size and the height can be reduced. Can do. As a result, according to the present embodiment, it is possible to improve the noise removal performance in the high frequency region while suppressing the oscillation of the power supply circuit, and to reduce the size and height.

(Second Embodiment)
Next, the configuration of the multilayer capacitor 2 according to the second embodiment will be described with reference to FIGS. Here, FIG. 6 is a perspective view showing the appearance of the multilayer capacitor 2. 7 is a cross-sectional view taken along line VII-VII in FIG. 6, and FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 6-9, the same code | symbol is attached | subjected about the component same or equivalent to 1st Embodiment.

  The multilayer capacitor 2 mainly includes a first resistance layer 31 having a different shape (details will be described later) instead of the resistance layer 30 described above, and between the power supply electrode 23 and the dielectric element body 11. The point that the second resistance layer 32 is further formed, and the point that the first internal electrode 55 and the second internal electrodes 56A and 56B are through electrodes, that is, the first internal electrode 51 instead of the first internal electrode 51. This is different from the multilayer capacitor 1 described above in that the electrode 55 is used and the second internal electrodes 56A and 56B are used instead of the second internal electrodes 52A and 52B.

  The multilayer capacitor 2 includes a rectangular parallelepiped dielectric element (laminate) 11 and a pair of power supply electrodes (external electrodes) provided on the lateral sides 11b and 11c of the dielectric element 11 facing each other. ) 22 and 23 and a pair of ground electrodes (external electrodes) 40 and 41 provided on the side surfaces 10d and 10e in the longitudinal direction orthogonal to the side surfaces 11b and 11c, respectively.

  The dielectric body (stacked body) 11 includes a plurality of rectangular dielectric layers 11a, a plurality of first internal electrodes 55, second internal electrodes 56A and 56B, and third internal electrodes 53A, 53B, and 53C. Are alternately stacked.

  Each of the first internal electrode 55, the second internal electrodes 56A, 56B, and the third internal electrodes 53A, 53B, 53C is formed in a rectangular thin film shape. The first internal electrodes 55 and the third internal electrodes 53C are alternately stacked so as to face each other across the dielectric layer 11a. The first capacitor electrode 7 is formed by the first internal electrode 55, the third internal electrode 53C, and the dielectric layer 11a. Similarly, the second internal electrodes 56A and 56B and the third internal electrodes 53A and 53B are alternately stacked so as to face each other with the dielectric layer 11a interposed therebetween. These second internal electrodes 56A and 56B, third internal electrodes 53A and 53B, and dielectric layer 11a form second capacitor portions 8A and 8B.

  The first internal electrode 55 and the second internal electrodes 56 </ b> A and 56 </ b> B are drawn out to both side surfaces 11 b and 11 c in the short direction of the dielectric element body 11. The third internal electrodes 53A, 53B, 53C are drawn out to both side surfaces 10d, 10e in the longitudinal direction of the dielectric body 10.

  The first internal electrode 55 is formed such that the width of the lead portions 55a and 55a at both ends (the length along the short direction of the dielectric body 11) is narrow. On the other hand, the second inner electrodes 56 </ b> A and 56 </ b> B are formed such that the widths of the lead portions 56 a and 56 b are wider than the lead portion 55 a of the first internal electrode 55.

  On both side surfaces 11b and 11c in the short direction of the dielectric body 11, the second internal electrodes are provided so as to cover all the lead portions 55a of the first internal electrodes 55 drawn to the both side surfaces 11b and 11c. The first resistance layer 31 and the second resistance layer 32 are formed so as to cover a part of the lead portions 56a and 56b of 56A and 56B. More specifically, as shown in FIGS. 8 and 9, the first resistance layer 31 and the second resistance layer 32 are wider than the width of the lead portion 55a of the first internal electrode 55, and the second internal electrode. It has a width that is narrower than the widths of the lead portions 56a and 56b of 56A and 56B, and is formed from the upper end to the lower end along the stacking direction of the dielectric body 11.

  As described above, the pair of power supply electrodes 22 and 23 are formed on both side surfaces 11b and 11c in the short direction of the dielectric element body 11, respectively. One power supply electrode 22 is connected to one lead portion 55 a of the first internal electrode 55 through the first resistance layer 31. The other power supply electrode 23 is connected to the other lead portion 55 a of the first internal electrode 55 through the second resistance layer 32.

  One power supply electrode 22 is connected to the central portion of one lead-out portion 56a, 56b of the second internal electrode 56A, 56B via the first resistance layer 31, and the second internal electrode 56A, 56B. It is directly connected to both end portions of the lead portions 56a and 56b. The other power supply electrode 23 is connected to the central portion of the other lead portions 56a and 56b of the second internal electrodes 56A and 56B via the second resistance layer 32, and the lead portion of the second internal electrodes 56A and 56B. It is directly connected to both ends of 56a and 56b.

  Further, as described above, a pair of ground electrodes 40 and 41 are formed on both side surfaces 11d and 11e in the longitudinal direction of the dielectric body 11, respectively. Each of the pair of ground electrodes 40, 41 is directly connected to the entire lead portions 53a, 53b, 53c of the third internal electrodes 53A, 53B, 53C.

  The first internal electrode 55, the third internal electrode 53C, and the dielectric layer 11a connected to the power supply electrode 22 through the first resistance layer 31 and connected to the power supply electrode 23 through the second resistance layer 32. The first capacitor portion 7 formed by the second and second internal electrodes 56A and 56B, the third internal electrodes 53A and 53B, both ends of which are directly connected to the power supply electrode 22 and the power supply electrode 23, and the dielectric layer 11a. The capacitance is larger than that of the second capacitor portions 8A and 8B. Therefore, hereinafter, the first capacitor unit 7 is also referred to as a large-capacitance capacitor unit 7, and the second capacitor units 8A and 8B are also referred to as small-capacitance capacitor units 8A and 8B.

  The capacitances of the first capacitor unit 7 and the second capacitor units 8A, 8B are, for example, the first internal electrode 55, the second internal electrodes 56A, 56B, and the third internal electrodes 53A, 53B, 53C, respectively. It can be adjusted by changing the area, the number of stacked layers, the thickness of the dielectric layer 11a, the dielectric constant, and the like.

  By being configured as described above, in the large-capacity capacitor unit 7 formed by the first internal electrode 55, the third internal electrode 53C, and the dielectric layer 11a, the first internal electrode 55 is connected to the first resistance layer 31. In addition to being connected to the power supply electrode 22 through the second resistance layer 32, the resistance component is inserted in series with respect to the capacitance component, and the value of ESR is large. Become. On the other hand, in the small-capacitance capacitor portions 8A and 8B formed by the second internal electrodes 56A and 56B and the third internal electrodes 53A and 53B, both end portions of the second internal electrodes 56A and 56B are directly connected to the power supply electrode 22 and the power supply. Since it is connected to the electrode 23, the value of ESR is smaller than that of the large-capacitance capacitor unit 7.

  In addition, since each of the pair of ground electrodes 40 and 41 is directly connected to each of the third internal electrodes 53A, 53B, and 53C, there are two paths from the power supply electrodes 22 and 23 to the ground electrodes 40 and 41. The ESL is reduced in both the large-capacitance capacitor unit 7 and the small-capacitance capacitor units 8A and 8B. Furthermore, since the first internal electrode 55 and the second internal electrodes 56A and 56B are through electrodes, the ESL is further reduced in both the large-capacity capacitor unit 7 and the small-capacitance capacitor units 8A and 8B.

  As a result of the above, by configuring as described above, a large capacity, high ESR, low ESL first capacitor section (large capacity capacitor section) 7 and small capacity are formed in one dielectric element body 11. The second capacitor portions (small-capacitance capacitor portions) 8A and 8B having low ESR and low ESL are formed.

  According to this embodiment, the same effect as the multilayer capacitor 1 described above can be obtained. In other words, it is possible to improve the noise removal performance in the high frequency region while suppressing the oscillation of the power supply circuit, and to reduce the size and height. Furthermore, according to the multilayer capacitor 2 according to the present embodiment, the ESL can be further reduced by using the power supply electrodes 22 and 23 (the first internal electrode 55 and the second internal electrodes 56A and 56B) as through electrodes. . Therefore, it is possible to further improve the noise removal performance in the high frequency region.

  Further, according to the present embodiment, the first internal electrode 55 with the narrow width of the lead portion 55a is connected to both the power supply electrodes 22 and 23 via the first resistance layer 31 and the second resistance layer 32. The first capacitor portion 7 formed by the first internal electrode 55 has a high ESR. On the other hand, the second internal electrodes 56A and 56B having the wide lead portions 56a and 56b are formed by the second internal electrodes 56A and 56B because both ends are directly connected to the power supply electrodes 22 and 23. The ESR of the second capacitor portions 8A and 8B is reduced. Therefore, the ESR of the first capacitor unit 7 can be effectively increased as compared with the ESR of the second capacitor units 8A and 8B.

  Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above-described embodiment, two small-capacitance capacitor portions 6A and 6B (8A and 8B) are formed in the dielectric body 10 (11), but the number of small-capacitance capacitor portions to be formed may be one.

  In the second embodiment, the first resistance layer 31 and the second resistance layer 31 are wider than the width of the lead portion 55a of the first internal electrode 55 and narrower than the width of the lead portions 56a and 56b of the second internal electrodes 56A and 56B. The resistance layer 32 is formed from the upper end to the lower end along the stacking direction of the dielectric element body 11, but only the lead portion 55a of the first internal electrode 55 drawn to the side surfaces 11b and 11c of the dielectric element body 11 is provided. You may form the 1st resistance layer 31 and the 2nd resistance layer 32 so that it may cover.

  In the second embodiment, the first resistance layer 31 and the second resistance layer 32 are provided on both side surfaces 10b and 10c of the dielectric element body 11, respectively, but of the both side surfaces 10b and 10c of the dielectric element body 11, It can also be set as the structure which provides a resistance layer only in any one.

1, 2 Multilayer capacitor 5, 7 Large-capacity capacitor (first capacitor)
6A, 6B, 8A, 8B Small capacitor section (second capacitor section)
DESCRIPTION OF SYMBOLS 10,11 Dielectric body 10a, 11a Dielectric layer 20, 21, 22, 23 Power supply electrode 30 Resistance layer 31 1st resistance layer 32 2nd resistance layer 40, 41 Ground electrode 51, 55 1st internal electrode 52A, 52B , 56A, 56B Second internal electrode 53A, 53B, 53C Third internal electrode

Claims (6)

A dielectric element body including a plurality of dielectric layers and formed in a substantially rectangular parallelepiped shape;
A pair of power supply electrodes provided on surfaces of the dielectric element body facing each other, and a pair of ground electrodes provided on a surface orthogonal to the surface provided with the pair of power supply electrodes;
A resistance layer disposed between one of the power supply electrodes and the dielectric body;
A first internal electrode connected to the one power supply electrode through the resistance layer;
A second internal electrode connected to the other power supply electrode;
A third internal electrode connected to both of the pair of ground electrodes,
In the first capacitor portion in which the first internal electrode and the third internal electrode are alternately stacked with the dielectric layer interposed therebetween, the second internal electrode and the third internal electrode sandwich the dielectric layer. The multilayer capacitor is characterized in that the capacitance is larger than that of the second capacitor portions alternately stacked in the section. The pair of power supply electrodes is provided on a lateral side surface of the dielectric body,
The multilayer capacitor according to claim 1, wherein the pair of ground electrodes are provided on a side surface in a longitudinal direction of the dielectric element body. A dielectric element body including a plurality of dielectric layers and formed in a substantially rectangular parallelepiped shape;
A pair of power supply electrodes provided on surfaces of the dielectric element body facing each other, and a pair of ground electrodes provided on a surface orthogonal to the surface provided with the pair of power supply electrodes;
A first resistance layer disposed between one of the power supply electrodes and the dielectric element body; a second resistance layer disposed between the other power supply electrode and the dielectric element body;
A first internal electrode having one end connected to the one power supply electrode via the first resistance layer and the other end connected to the other power supply electrode via the second resistance layer;
At least a part of one end is connected to the one power supply electrode without going through the first resistance layer, and at least a part of the other end is connected to the other power supply electrode without going through the second resistance layer. A second internal electrode;
A third internal electrode connected to both of the pair of ground electrodes,
In the first capacitor portion in which the first internal electrode and the third internal electrode are alternately stacked with the dielectric layer interposed therebetween, the second internal electrode and the third internal electrode sandwich the dielectric layer. The multilayer capacitor is characterized in that the capacitance is larger than that of the second capacitor portions alternately stacked in the section. The first internal electrode is formed such that the width of the lead portion at both ends is narrower than the width of the lead portion of the second internal electrode,
The widths of the first resistance layer and the second resistance layer are wider than the width of the lead portion of the first internal electrode, narrower than the width of the lead portion of the second internal electrode, and the first internal layer The multilayer capacitor according to claim 3, wherein the multilayer capacitor is formed from an upper end to a lower end along a lamination direction of the electrode and the second internal electrode. A dielectric element body including a plurality of dielectric layers and formed in a substantially rectangular parallelepiped shape;
A pair of power supply electrodes provided on surfaces of the dielectric element body facing each other, and a pair of ground electrodes provided on a surface orthogonal to the surface provided with the pair of power supply electrodes;
A resistance layer disposed between one of the power supply electrodes and the dielectric body;
A first internal electrode having one end connected to the one power supply electrode through the resistance layer and the other end directly connected to the other power supply electrode;
A second internal electrode in which at least a part of one end is connected to the one power supply electrode without passing through the resistance layer, and the other end is directly connected to the other power supply electrode;
A third internal electrode connected to both of the pair of ground electrodes,
In the first capacitor portion in which the first internal electrode and the third internal electrode are alternately stacked with the dielectric layer interposed therebetween, the second internal electrode and the third internal electrode sandwich the dielectric layer. The multilayer capacitor is characterized in that the capacitance is larger than that of the second capacitor portions alternately stacked in the section. The first internal electrode is formed such that the width of the lead portion connected to the one power supply electrode via the resistance layer is narrower than the width of the lead portion of the second internal electrode,
The resistance layer has a width wider than a width of the lead portion of the first internal electrode, narrower than a width of the lead portion of the second internal electrode, and the first and second internal electrodes. 6. The multilayer capacitor according to claim 5, wherein the multilayer capacitor is formed from the upper end to the lower end along the lamination direction.

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