JP6935707B2 - Multilayer ceramic capacitors - Google Patents

Description

The present invention relates to a multilayer ceramic capacitor and a method for manufacturing a multilayer ceramic capacitor.

Since the monolithic ceramic capacitor has a low equivalent series resistance (ESR), when it resonates in the high frequency range, it may exceed the impedance that is the reference of the circuit. Therefore, as a multilayer ceramic capacitor compatible with high frequencies, there is a multilayer ceramic capacitor (also referred to as a capacitor with a resistor) to which a resistor is connected. The first resistor-equipped capacitor contains, for example, a conductive substance and glass on the surface of an element body in which dielectric layers (also referred to as ceramic layers) and internal electrode layers are alternately laminated, and functions as a resistance electrode layer. A laminated ceramic capacitor having an external terminal electrode electrically connected to an internal electrode layer by directly forming a conductive layer and forming a second conductive layer containing metal and glass on the surface of the first conductive layer. (For example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2004-128328

However, the multilayer ceramic capacitor described in Patent Document 1 has a problem that the connectivity between the internal electrode layer of the element body and the external electrode is not stable. It is considered that this is due to the presence of irregularities on the surface of the internal electrode layer exposed on the surface of the element body.
In the multilayer ceramic capacitor described in Patent Document 1, a paste for a first conductive layer is applied to the surface of the element body and heat-treated to form a first conductive layer that functions as a resistance electrode layer. However, there are irregularities on the surface of the internal electrode layer that comes into contact with the first conductive layer. The first conductive layer formed by heat-treating the paste for the first conductive layer does not have sufficient followability to the unevenness of the surface of the internal electrode layer. As a result, the adhesion between the first conductive layer produced by using the paste for the first conductive layer and the internal electrode layer of the element body varies, and the connectivity is not stable.

Further, the electrode formed by baking the conductive paste may have variations in contact with the internal electrode layer due to the influence of components other than the conductive component contained in the conductive paste. The first conductive layer functions as a resistance electrode layer, but if a region having low resistance is partially formed due to variations in the contact property between the internal electrode layer and the first conductive layer, the current concentrates in that region. Therefore, there is a problem that it becomes difficult to control the resistance value of the entire ceramic capacitor.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a monolithic ceramic capacitor having stable connectivity between an internal electrode layer and an external electrode.

The multilayer ceramic capacitor of the present invention includes a substantially rectangular laminate having a plurality of laminated ceramic layers and a plurality of internal electrode layers, and having two or more exposed regions where the plurality of internal electrode layers are exposed. An external electrode covering the exposed region is provided, and at least one of the external electrodes is an external electrode with resistance, and the internal electrode layer is laminated with a first internal electrode layer and the first internal electrode layer. The external electrode with resistance has a second internal electrode layer facing each other in the direction, and the external electrode with resistance includes a thin film electrode layer that directly contacts the internal electrode layer in the exposed region and a resistance electrode provided on the thin film electrode layer. It is characterized by including a layer and an upper electrode layer having an electric resistance smaller than that of the resistance electrode layer provided on the resistance electrode layer.

In the multilayer ceramic capacitor of the present invention, it is preferable that the thin film electrode layer is arranged in the plane where the exposed region is formed in the laminated body.

In the multilayer ceramic capacitor of the present invention, it is preferable that the resistance electrode layer is arranged in the plane of the laminate in which the exposed region is formed.

In the multilayer ceramic capacitor of the present invention, the laminate is orthogonal to the first end face and the second end face facing the first end face, the first end face and the second end face, and faces each other. It has a first side surface and a second side surface, and the first internal electrode layer is exposed on the first end surface and the second end surface, and the first side surface and the second side surface are exposed. The second internal electrode layer is exposed on the side surface of the above, and the external electrode covering the exposed region where the first internal electrode layer is exposed on the first end face and the second end face is the resistance. It is preferably an external electrode.

In the multilayer ceramic capacitor of the present invention, it is preferable that the external electrode covering the exposed region where the second internal electrode layer is exposed on the first side surface and the second side surface is a low resistance external electrode.

In the multilayer ceramic capacitor of the present invention, the thin film electrode layer is preferably a plated electrode.

The method for manufacturing a multilayer ceramic capacitor of the present invention comprises a substantially rectangular laminate having a plurality of laminated ceramic layers and a plurality of internal electrode layers, and having two or more exposed regions where the plurality of internal electrode layers are exposed. A laminate forming step to be formed and a coating step of covering the exposed region with an external electrode are provided, and the coating step includes a thin film electrode layer, a resistance electrode layer provided on the thin film electrode layer, and the resistance electrode. It has a first coating step of covering at least one of the exposed regions with a resistant external electrode having an upper electrode layer having an electric resistance smaller than that of the resistance electrode layer provided on the layer, and the first coating. The process is characterized in that a thin film electrode layer is formed directly on the exposed internal electrode layer.

In the method for manufacturing a multilayer ceramic capacitor of the present invention, it is preferable to form the thin film electrode layer by a plating method.

In the method for manufacturing a multilayer ceramic capacitor of the present invention, in the laminate forming step, the first exposed region of the internal electrode layer is exposed and the first exposed region is opposed to the first exposed region. The surface of the laminate is the second exposed region, the third exposed region where the second internal electrode layer of the internal electrode layers is exposed, and the fourth exposed region facing the third exposed region. The first coating step includes a step of directly forming the thin film electrode layer on the first internal electrode layer exposed to the first exposed region and the second exposed region, and the coating The step preferably further includes a second coating step of directly forming a low resistance external electrode on the second internal electrode layer exposed in the third exposed region and the fourth exposed region.
The order of the first coating step and the second coating step is not particularly limited.

In the method for manufacturing a multilayer ceramic capacitor of the present invention, the first coating step includes a first firing step of applying a resistance electrode paste on the thin film electrode layer and then firing to form the resistance electrode layer. A second firing step of applying the upper layer electrode paste on the resistance electrode layer and then firing to form the upper electrode layer is included, and the maximum temperature in the first firing step is the highest in the second firing step. It is preferably higher than the temperature.

In the method for manufacturing a multilayer ceramic capacitor of the present invention, the second coating step is a low resistance external electrode paste on the second internal electrode layer exposed to the third exposed region and the fourth exposed region. It is preferable to include a third firing step of firing after coating.

In the method for manufacturing a multilayer ceramic capacitor of the present invention, it is preferable that the maximum temperature in the third firing step is higher than the maximum temperature in the first firing step.

According to the present invention, it is possible to provide a monolithic ceramic capacitor having stable connectivity between an internal electrode layer and an external electrode layer, and a method for manufacturing the same.

FIG. 1 is a perspective view schematically showing an example of a laminated body constituting the multilayer ceramic capacitor of the present invention. FIG. 2 is a perspective view schematically showing an example of the multilayer ceramic capacitor of the present invention. FIG. 3A is a cross-sectional view schematically showing an example of the LT cross section of the multilayer ceramic capacitor shown in FIG. 2, and FIG. 3B is a schematic cross-sectional view showing an example of the WT cross section of the multilayer ceramic capacitor shown in FIG. It is sectional drawing which shows. FIG. 4 is an enlarged cross-sectional view of a region in the vicinity of the external electrode with resistance surrounded by a broken line in FIG. 3A. FIG. 5 is an explanatory diagram schematically showing the states of the internal electrode layer, the thin film electrode layer, and the laminated body of the first end face shown in FIG. FIG. 6 is an LT cross-sectional view schematically showing another example of the multilayer ceramic capacitor of the present invention.

Hereinafter, the method for manufacturing the multilayer ceramic capacitor of the present invention and the multilayer ceramic capacitor of the present invention will be described with reference to the drawings.
However, the present invention is not limited to the following configurations, and can be appropriately modified and applied without changing the gist of the present invention. It should be noted that a combination of two or more individual desirable configurations of the present invention described below is also the present invention.

[Multilayer ceramic capacitor]
Hereinafter, an example of the multilayer ceramic capacitor of the present invention including the laminate and the external electrode will be described.
First, the laminate and the external electrode constituting the multilayer ceramic capacitor of the present invention will be described with reference to FIGS. 1 and 2.
FIG. 1 is a perspective view schematically showing an example of a laminated body constituting the multilayer ceramic capacitor of the present invention. FIG. 2 is a perspective view schematically showing an example of the multilayer ceramic capacitor of the present invention.

In the laminated ceramic capacitor and the laminated body of the present invention, the length direction, the width direction, and the laminated body are the directions defined by double-headed arrows L, W, and T in the laminated body 10 shown in FIG. 1 and the laminated ceramic capacitor 1 shown in FIG. 2, respectively. And. Here, the length direction, the width direction, and the stacking direction are orthogonal to each other. The stacking direction is a direction in which the plurality of ceramic layers 20 and the plurality of internal electrode layers 30 constituting the laminated body 10 are stacked.
In the laminated body 10 shown in FIG. 1 and the laminated ceramic capacitor 1 shown in FIG. 2, the dimension in the length direction is longer than the dimension in the width direction. However, in the multilayer ceramic capacitor and the laminate of the present invention, the magnitude relationship between the dimension in the length direction and the dimension in the width direction is not particularly limited, and the dimension in the length direction may be larger or smaller than the dimension in the width direction. You may.

The laminated body 10 has a substantially rectangular parallelepiped shape having six surfaces, and has a plurality of laminated ceramic layers 20 and a plurality of internal electrode layers 30. The laminated body 10 has a width indicated by a double-headed arrow W that is orthogonal to the first main surface 11 and the second main surface 12 facing the stacking direction T indicated by the double-headed arrow T in FIG. The first side surface 13 and the second side surface 14 facing the direction W, and the first end face 15 and the second end face 15 and the second side surface 15 and the second side surface facing the length direction L indicated by the double-headed arrow L, which are orthogonal to the stacking direction T and the width direction W. The end face 16 and the like are included.

In the present specification, the cross section of the laminated body 10 orthogonal to the first end surface 15 and the second end surface 16 and parallel to the laminating direction of the laminated body 10 is referred to as an LT cross section. Further, a cross section of the laminated body 10 orthogonal to the first side surface 13 and the second side surface 14 and parallel to the laminating direction of the laminated body 10 is referred to as a WT cross section.
Further, a cross section of the laminated body 10 orthogonal to the first side surface 13, the second side surface 14, the first end surface 15 and the second end surface 16 and orthogonal to the laminating direction of the laminated body 10 is referred to as an LW cross section.

The ceramic layer 20 includes an outer layer portion 21 and an inner layer portion 22. The outer layer portion 21 is a ceramic layer located on both main surface sides of the laminated body 10 and located between the main surface and the inner electrode layer closest to the main surface. The region sandwiched between the outer layer portions 21 is the inner layer portion 22.

In the multilayer ceramic capacitor 1 shown in FIG. 2, the end faces (first end face 15 and second end face 16) of the laminate 10 shown in FIG. 1 are external electrodes with resistance, and external electrodes 100 with resistance (hereinafter, simply external electrodes with resistance). It is covered with a low resistance external electrode 200 (hereinafter, simply referred to as a low resistance external electrode) among the external electrodes, and a part of the side surfaces (first side surface 13 and second side surface 14) of the laminated body 10 is covered with the external electrodes. Also called).
In the multilayer ceramic capacitor of the present invention, at least one of the external electrodes covering the exposed region may be an external electrode with resistance, and the other external electrode may be an external electrode with resistance or a low resistance external electrode. good.

Subsequently, the ceramic layer and the internal electrode layer constituting the multilayer ceramic capacitor of the present invention will be described with reference to FIGS. 3 (a) and 3 (b).
FIG. 3A is a cross-sectional view schematically showing an example of the LT cross section of the multilayer ceramic capacitor shown in FIG. 2. FIG. 3A is also a cross-sectional view taken along the line AA in FIG. FIG. 3B is a cross-sectional view schematically showing an example of a WT cross section of the multilayer ceramic capacitor shown in FIG. FIG. 3B is also a cross-sectional view taken along the line BB in FIG.
As shown in FIGS. 3A and 3B, the plurality of internal electrode layers 30 include a laminated first internal electrode layer 35 and a second internal electrode layer 36. The first internal electrode layer 35 is exposed to the first end surface 15 and the second end surface 16, and the second internal electrode layer 36 is exposed to the first side surface 13 and the second side surface 14. Capacitance is generated at the counter electrode portion where the first internal electrode layer 35 and the second internal electrode layer 36 face each other with the ceramic layer 20 interposed therebetween.

The exposed region where the first internal electrode layer 35 is exposed is covered with the external electrode 100 with resistance. The external electrode 100 with resistivity includes a thin film electrode layer 61 that is in direct contact with the internal electrode layer 30 (first internal electrode layer 35), a resistance electrode layer 62 provided on the thin film electrode layer 61, and a resistance electrode layer 62. It is composed of an upper electrode layer 63 having an electric resistivity smaller than that of the resistance electrode layer 62 provided in the above.

The first internal electrode layer 35 has a counter electrode portion facing the second internal electrode layer 36 with the ceramic layer 20 interposed therebetween, and a drawer drawn from the counter electrode portion to the first end surface 15 or the second end surface 16. It has an electrode portion, and a region on which the first internal electrode layer 35 is exposed is formed on the first end surface 15 and the second end surface 16.
The region where the first internal electrode layer 35 (drawing electrode portion) is exposed on the first end surface 15 is defined as the first exposed region, and the first internal electrode layer 35 (drawing electrode portion) is the second end surface 16 The area exposed to the surface is defined as the second exposed area.

The second internal electrode layer 36 is formed on a counter electrode portion facing the counter electrode portion of the first internal electrode layer 35 with the ceramic layer 20 interposed therebetween, and on the first side surface 13 or the second side surface 14 from the counter electrode portion. It has a drawer electrode portion that is pulled out and exposed, and a third exposed region is formed on the first side surface 13 from which the second internal electrode layer 36 is exposed, and the second side surface 14 has a third exposed region. A fourth exposed region is formed in which the second internal electrode layer 36 is exposed. The third exposed region and the fourth exposed region are each covered with a low resistance external electrode 200 having no resistance electrode layer.

FIG. 4 is an enlarged cross-sectional view of a region in the vicinity of the external electrode with resistance surrounded by a broken line in FIG. 3A.
As shown in FIG. 4, in the exposed region where the first internal electrode layer 35 is exposed, the first internal electrode layer 35 is in direct contact with the thin film electrode layer 61. The first exposed region where the first internal electrode layer 35 is exposed on the first end surface 15 is a region including two first internal electrode layers 35 formed on the outermost side (double-headed arrow X in FIG. 4). Area indicated by _2). In contrast, (in FIG. 4, the area indicated by the double arrow X ₃₎ area thin film electrode layer 61 is formed, it is preferable that completely covers the first exposed region.
The distance from the edge line of the stack to the thin-film electrode layer 61, a predetermined length (in FIG. 4, the length indicated by double-headed arrow X ₁₎ are separated by, first from ridge portions of the laminate the distance to the exposed regions are separated by a predetermined length (in FIG. 4, the length indicated by the double arrow X _4).

Subsequently, an exposed region where the internal electrode layer is exposed on the end face of the laminated body and a thin film electrode layer formed on the exposed region will be described with reference to FIG.
FIG. 5 is an explanatory view schematically showing the states of the internal electrode layer 30, the thin film electrode layer 61, and the laminated body of the first end face shown in FIG. In FIG. 5, the region where the thin film electrode layer is formed is indicated by a chain double-dashed line.
As shown in FIG. 5, the region where the first internal electrode layer 35 is exposed is abbreviated as indicated by _{a double-headed arrow X 2W extending in the width direction (W direction) and a double-headed arrow X 2T} extending in the stacking direction (T direction). It is a rectangular area. This area is the first exposed area.
The thin film electrode layer 61 is formed so as to cover the first exposed region (in FIG. 5, the region covered by the thin film electrode layer 61 is indicated by a chain double-dashed line). The region in which the thin film electrode layer 61 is formed is a substantially rectangular region indicated by _{a double-headed} arrow X 3W extending in the width direction (W direction) and a double- _{headed arrow X 3T} extending in the stacking direction (T direction). It completely covers the exposed area of 1.
When the thin film electrode layer 61 completely covers the first exposed region, the contact resistance between the first internal electrode layer 35 and the thin film electrode layer 61 is reduced.

The length from the second main surface 12 to the first internal electrode layer 35 is indicated _{by X 4T.} The length indicated by the double- _{headed arrow X 4T} is also called the T gap. On the other hand, the length from the first side surface 13 to the first internal electrode layer 35 is indicated by the double-headed arrow X _4W . The length indicated by the double- _{headed arrow X 4W} is also referred to as a W gap.

The distance from the second main surface 12 to the thin film electrode layer 61 is indicated by the double- _headed arrow X 1T. If the length indicated by _{X 1T is smaller than the length indicated by X 4T} , the thin film electrode layer 61 can cover the entire first exposed region in the T direction, which is preferable. Furthermore, the length indicated by _{X 1T is 1/3 or more of the length indicated by X 4T} (that is, the distance from the second main surface 12 to the thin film electrode layer 61 is 1/3 or more of the T gap). It is preferably 1/2 or more, and further preferably 9/10 or more. The same applies to the distance from the first main surface 11 to the thin film electrode layer 61.

The distance from the first side surface 13 to the thin film electrode layer 61 is indicated by the double-headed arrow X _1W . If the length represented by _{X 1W is smaller than the length represented by X 4W} , the thin film electrode layer 61 can cover the entire first exposed region in the W direction, which is preferable. Furthermore, the length indicated by _{X 1W is 1/3 or more of the length indicated by X 4W} (that is, the distance from the first side surface 13 to the thin film electrode layer 61 is 1/3 or more of the W gap). It is preferably ½ or more, more preferably 9/10 or more, and even more preferably 9/10 or more. The same applies to the distance from the second side surface 14 to the thin film electrode layer 61.
When the distance from the side surface or main surface of the laminated body to the thin film electrode layer is 9/10 or more of the W gap or the T gap, respectively, the thin film electrode layer 61 is near the ridgeline portion of the laminated body 10 (hereinafter, also referred to as an edge portion). ), Therefore, the thickness of the resistance electrode layer formed on the thin film electrode layer is less likely to be affected by variations in the edge portion.

However, as shown in FIG. 6, in the multilayer ceramic capacitor of the present invention, the thin film electrode layer 61 may completely cover the first end surface 15, and a part of the thin film electrode layer 61 turns to another surface. It may be crowded.
FIG. 6 is an LT cross-sectional view schematically showing another example of the multilayer ceramic capacitor of the present invention. In the multilayer ceramic capacitor shown in FIG. 6, on the first main surface 11 and the second main surface 12 so that a part of the thin film electrode layer 61 formed on the first end surface 15 protrudes from the first end surface 15. It is formed by wrapping around.

In the present specification, the first internal electrode layer is exposed on the first end surface 15 and the second end surface 16, and the second internal electrode layer is exposed on the first side surface 13 and the second side surface 14. Although the multilayer ceramic capacitor using the laminate has been described, the laminate constituting the multilayer ceramic capacitor of the present invention is not limited to the laminate having the above configuration. For example, the first internal electrode layer 35 is exposed on the first end surface 15, the second internal electrode layer 36 is exposed on the second end surface, and the internal electrode layer is exposed on the first side surface 13 and the second side surface 14. Even if an unexposed laminate was used, the exposed areas exposed on the first end face 15 and / or the second end face 16 were covered with external electrodes, and at least one of them was designated as the external electrode 100 with resistance. The one is the multilayer ceramic capacitor of the present invention.

The laminated body 10 preferably has rounded corners and ridges. The corner portion is a portion where the three surfaces of the laminated body intersect, and the ridge portion is a portion where the two surfaces of the laminated body intersect.
The distance from the ridgeline portion to the thin film electrode layer is the distance from the ridgeline portion on the assumption that the ridgeline portion is not rounded even if the ridgeline portion is rounded.

The length of the laminate 10 in the L direction is preferably 0.4 mm or more and 5.7 mm or less, more preferably 0.46 mm or more and 4.6 mm or less, and 0.46 mm or more and 3.2 mm or less. Is even more preferable. The length of the laminate 10 in the W direction is preferably 0.2 mm or more and 5.0 mm or less, more preferably 0.28 mm or more and 2.75 mm or less, and 0.28 mm or more and 2.5 mm or less. Is even more preferable. The length of the laminate 10 in the T direction is preferably 0.19 mm or more and 2.7 mm or less, more preferably 0.2 mm or more and 2.5 mm or less, and 0.2 mm or more and 1.95 mm or less. Is even more preferable.

The number of ceramic layers is preferably 50 or more and 600 or less, and more preferably 100 or more and 600 or less. The number of ceramic layers does not include the number of ceramic layers constituting the outer layer portion.
The thickness of each ceramic layer constituting the inner layer portion of the ceramic layers is preferably 0.4 μm or more and 3.0 μm or less. The thickness of the outer layer portion is preferably 20 μm or more and 80 μm or less on one side, and more preferably 30 μm or more and 80 μm or less.
Each dimension of the laminate as described above can be measured with a micrometer, and the number of ceramic layers can be counted with an optical microscope.

Each ceramic layer contains at least one selected from the group consisting of Sr and Ca in addition to Ba, which is represented by the general formula AmBO _{3 (A site is Ba) represented by barium titanate (BaTIO 3).} The B site may be Ti, and may contain at least one selected from the group consisting of Zr and Hf in addition to Ti. O is oxygen. M is the molar ratio of A site to B site.) The represented perovskite type compound can be preferably used. Further, a ceramic material containing calcium titanate (CaTIO ₃ ), strontium titanate (SrTiO ₃ ), calcium zirconate (CaZrO ₃ ) or the like as a main component may be used. Further, each ceramic layer may contain Mn, Mg, Si, Co, Ni, V, Al, a rare earth element or the like as an auxiliary component having a content smaller than that of the main component.

The internal electrode layer preferably contains a metal material such as Ni, Cu, Ag, Pd, Ag—Pd alloy or Au. It is also preferable that the ceramic layer contains a dielectric material having the same composition as the ceramic material.

The number of internal electrode layers is preferably 50 or more and 600 or less, and more preferably 100 or more and 600 or less. The average thickness of the internal electrode layer is preferably 0.3 μm or more and 1.0 μm or less.

In the multilayer ceramic capacitor of the present invention, all of the external electrodes covering the exposed region where the first internal electrode layer is exposed, or all of the external electrodes covering the exposed region where the second internal electrode layer is exposed are external electrodes with resistance. Is preferable.
When there are two or more exposed areas where the first internal electrode layer is exposed, and one or more of them is covered with an external electrode which is not an external electrode with resistance, the exposed area where the first internal electrode layer is exposed. Of these, the current preferentially flows to the exposed region covered by the external electrode, which is not the external electrode with resistance, and it becomes difficult to design the resistance value of the multilayer ceramic capacitor as a whole. The same applies to the exposed region where the second internal electrode layer is exposed.

In the multilayer ceramic capacitor of the present invention, the exposed region is covered with an external electrode.
Examples of the external electrode include an external electrode with resistance and an external electrode with low resistance.
The external electrode with resistance includes a thin film electrode layer, a resistance electrode layer, and an upper electrode layer having a resistivity smaller than that of the resistance electrode layer. The external electrode with resistance covers at least one of the exposed regions formed in the laminate. The thin film electrode layer is in direct contact with the first internal electrode layer or the second internal electrode layer, the resistance electrode layer is provided on the thin film electrode layer, and the upper electrode layer is provided on the resistance electrode layer. ing.

In the multilayer ceramic capacitor of the present invention, at least one of the external electrodes covering the exposed region where the internal electrode layer is exposed is an external electrode with resistance composed of a thin film electrode layer, a resistance electrode layer and an upper electrode layer. The internal electrode layer is exposed in the exposed region, and the thin film electrode layer is in direct contact with the internal electrode layer.
When considering the equivalent circuit of the multilayer ceramic capacitor of the present invention, it can be considered that the wirings from the plurality of capacitor element portions, which are grouped together by the thin film electrode layer, are connected to the resistance electrode layer. On the other hand, when the internal electrode layer is in direct contact with the resistance electrode layer, it can be considered that a plurality of circuits in which the capacitor element portion and the resistance element portion are connected in series are connected in parallel. Therefore, in the multilayer ceramic capacitor of the present invention, it is considered that the connectivity is stable as compared with the case where the internal electrode layer is in direct contact with the resistance electrode layer.

The thin film electrode layer preferably has an electrical resistivity of 1.65 × 10 ^-6 Ω · cm or more and 1.65 × 10 ^-4 Ω · cm or less. Further, the thin film electrode layer preferably has a lower electrical resistivity than the resistance electrode layer.
The thin film electrode layer is an atomic layer on which atoms are deposited, unlike a layer on which a conductive paste is baked, and can be formed by a thin film forming method such as plating, sputtering, or vapor deposition. In these methods, the thin film electrode layer having a desired thickness can be formed while suppressing the variation in the thickness of the thin film electrode layer.
From the viewpoint of electrical resistivity, adhesiveness, ease of manufacture, etc. of the thin film electrode layer, a plated electrode formed by plating is preferable.
The thin film electrode layer formed by the plating method is also referred to as a plating electrode, the thin film electrode layer formed by sputtering is referred to as a sputtering electrode, and the thin film electrode layer formed by vapor deposition is also referred to as a vapor deposition electrode.
The thin film electrode layer may be a stack of a plurality of layers using at least one of the plating electrodes, sputtering electrodes, and vapor deposition electrodes.
The above thin film forming method is suitable when trying to achieve a preferable thickness (described later) of the thin film electrode layer. The electrode layer formed by a method other than the above thin film forming method, for example, a paste dip, has insufficient flatness in thickness, and it is difficult to achieve a preferable thickness (described later) in relation to the paste viscosity. ..

The metal constituting the thin film electrode layer preferably contains at least one metal selected from the group consisting of Cu, Ni, Ag, Pd, Ag—Pd alloy and Au, and more preferably contains Cu. The thin film electrode layer is preferably a layer that does not contain glass, and the metal content per unit volume is preferably 99% by volume or more.

The thickness of the thin film electrode layer is not particularly limited, but is preferably 0.5 μm or more and 9 μm or less, more preferably 1 μm or more and 5 μm or less, and further preferably 2 μm or more and 3 μm or less.
The thickness of the thin film electrode layer can be measured by cutting a monolithic ceramic capacitor to expose the LT cross section and observing it with a microscope. Five points (three points that are boundaries between the divided thin film electrode layers and both ends in the T direction) obtained by dividing one thin film electrode layer into four equal parts in the T direction on the exposed region where the internal electrode layer is exposed. The operation of calculating the thickness of the thin film electrode layer at the two points) is performed with 6 samples, and the average value of 30 points is taken as the thickness of the thin film electrode layer.

It is preferable that the thin film electrode layer is arranged in the plane where the exposed region of the laminated body is formed when the laminated body is viewed in a plan view from the L direction. The thickness of the resistance electrode layer tends to be thin in the vicinity of the ridgeline portion (also referred to as the edge portion) of the laminated body, and the thickness tends to vary. When the thin film electrode layer is extended to the outside of the plane where the exposed region is formed, the current flowing through the resistance electrode layer near the ridge line increases, so that the resistance value of the multilayer ceramic capacitor varies, or the multilayer ceramic capacitor as a whole It becomes difficult to design the resistance value.

In addition to the resistance component, glass, metal and metal oxide are added to the resistance electrode layer as needed.
The resistance component refers to a component having a relatively high electrical resistivity excluding metal and glass contained in a general external electrode, and specifically, a metal oxide and carbon excluding glass.
Examples of the metal oxide constituting the resistance component (hereinafter, also referred to as the first metal oxide) include In—Sn composite oxide (ITO), La—Cu composite oxide, Sr—Fe composite oxide, and Ca. A composite oxide such as a −Sr—Ru composite oxide can be used.
As the carbon, amorphous carbon such as carbon black, graphite, or the like can be used.

As the glass, B-Si-based glass, B-Si-Zn-based glass, B-Si-Zn-Ba-based glass, B-Si-Zn-Ba-Ca-Al-based glass and the like can be used.
The volume ratio of the first metal oxide to the glass in the resistance electrode layer is preferably 30:70 to 70:30.

The metal preferably comprises at least one metal selected from the group consisting of Ag, Ni, Cu, Au and Pd. Among these, it is more preferable to contain Ni. This is because Ni can have a fine particle size.

The first metal oxide other metal oxides as a (hereinafter, also referred to as the second metal oxide), for _{example, Al 2 O 3, ZrO 2} , TiO 2, ZnO and the like.

The electrical resistivity of the resistance electrode layer and the denseness of the resistance electrode layer can be adjusted by the resistance component, glass, metal and the second metal oxide.
For example, when a metal is added, the resistivity of the resistance electrode layer decreases, and when a second metal oxide is added, the resistivity of the resistance electrode layer increases.
Further, when a metal such as Ni or Cu or Al ₂ O ₃ or TiO ₂ is added, the densification of the resistance electrode layer can be promoted. On the other hand, when a metal such as Mo, Cr or Nb or a _{second metal oxide such as ZrO 2} or ZnO is added, the densification of the resistance electrode layer can be suppressed.
The suppression of densification has the meaning of preventing the generation of blister due to oversintering of the resistance electrode layer.

The thickness of the resistance electrode layer is not particularly limited, but is preferably 5 μm or more and 25 μm or less. The thickness of the resistance electrode layer is the same as the thickness of the thin film electrode layer, which is the thickness of the resistance electrode layer at five points obtained by dividing the exposed region where the internal electrode layer is exposed into four equal parts in the T direction. The average value of 30 points measured with one sample is used.
Further, it is preferable that the thickness of the resistance electrode layer formed directly above the thin film electrode layer does not vary. Further, the thickness of the resistive electrode layer formed directly on the thin film electrode layer, and the thickest portion of the thickness (portion indicated by the double-headed arrow Y ₁ in FIG. 4), the thinnest portion (4 thick The difference in thickness from the portion indicated by the double-headed arrow Y ₂ ) is more preferably 15 μm or less, and further preferably 5 μm or less.

The electrical resistivity of the resistance electrode layer is preferably 0.01 Ω · cm or more and 100 Ω · cm or less, more preferably 0.05 Ω · cm or more and 10 Ω · cm or less, and 0.05 Ω · cm or more and 1 Ω ·. It is more preferably cm or less.

The resistance electrode layer preferably covers the entire thin film electrode layer arranged immediately below the resistance electrode layer. When a part of the thin film electrode layer is not covered with the resistance electrode layer, the current preferentially flows to the uncovered region, and it becomes difficult to design the resistance value of the multilayer ceramic capacitor as a whole.

It is preferable that the resistance electrode layer is arranged in the plane where the exposed region of the laminated body is formed when the laminated body is viewed in a plan view from the L direction. When the resistance electrode layer is arranged in the plane on which the exposed region of the laminated body is formed, the resistance electrode layer is not arranged on another surface beyond the ridgeline portion of the laminated body. Therefore, it is possible to prevent the thickness of the resistance electrode layer from fluctuating in the vicinity of the ridgeline portion (also referred to as the edge portion) of the laminated body.

The upper electrode layer may have an electrical resistivity smaller than that of the resistance electrode layer, and preferably contains at least one metal selected from the group consisting of, for example, Cu, Ni, Ag, Pd, Ag—Pd alloy and Au. , Cu is more preferably contained. The thin film electrode layer is preferably a layer that does not contain glass, and the metal content per unit volume is preferably 99% by volume or more.

The thickness of the upper electrode layer is not particularly limited, but when an external electrode with resistance is formed on the end face of the laminated body, the thickness of the upper electrode layer constituting the external electrode is preferably 5 μm or more and 50 μm or less. .. When the external electrode with resistance is formed on the side surface of the laminated body, the thickness of the upper electrode layer constituting the external electrode is preferably 5 μm or more and 40 μm or less.
The thickness of the upper electrode layer is the same as the thickness of the thin film electrode layer, which is the thickness of the upper electrode layer at five points obtained by dividing the exposed region where the first internal electrode layer is exposed into four equal parts in the T direction. The average value of 30 points measured with 6 samples is used.

In the multilayer ceramic capacitor of the present invention, some of the external electrodes covering the exposed region formed on the laminate may be low resistance external electrodes.
The low resistance external electrode is an external electrode that does not have a resistance electrode layer, and is not particularly limited as long as it is made of a material having a low electrical resistivity. For example, a conductive paste is applied and baked. ..
The low resistivity external electrode preferably has a lower resistivity than the resistance electrode layer.

[Manufacturing method of multilayer ceramic capacitors]
The method for manufacturing the multilayer ceramic capacitor of the present invention will be described below.
The method for manufacturing a multilayer ceramic capacitor of the present invention comprises a substantially rectangular laminate having a plurality of laminated ceramic layers and a plurality of internal electrode layers, and having two or more exposed regions where the plurality of internal electrode layers are exposed. A laminate forming step to be formed and a coating step of covering the exposed region with an external electrode are provided, and the coating step includes a thin film electrode layer, a resistance electrode layer provided on the thin film electrode layer, and the resistance electrode. It has a first coating step of covering at least one of the exposed regions with a resistant external electrode having an upper electrode layer having an electric resistance smaller than that of the resistance electrode layer provided on the layer, and the first coating. The process is characterized in that a thin film electrode layer is formed directly on the exposed internal electrode layer.

First, the laminate forming step will be described.
In the laminate forming step, a substantially rectangular parallelepiped-shaped laminate is formed, which is composed of a plurality of laminated ceramic layers and a plurality of internal electrode layers, and has two or more exposed regions where the plurality of internal electrode layers are exposed.
As a method for forming such a laminate, for example, a predetermined number of ceramic green sheets having an internal electrode pattern as an internal electrode layer formed on the ceramic green sheet are laminated and compressed to obtain a green sheet laminate. After that, a method of firing and the like can be mentioned.

The ceramic green sheet is obtained by, for example, spray coating, die coating, screen printing or the like on a carrier film such as a PET film by spraying a ceramic slurry in which a metal oxide as a raw material of a ceramic layer, an organic substance, a solvent or the like is mixed. It can be obtained by applying in the form of a sheet.
The thickness of the ceramic green sheet is preferably 0.4 μm or more and 3.0 μm or less.
As the metal oxide used as a raw material for the ceramic layer, the same metal oxide as the raw material constituting the ceramic layer in the multilayer ceramic capacitor of the present invention can be preferably used.

The conductive paste that becomes the internal electrode layer is composed of a metal material such as Ni powder, a solvent, a dispersant, and a binder, and an internal electrode pattern is produced by printing on a ceramic green sheet by a method such as screen printing or gravure printing. can do.
The thickness of the printed internal electrode pattern is preferably 0.3 μm or more and 1.0 μm or less.
Examples of the compression method include a rigid body press and a hydrostatic pressure press.
By arranging a resin sheet having a constant thickness in the outermost layer during pressing, sufficient pressure is applied to a portion where the internal electrode pattern is not formed, and the adhesive force between the ceramic green sheets can be enhanced.

Then, the obtained green sheet laminate is cut out so that the internal electrode layers are exposed at two or more places, if necessary, and fired under predetermined conditions to obtain the laminate.
It is preferable to perform barrel polishing by accommodating the green sheet laminate cut into a predetermined shape and an abrasive in a barrel and giving a rotational motion to the barrel to round the corners and ridges of the laminate.

Subsequently, the coating process will be described.
The coating step is a step of covering the exposed region with an external electrode, and has a first coating step described later.

In the first coating step, at least one of the exposed regions is covered by a resistant external electrode composed of a thin film electrode layer, a resistance electrode layer provided on the thin film electrode layer, and an upper electrode layer provided on the resistance electrode layer. cover. At this time, the thin film electrode layer is formed directly on the internal electrode layer.

Examples of the method for forming the thin film electrode layer directly on the internal electrode layer include plating, vapor deposition, and sputtering, and it is preferable to form the thin film electrode layer by a plating method.
As the material of the thin film electrode layer, the material of the thin film electrode layer described in the multilayer ceramic capacitor of the present invention can be preferably used.
In forming the thin film electrode layer directly on the internal electrode layer, a catalyst or the like may be attached to the surface of the internal electrode layer.
By adhering a catalyst or the like to the surface of the internal electrode layer, it becomes easy to control the region where the thin film electrode layer is formed.

It is preferable that the thin film electrode layer is not formed on a surface other than the surface on which the internal electrode layer is exposed. Further, it is preferable to form the thin film electrode layer so that the distance from the ridgeline portion of the laminated body to the thin film electrode layer in the W direction of the laminated body is 1/3 or more of the W gap of the laminated body, and 1/2 or more. It is more preferable to form the thin film electrode layer so as to be 9/10 or more, and it is further preferable to form the thin film electrode layer so as to be 9/10 or more. Further, it is preferable to form the thin film electrode layer so that the distance from the ridge of the laminated body to the thin film electrode layer in the T direction of the laminated body is 1/3 or more of the T gap of the laminated body, and more than 1/2. It is more preferable to form the thin film electrode layer so as to be 9/10 or more, and it is further preferable to form the thin film electrode layer so as to be 9/10 or more.

The thickness of the thin film electrode layer is not particularly limited, but is preferably thinner than the resistance electrode layer formed in the subsequent steps, and more preferably 0.5 μm or more and 9 μm or less.

Subsequently, a resistance electrode layer is formed on the thin film electrode layer.
As a method of forming the resistance electrode layer on the thin film electrode layer, for example, a method of impregnating the end face (or side surface) of the laminate on which the thin film electrode layer is formed with the resistance electrode paste to be the resistance electrode layer and then firing. Alternatively, a method in which a resistance electrode paste to be a resistance electrode layer is processed into a sheet is applied to the surface of the thin film electrode layer and then fired.
The thickness of the resistance electrode paste formed on the thin film electrode layer is not particularly limited, but it is preferable that the thickness of the resistance electrode layer after firing is 5 μm or more and 25 μm or less.

The resistance electrode paste preferably contains, for example, metal oxide powder, glass, a dispersant, a solvent, and the like, and has a constant viscosity.
Examples of the method for processing the resistance electrode paste into a sheet include a method in which the resistance electrode paste is applied onto a carrier film, dried, and then the carrier film is peeled off.
As the metal oxide and glass constituting the resistance electrode paste, the same materials as those constituting the resistance electrode layer described in the multilayer ceramic capacitor of the present invention can be preferably used.

A resistance electrode layer is formed on the thin film electrode layer by firing the resistance electrode paste or a sheet of the resistance electrode paste processed by the first firing step.
The firing temperature in the first firing step is not particularly limited, but is preferably 700 ° C. or higher and 800 ° C. or lower, and the maximum temperature in the first firing step is higher than the maximum temperature in the second firing step described later. Is also preferable.

Subsequently, an upper electrode layer is formed on the resistance electrode layer.
Examples of the method of forming the upper electrode layer on the resistance electrode layer include a method of applying an upper layer electrode paste in which metal particles constituting the upper layer electrode layer are dispersed in a solvent and firing the upper layer electrode layer, and a method of firing the upper layer electrode. Examples thereof include a method in which an upper layer electrode paste sheet obtained by molding a paste into a sheet is applied onto a resistance electrode layer and fired.
Further, a conductive resin paste containing metal particles constituting the upper electrode layer and a thermosetting resin may be applied onto the resistance electrode layer and heat-treated to heat-cure the resin to form the upper electrode layer. ..
The thickness of the upper electrode paste applied or applied on the resistance electrode layer is not particularly limited, but the thickness of the upper electrode layer after firing is 5 μm or more and 50 μm or less in the case of the end face, and the thickness of the side surface. In some cases, the thickness is preferably 5 μm or more and 40 μm or less.

The upper electrode paste to be the upper electrode layer may have a composition such that the electrical resistivity of the upper electrode layer is smaller than that of the resistance electrode layer, and includes, for example, metal particles, glass, a dispersant, a solvent, and the like, and is constant. It is preferable to have the viscosity of.
The average particle size of the metal particles constituting the upper metal layer is preferably small, and more preferably the average particle size is 0.1 μm or more and 3 μm or less.
The smaller the average particle size of the metal particles, the larger the contact area with the resistance electrode layer, and the easier the sintering proceeds even at a low temperature.
As the metal particles and glass constituting the upper electrode layer, the same materials as those constituting the upper electrode layer described in the multilayer ceramic capacitor of the present invention can be preferably used.

The metal particles constituting the upper electrode paste preferably include flat metal particles. By including the flat metal particles, the thickness of the upper electrode layer covering the resistance electrode layer formed near the ridge of the laminate can be increased, so that the resistance value of the multilayer ceramic capacitor varies from the design value. Can be suppressed.

The method of applying the upper electrode paste on the resistance electrode layer is not particularly limited, but a method of impregnating the end face (or side surface) of the laminate on which the resistance electrode layer is formed into the upper electrode paste to be the upper electrode layer, printing, etc. Method can be mentioned.

The upper electrode layer is formed on the resistance electrode layer by firing the upper electrode paste or the upper electrode paste processed into a sheet by the second firing step.
The maximum temperature in the second firing step is not particularly limited, but is preferably 600 ° C. or higher and 700 ° C. or lower, and the maximum temperature in the second firing step is lower than the maximum temperature in the first firing step. preferable. If the maximum temperature in the second step is higher than the maximum temperature in the first firing step, the resistance electrode layer once formed may be deteriorated by the second firing step.

By the above steps, an external electrode with resistance that covers the exposed region is formed.
A plating layer may be further formed on the upper electrode layer, which is the outermost layer of the external electrode with resistance. By forming the plating layer, the solder wettability is improved and the multilayer ceramic capacitor can be easily mounted. The composition of the plating layer is not particularly limited, but Ni / Sn plating is preferable.
Further, when the plating layer is formed on the upper electrode layer, the surface of the upper electrode layer may be roughened by a blasting treatment or the like. By applying the roughening treatment, the plating property is improved.

In the method for manufacturing a multilayer ceramic capacitor of the present invention, the coating step may further include a second coating step.
The second coating step is a step of directly forming a low resistance external electrode on the internal electrode layer with respect to the exposed region where the internal electrode layer is exposed.
For example, in the laminate forming step, the first exposed region where the first internal electrode layer is exposed, the second exposed region facing the first exposed region, and the third exposed region where the second internal electrode layer is exposed. When a laminate having an exposed region of No. 1 and a fourth exposed region facing the third exposed region is formed, the coating step covers the first exposed region and the second exposed region of the laminate. In addition to the first coating step of forming the external electrode with resistance, the second coating for forming the low resistance external electrode directly on the second internal electrode layer exposed to the third exposed region and the fourth exposed region. It may be provided with a process.

As a second coating step, for example, a method of applying a conductive paste to an exposed region where the internal electrode layer is exposed and firing it can be mentioned.
As the conductive paste that can be used in the second coating step, the upper electrode paste used in the first coating step can be preferably used.
By applying the upper electrode paste to the surface of the exposed region where the internal electrode layer is exposed and then performing the third firing step, the low resistance external electrode can be directly formed on the surface of the exposed region where the internal electrode layer is exposed. can.
The maximum temperature of the third firing step is not particularly limited, but is preferably higher than the maximum temperature of the second firing step.
A plating layer may be formed on the surface of the low resistance external electrode, if necessary. By forming the plating layer, the solder wettability is improved and the multilayer ceramic capacitor can be easily mounted. The composition of the plating layer is not particularly limited, but Ni / Sn plating is preferable.

The order of the first coating step and the second coating step is not particularly limited, and the first coating step may be performed first, the second coating step may be performed first, and the first coating step may be performed first. A part of the second coating step may be performed during the second coating process, or a part of the first coating step may be performed during the second coating process.
However, considering the denseness of the electrode to be formed and the firing temperature, it is preferable to perform the second coating step first.

Hereinafter, examples in which the multilayer ceramic capacitor of the present invention is disclosed more specifically will be shown. The present invention is not limited to these examples.

(Example 1)
(Preparation of laminate)
A polyvinyl butyral-based binder, a plasticizer, and ethanol as an organic solvent were added to _{BaTIO 3} as a ceramic raw material, and these were wet-mixed with a ball mill to prepare a ceramic slurry. Next, this ceramic slurry was sheet-molded by the lip method to obtain a rectangular ceramic green sheet. Next, a conductive paste containing Ni was screen-printed on the ceramic green sheet to form an internal electrode pattern containing Ni as a main component. Next, a plurality of ceramic green sheets on which the internal electrode pattern was formed were laminated so that the drawn sides of the internal electrode layers were staggered to obtain a raw laminated sheet to be the capacitor body. Next, this raw laminated sheet was pressure-molded and divided by dicing to obtain chips. The obtained chips are _{heated at 1200 ° C. in an N 2} atmosphere to burn a binder, and then fired in _{a reducing atmosphere containing H 2} , N ₂ and H ₂ O gases, and the sintered laminate is sintered. Got The structure of the laminate is a structure having a plurality of ceramic layers and a plurality of internal electrode layers. The dimensions of the laminate were 0.92 mm in the L direction × 0.55 mm in the W direction × 0.39 mm in the T direction. An exposed region where the first internal electrode layer is exposed is formed on the first end face and the second end face which are the end faces in the L direction, and on the first side surface and the second side surface which are the end faces in the W direction. Was formed with an exposed region where the second internal electrode layer was exposed.
The average thickness of the internal electrode layer was 0.55 μm, the average thickness of the ceramic layer sandwiched between the internal electrode layers was 0.75 μm, and the number of internal electrodes was 266.

(Second coating step)
A conductive paste containing copper powder is applied to the surfaces of the first side surface and the second internal electrode layer exposed on the second side surface, and fired at 850 ° C. to obtain the first side surface and the first side surface. Low resistance external electrodes were formed on each of the side surfaces of 2.

(First coating step)
(1) Preparation of Thin Film Electrode Layer The first end face and the second end face are sandblasted to improve the degree of exposure of the internal electrode layer on the first end face and the second end face to improve the plating property. Improved.
After that, wet copper plating is performed on the entire laminate to form a thin film electrode layer having a thickness of 2 μm directly connected to the first internal electrode layer on the first end face and the second end face, and the first side surface. And a plating layer was formed on the low resistance external electrode on the second side surface. At this time, the distances from the ridges of the thin film electrode layers formed on the first end face and the second end face are 0.95 times the W gap in the W direction and 0.95 times the T gap in the T direction. rice field.
(2) Preparation of Resistance Electrode Layer A resistance electrode paste was prepared by dispersing a mixed powder in which In—Sn composite oxide, glass and Ni powder were mixed at a ratio of 40 wt%: 50 wt%: 10 wt% in a solvent. As the glass, B-Si-Zn-Ba-Ca-Al-based glass was used.
Dispenser so that the obtained resistance electrode paste completely covers the thin film electrode layers formed on the first end face and the second end face, and does not protrude from the first end face and the second end face, respectively. And fired at 770 ° C.
(3) Preparation of Upper Electrode Layer An upper electrode paste was prepared by dispersing a mixture of copper particles (mixture of spherical particles and flat particles) having an average particle diameter of 1 μm and glass in a solvent. At this time, the composition of the upper electrode paste is adjusted so that the electrical resistivity of the upper electrode layer obtained by firing the upper electrode paste is lower than the electrical resistivity of the resistance electrode layer obtained by firing the resistance electrode paste. bottom.
As the glass, B-Si-Zn-Ba-Ca-Al-based glass similar to the resistance electrode paste was used.
The first end face and the second end face were immersed in the obtained upper electrode paste to apply the upper electrode paste on the resistance electrode layer, and then fired at 650 ° C. The thickness of the formed upper electrode layer was 20 μm at the thickest portion.
By the above procedure, the first end face and the second end face were covered with an external electrode with resistance composed of a thin film electrode layer, a resistance electrode layer and an upper electrode layer.

(Polishing of laminate)
After the laminate is housed in a mesh cage having a finer mesh than the laminate, polishing is performed by hitting the laminate with zirconia powder at a pressure of 0.05 MPa for 20 minutes while rotating the mesh cage. The glass on the surface of the upper electrode layer formed on the end face and the second end face was removed to improve the plating property.

(Plating process)
The polished laminate is first subjected to Ni plating, then Sn plating, and then on the upper electrode layer formed on the first end face and the second end face, and on the first side surface and the second side surface. A Ni / Sn plating layer was formed on each of the low resistance external electrodes formed in.
Through the above procedure, a monolithic ceramic capacitor according to Example 1 was obtained.
The composition and thickness of the resistance electrode layer were adjusted to adjust the ESR of the multilayer ceramic capacitor according to Example 1 to about 50 mΩ.

(Example 2)
In the preparation of the resistance electrode layer (2) in the first coating step, by immersing the first end face and the second end face in the resistance conductive paste, the resistance so as to protrude from the first end face and the second end face. Electrode paste was applied. A multilayer ceramic capacitor according to Example 2 was manufactured in the same procedure as in Example 1 except for the above.

(Example 3)
Prior to the preparation of the thin film electrode layer (1) in the first coating step, palladium particles as a catalyst are applied to the entire surfaces of the first end face and the second end face, and then the thin film electrode layer is formed. A thin film electrode layer was formed on a part of the first side surface, the second side surface, the first main surface, and the second main surface so as to protrude from the first end face and the second end face. Except for this, the monolithic ceramic capacitor according to Example 3 was manufactured by the same procedure as in Example 2.

(Comparative Example 1)
The composition of the resistance electrode paste used in the preparation of (2) the resistance electrode layer was changed without producing (1) the thin film electrode layer in the first coating step. Other than that, the monolithic ceramic capacitor according to Comparative Example 1 was manufactured by the same procedure as in Example 1. Further, the ESR of the multilayer ceramic capacitor according to Comparative Example 1 was adjusted to about 50 mΩ by changing the composition of the resistance electrode paste in (2) preparation of the resistance electrode layer.

(Comparative Example 2)
The composition of the resistance electrode paste used in the preparation of (2) the resistance electrode layer was changed without producing (1) the thin film electrode layer in the first coating step. Other than that, the monolithic ceramic capacitor according to Comparative Example 2 was manufactured by the same procedure as in Example 2. Further, the ESR of the multilayer ceramic capacitor according to Comparative Example 2 was adjusted to about 50 mΩ by changing the composition of the resistance electrode paste in (2) preparation of the resistance electrode layer.

(Observation of external electrode with resistance on the end face)
The periphery of the multilayer ceramic capacitors according to Examples 1 to 3 and Comparative Examples 1 and 2 is hardened with resin, the side surface of the LT is polished, and the surface is polished to a depth of 1/2 in the W direction to expose the LT cross section. I let you. A cross section for observation was obtained by performing ion milling on the polished surface to remove sagging due to polishing. By observing the cross section for observation with a microscope, the region where each electrode layer (thin film electrode layer, resistance electrode layer and upper electrode layer) was formed was observed. The results are shown in Table 1.

(Measurement of ESL)
Twenty multilayer ceramic capacitors according to Examples 1 to 3 and Comparative Examples 1 and 2 were prepared, mounted on a mounting substrate, and ESL was measured using a network analyzer (E5071B manufactured by Agilent). The average value of the pieces was calculated. The measurement frequency band was 100 MHz. The results are shown in Table 1.

(Measurement of ESR)
Twenty multilayer ceramic capacitors according to Examples 1 to 3 and Comparative Examples 1 and 2 were prepared, and ESR was measured using an LCR meter (E4980A manufactured by Agilent). ESR_CV) was calculated. The measurement conditions were 1 MHz and 0.01 Vrms. The results are shown in Table 1.

From the results in Table 1, it was confirmed that the multilayer ceramic capacitor of the present invention has a low ESL and stable connectivity between the internal electrode layer and the external electrode. It was also confirmed that the variation in ESR (ESR_CV) can be suppressed by forming the thin film electrode layer and / or the resistance electrode layer in the plane of the laminate forming the external electrode with resistance (that is, only the end face). did it.
In Examples 1 to 3, the thin film electrode layer was formed by the plating method, but even if the thin film electrode layer is formed by sputtering and vapor deposition, the plating method has the effect of reducing ESL and suppressing variation in ESR. It was confirmed that it was the same as the case. Further, even when the thickness of the thin film electrode layer is changed from 2 μm to 0.5 μm and 9 μm, respectively, the effects of lowering the ESL and suppressing the variation in ESR are the cases of Examples 1 to 3 (thickness 2 μm). It was confirmed that it was the same as (in the case of).

1 Multilayer ceramic capacitor 10 Laminated body 11 First main surface 12 Second main surface 13 First side surface 14 Second side surface 15 First end surface 16 Second end surface 20 Ceramic layer 21 Outer layer (ceramic layer)
22 Inner layer (ceramic layer)
30 Internal electrode layer 35 First internal electrode layer 36 Second internal electrode layer 61 Thin film electrode layer 62 Resistance electrode layer 63 Upper electrode layer 100 External electrode (external electrode with resistance)
200 external electrodes (low resistance external electrodes (external electrodes without a resistance electrode layer))

Claims (5)

A substantially rectangular parallelepiped-shaped laminate having a plurality of laminated ceramic layers and a plurality of internal electrode layers and having two or more exposed regions where the plurality of internal electrode layers are exposed.
An external electrode covering the exposed area is provided.
At least one of the external electrodes is an external electrode with resistance.
The internal electrode layer has a first internal electrode layer and a second internal electrode layer that faces the first internal electrode layer in the stacking direction.
The external electrode with resistance includes a thin film electrode layer that directly contacts the internal electrode layer in the exposed region, a resistance electrode layer provided on the thin film electrode layer, and the resistance electrode provided on the resistance electrode layer. It has an upper electrode layer with a lower electrical resistivity than the layer,
The thin film electrode layer is arranged only in the plane where the exposed region is formed in the laminated body .
The upper electrode layer is a multilayer ceramic capacitor containing metal particles and glass. The multilayer ceramic capacitor according to claim 1, wherein the resistance electrode layer is arranged in a plane in which the exposed region is formed in the laminated body. The laminated body has a first end face and a second end face facing the first end face, and a first side surface and a second end face orthogonal to the first end face and the second end face and facing each other. With sides,
The first internal electrode layer is exposed on the first end face and the second end face.
The second internal electrode layer is exposed on the first side surface and the second side surface.
The multilayer ceramic capacitor according to claim 1 or 2, wherein the external electrode covering the exposed region where the first internal electrode layer is exposed on the first end face and the second end face is the external electrode with resistance. The multilayer ceramic capacitor according to claim 3, wherein the external electrode covering the exposed region where the second internal electrode layer is exposed on the first side surface and the second side surface is a low resistance external electrode. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the thin film electrode layer is a plated electrode.

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