JP7209072B2 - Multilayer ceramic capacitor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a multilayer ceramic capacitor capable of miniaturization and high performance, and a manufacturing method thereof.

In recent years, with the miniaturization of electronic devices such as smart phones and mobile phones, there is an increasing demand for miniaturization and large capacity for electronic components mounted in electronic devices, such as multilayer ceramic capacitors.

In such a laminated ceramic capacitor, the problem is how to ensure the moisture resistance of the ceramic layers. Conventionally, in order to ensure moisture resistance, the sinterability of the ceramic layer has been controlled by adding an auxiliary agent that enhances the sinterability to the ceramic material or reducing the diameter of the dielectric particles that make up the ceramic layer. , to achieve densification (see Patent Documents 1 to 4, for example).

Japanese Patent No. 4135443 JP 2012-227260 A JP 2003-017356 A JP 2010-103566 A

Addition of a sintering aid such as manganese or magnesium is effective in promoting the densification of the ceramic layer. However, the addition of a sintering aid lowers the dielectric constant of the dielectric, making it difficult to secure the desired capacitance. For this reason, it has been very difficult to ensure both moisture resistance and capacitance.

SUMMARY OF THE INVENTION In view of the circumstances as described above, an object of the present invention is to provide a multilayer ceramic capacitor capable of ensuring both moisture resistance and capacitance, and a method for manufacturing the same.

To achieve the above object, a multilayer ceramic capacitor according to one aspect of the present invention includes a laminate, an external dielectric, a first external electrode, and a second external electrode.
In the laminate, the first internal electrode layers and the second internal electrode layers are alternately laminated via an internal dielectric formed of a ceramic dielectric containing a sintering aid such as manganese or magnesium. , a first surface that is a surface in the stacking direction, a second surface that is a surface opposite to the first surface, and the first inner surface perpendicular to the first surface and the second surface. a third surface from which the electrode layers and the second internal electrode layers are drawn; and a surface opposite to the third surface from which the first internal electrode layers and the second internal electrode layers are drawn. and a fifth surface perpendicular to the first surface, the second surface, the third surface, and the fourth surface, from which the first internal electrodes are drawn. and a sixth surface opposite to the fifth surface from which the second internal electrodes are drawn.
The outer dielectric is formed of a ceramic dielectric containing a larger amount of sintering aid than the inner dielectric, and is arranged on the first surface, the second surface, the third surface, and the third surface of the laminate. 4 face.
The first external electrode covers the fifth surface and is electrically connected to the first internal electrode layer.
The second external electrode covers the sixth surface and is electrically connected to the second internal electrode layer.
A portion of the external dielectric covering at least the third surface and the fourth surface is composed of an outer layer portion and an intermediate portion provided between the outer layer portion and the laminate. The outer layer portion has a higher concentration of the sintering aid than the intermediate portion.

As the content of manganese or magnesium, which is a sintering aid, increases, the capacitance decreases. Therefore, reducing the content of the sintering aid in the internal dielectric facilitates securing the capacitance. On the other hand, a decrease in the amount of sintering aid results in a decrease in sinterability, but at this time, even if the amount of sintering aid in the inner dielectric is small, the outer dielectric contains more sintering aid than the inner dielectric. By containing it, the sinterability of the outer dielectric is improved more than the sinterability of the inner dielectric, and a multilayer ceramic capacitor having a dense surface can be realized. This densely sintered outer dielectric prevents the ingress of moisture from the outside atmosphere into the inner dielectric regions.

On the other hand, since there is a concentration difference in the sintering aid between the inner dielectric and the outer dielectric, the sintering aid derived from the outer dielectric may diffuse into the inner dielectric. In particular, the third surface and the fourth surface are in direct contact with the inner dielectric and the outer dielectric, so diffusion contamination is likely to occur. Therefore, as in the above configuration, by configuring the external dielectric with the outer layer portion and the intermediate portion provided between the laminated body and the outer layer portion, the outer layer portion and the laminated body having a high concentration of the sintering aid It is possible to keep a distance from the body. Therefore, the sintering aid originating from the outer layer portion diffuses into the intermediate portion without being directly diffused and mixed into the inner dielectric constituting the laminate. Therefore, not only the decrease in capacitance due to diffusion of the sintering aid into the internal dielectric is suppressed, but also the decrease in compactness is suppressed. Therefore, according to the laminated ceramic capacitor, it is possible to ensure moisture resistance and capacitance.

The concentration of the sintering aid contained in the intermediate portion increases with a first concentration gradient from the laminate side toward the outer layer portion side, and the sintering aid contained in the outer layer portion increases in concentration from the laminate side toward the outer layer portion side. The concentration may increase from the portion side toward the surface of the outer layer portion with a second concentration gradient that is smaller than the first concentration gradient.

The inner dielectric and the outer dielectric may contain at least one of silicon and vanadium.

The outer dielectric may be entirely composed of the outer layer portion and the intermediate portion.

The external dielectric includes a cover portion on the first surface and the second surface, and a side margin portion on the third surface and the fourth surface, wherein the cover portion and the side margin portion are provided. Vickers hardness of the cover portion may be 650 or more, and a ratio of the Vickers hardness of the cover portion to the Vickers hardness of the side margin portion may be 1.00 or more.

By designing the Vickers hardness of the cover portion and the side margin portions as described above, the density of the outer dielectric composed of the cover portion and the side margin portions is improved, thereby ensuring the moisture resistance of the multilayer ceramic capacitor. becomes possible.

The outer dielectric may contain more manganese or magnesium in the range of 0.3 mol or more and 4.5 mol or less per 100 mol of Ti (titanium) than the inner dielectric.

The outer dielectric contains more Mn (manganese) or Mg (magnesium) than the inner dielectric in the range of 0.3 mol or more and 4.5 mol or less per 100 mol of Ti. Not only is the difference in contraction behavior alleviated, but also the decrease in capacitance due to the diffusion of Mn (manganese) or Mg (magnesium) into the internal dielectric is suppressed.

The internal dielectric and the external dielectric contain silicon and boron, and the external dielectric contains more silicon than the internal dielectric in the range of 2.8 mol or less per 100 mol of Ti, and 0 per 100 mol of Ti. A large amount of boron may be contained in the range of 0.8 mol or less.

The outer dielectric contains more silicon than the inner dielectric in the range of 2.8 mol or less per 100 mol of Ti, and more boron in the range of 0.8 mol or less per 100 mol of Ti, thereby constituting the outer dielectric. Since the grain growth of the dielectric particles is suppressed, the decrease in strength due to the incomplete densification of the surface of the product is suppressed.

In order to achieve the above object, a method for manufacturing a multilayer ceramic capacitor according to one aspect of the present invention comprises:
forming a first laminate by alternately laminating internal dielectrics containing a sintering aid and internal electrode layers;
A first internal layer having a sintering aid concentration equal to or lower than the internal dielectric is laminated on the first surface of the first laminate and the second surface opposite to the first surface, and laminating a first outer layer having a higher concentration of sintering aid than the inner dielectric on the first inner layer to form a second laminate;
The second laminate is cut into a chip size, a second internal layer made of the same material as the first internal layer is laminated on both side surfaces of the second laminate having a chip size, and the second internal layer laminating a second outer layer made of the same material as the first outer layer on the inner layer to form a third laminate;
An outer dielectric comprising an intermediate portion having a sintering aid concentration higher than that of the inner dielectric and an outer layer portion having a sintering aid concentration higher than that of the intermediate portion by firing the third laminate. to form

Since the concentration of the sintering aid in the first inner layer and the second inner layer is less than the inner dielectric and lower than that in the first outer layer and the second outer layer, when firing the third laminate, , the inner dielectric, the first outer layer and the sintering aid from the second outer layer diffuse into the first inner layer and the second inner layer. As a result, it is possible not only to suppress the decrease in capacitance due to diffusion of the sintering aid into the internal dielectric, but also to suppress the decrease in compactness.

In order to achieve the above object, another manufacturing method of a multilayer ceramic capacitor according to one aspect of the present invention comprises:
An internal dielectric containing a sintering aid, an internal electrode layer, a first relaxation layer having a sintering aid concentration lower than that of the internal dielectric, and a second relaxation layer having a sintering aid concentration higher than that of the internal dielectric. forming a first laminate by laminating a plurality of first internal layers made of relaxing layers;
A second inner layer made of the same material as the first relaxation layer is laminated on the first surface of the first laminate and the second surface opposite to the first surface, forming a second laminate by laminating an outer layer made of the same material as the second relaxation layer on the inner layer of 2;
The second laminate is cut into a chip size, and the chip-sized second laminate is fired to obtain an intermediate portion having a higher concentration of the sintering aid than the internal dielectric, and an intermediate portion having a higher concentration of the sintering aid than the intermediate portion. forming an outer dielectric including an outer layer portion having a high concentration of a sintering aid;

As described above, according to the present invention, it is possible to provide a multilayer ceramic capacitor capable of ensuring moisture resistance and capacitance, and a method for manufacturing the same.

1 is a perspective view of a laminated ceramic capacitor according to a first embodiment of the invention; FIG. FIG. 2 is a cross-sectional view taken along line AA of FIG. 1; FIG. 2 is a cross-sectional view along BB in FIG. 1; FIG. 3 is a schematic diagram showing each element of the external dielectric shown in FIG. 2 ; FIG. 4 is a diagram showing concentration curves (concentration gradients) of Mn (manganese) contained in an internal dielectric and an external dielectric according to the embodiment; It is a schematic diagram which shows the manufacturing process of the same laminated ceramic capacitor. It is a schematic diagram which shows the manufacturing process of the same laminated ceramic capacitor. It is a schematic diagram which shows the manufacturing process of the same laminated ceramic capacitor. It is a figure which shows the density|concentration change of the sintering aid which concerns on the 3rd laminated body of the same embodiment. It is a concentration curve of a sintering aid related to the fourth laminate of the same embodiment. FIG. 4 is a schematic diagram showing another manufacturing process of the same multilayer ceramic capacitor; FIG. 4 is a schematic diagram showing another manufacturing process of the same multilayer ceramic capacitor; FIG. 4 is a schematic diagram showing another manufacturing process of the same multilayer ceramic capacitor; FIG. 4 is a perspective view of a laminated ceramic capacitor according to a second embodiment of the invention; FIG. 15 is a cross-sectional view taken along line AA of FIG. 14; 4 is a table showing the results of characteristic tests according to Example 1 of the present invention; 4 is a table showing the results of characteristic tests according to Example 2 of the present invention; 4 is a table showing the results of characteristic tests according to Example 2 of the present invention; 4 is a table showing the results of characteristic tests according to Example 2 of the present invention; 3 shows the ratio of the sintering aid contained in the internal dielectric and the external dielectric of laminated ceramic capacitors according to Examples 3 and 4 of the present invention and Comparative Examples 1 to 3, and the results of characteristic tests of each laminated ceramic capacitor. It is a table.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the embodiment described below is an example, and is not limited to this.

<First embodiment>
[Overall Configuration of Multilayer Ceramic Capacitor]
FIG. 1 is a perspective view of a laminated ceramic capacitor according to one embodiment of the present invention. 2 is a cross-sectional view along AA in FIG. 1, and FIG. 3 is a cross-sectional view along BB in FIG. In the following figures, the X, Y, and Z axis directions indicate three mutually orthogonal axial directions, respectively. In this embodiment, the X axis direction is the length direction of the multilayer ceramic capacitor, and the Y axis direction is the width direction. , the Z-axis direction corresponds to its height direction.

The multilayer ceramic capacitor 10 of this embodiment has an external dielectric 11, a first external electrode 12, a second external electrode 13, and a laminate 14, as shown in FIGS.

As will be described later, the laminated body 14 is formed by alternately laminating internal electrode layers and internal dielectrics in the Z-axis direction. The first external electrode 12 and the second external electrode 13 are formed on the terminal surfaces of the laminate 14 facing each other in the X-axis direction, and are electrically connected to the internal electrode layers of the laminate 14 . The external dielectric 11 is formed around the outer periphery of the laminate 14, as shown in FIG. Specifically, as shown in FIG. 2, the surfaces of the laminate 14 that face each other in the Y-axis direction and the faces that face each other in the Z-axis direction are covered. Details of each part of the multilayer ceramic capacitor 10 will be described below.

(Laminate)
As shown in FIG. 2, the laminate 14 includes a first surface 14a, a second surface 14b opposite to the first surface 14a, and a second surface perpendicular to the first surface 14a and the second surface 14b. and a fourth surface 14d opposite the third surface 14c, the first surface 14a, the second surface 14b, the third surface 14c and the fourth surface 14d being external. It is coated with dielectric 11 .

The laminate 14 has a first internal electrode layer 15, a second internal electrode layer 17 and an internal dielectric 16, as shown in FIG. A first internal electrode layer 15 and a second internal electrode layer 17 are drawn out from the third surface 14 c and the fourth surface 14 d of the laminate 14 .

As shown in FIG. 3, the laminate 14 is configured by sequentially laminating a first internal electrode layer 15, an internal dielectric 16, and a second internal electrode layer 17 in the Z-axis direction. and the second internal electrode layer 17 are arranged to face each other with the internal dielectric 16 interposed therebetween. The number of layers of the first internal electrode layers 15 and the second internal electrode layers 17 is not limited to the illustrated example, and each may be composed of several tens of layers or more.

Further, as shown in FIG. 3, the laminate 14 has a fifth surface 14e orthogonal to the first surface 14a, the second surface 14b, the third surface 14c, and the fourth surface 14d, and the fifth surface 14d. It has a sixth surface 14f opposite the surface 14e. The first internal electrode layer 15 is drawn out on the fifth surface 14e, the first external electrode 12 is provided so as to be electrically connected to the first internal electrode layer 15, and the sixth surface 14f , the second internal electrode layer 17 is drawn out, and the second external electrode 13 is provided so as to be electrically connected to the second internal electrode layer 17 .

The first internal electrode layers 15 and the second internal electrode layers 17 are composed of rectangular metal thin films obtained by sintering a conductive paste containing base metal powder such as Ni or Cu.

The internal dielectric 16 is formed mainly of dielectric powder such as barium titanate (BaTiO ₃ ), calcium titanate (CaTiO ₃ ), strontium titanate (SrTiO ₃ ), calcium zirconate (CaZrO ₃ ). It is composed of a sintered rectangular green sheet and has insulating properties. In this embodiment, the internal dielectric 16 is made of a slurry containing a barium titanate (BaTiO ₃ )-based ceramic material as a main component.

(external dielectric)
As shown in FIG. 2, the outer dielectric 11 of this embodiment has a structure including an intermediate portion 18 and an outer layer portion 19 .

As shown in FIG. 2, the intermediate portion 18 covers the first surface 14a, the second surface 14b, the third surface 14c, and the fourth surface 14d of the laminate 14, and separates the laminate 14 and the outer layer portion 19. intervene between The thickness of the intermediate portion 18 is appropriately changed according to the chip size, and is preferably 2 μm or more, for example.

The intermediate portion 18 is formed mainly of dielectric powder such as barium titanate (BaTiO ₃ ), calcium titanate (CaTiO ₃ ), strontium titanate (SrTiO ₃ ), calcium zirconate (CaZrO ₃ ), or the like. It is a sintered body and has insulating properties. In this embodiment, the intermediate portion 18 is made of a slurry containing a barium titanate (BaTiO ₃ ) ceramic material as a main component, like the internal dielectric 16 .

The outer layer portion 19 covers the outside of the intermediate portion 18 and constitutes the outer wall of the multilayer ceramic capacitor 10, as shown in FIG. The thickness of the outer layer portion 19 is appropriately set according to the chip size. For example, the thickness is preferably 10 μm or more, more preferably 20 μm or more.

The outer layer portion 19 is formed mainly of dielectric powder such as barium titanate (BaTiO ₃ ), calcium titanate (CaTiO ₃ ), strontium titanate (SrTiO ₃ ), calcium zirconate (CaZrO ₃ ), or the like. It is composed of a sintered body and has insulating properties. In this embodiment, the outer layer portion 19 is made of a slurry containing barium titanate (BaTiO ₃ )-based ceramic material as the main component, like the inner dielectric 16 and the intermediate portion 18 .

FIG. 4 is a schematic diagram showing each element of the external dielectric 11 shown in FIG. The external dielectric 11 according to this embodiment is composed of a side margin portion 20 and a cover portion 21, as shown in FIG.

As shown in FIG. 4, the side margin portion 20 includes a first coating layer 11c that covers the third surface 14c and the fourth surface 14d of the laminate 14, and a second coating layer that is laminated on the first coating layer 11c. layer 11d.

As shown in FIG. 4, the cover part 21 includes a third coating layer 11e that covers a plane parallel to the Y-axis direction of the first surface 14a, the second surface 14b, and the first coating layer 11c of the laminate 14. , and a fourth coating layer 11f covering the plane parallel to the Y-axis direction of the third coating layer 11e and the second coating layer 11d. Here, the intermediate portion 18 is composed of the first coating layer 11c and the third coating layer 11e, and the outer layer portion 19 is composed of the second coating layer 11d and the fourth coating layer 11f.

(external electrode)
The first external electrode 12 is an external terminal of the multilayer ceramic capacitor 10 . The first external electrode 12 is provided on the fifth surface 14e and partially covers the external dielectric 11, as shown in FIG. The first external electrode 12 is electrically connected to the first internal electrode layer 15 via the first lead end 15a, as shown in FIG.

The second external electrode 13 is an external terminal of the multilayer ceramic capacitor 10 . The second external electrode 13 is provided on the sixth surface 14f and partially covers the external dielectric 11, as shown in FIG. The second external electrode 13, as shown in FIG. 3, is electrically connected to the second internal electrode layer 17 via the second lead end 17a.

The first external electrode 12 and the second external electrode 13 are conductive electrodes containing base metal powder such as Ni, Cu, Cr, Ag, Pd, Fe, Sn, Pb, Pt, Ir, Rh, Ru, Al, and Ti. It consists of a thin metal film made by sintering paste. The surfaces of the first external electrodes 12 and the second external electrodes 13 may be plated with solder in order to improve wettability with solder when mounted on a circuit board.

[About sintering aid]
The inner dielectric 16, the intermediate portion 18 and the outer layer portion 19 of the present embodiment contain a sintering aid used for promoting and stabilizing sintering in manufacturing the multilayer ceramic capacitor 10. be. Here, the sintering aid contains at least Mn (manganese) or Mg (magnesium). The intermediate portion 18 according to this embodiment contains more sintering aid than the inner dielectric 16 , and the outer layer portion 19 contains more sintering aid than the intermediate portion 18 .

In addition to Mn (manganese) and Mg (magnesium), sintering aids include Si (silicon), B (boron), Ho (holmium), Ca (calcium), V (vanadium) and their oxides, Li (lithium), K (potassium), Na (sodium), and B (boron), such as glass containing Si (silicon) as a main component. In addition, these may be used alone, or a plurality of types may be mixed.

FIG. 5 is a schematic diagram of a main part of an EPMA (Electron Probe Micro Analyzer) spectrum of Mn (manganese) contained in the internal dielectric 16 and the external dielectric 11 of this embodiment. 3 shows a concentration curve (concentration gradient) of Mn (manganese) contained in the body 11. FIG.

Here, in FIG. 5, the curve in region La is the concentration curve of Mn (manganese) in region L1 related to the edge of laminate 14 (internal dielectric 16) shown in FIG. Further, the curve in the region Lb is the concentration curve of Mn (manganese) in the region L2 of the intermediate portion 18 shown in FIG. 2, and the curve in the region Lc is the region L3 It is a concentration curve of Mn (manganese) in.

As shown in FIG. 5, the laminated ceramic capacitor 10 of this embodiment has a structure in which the concentration of Mn increases from the laminate 14 toward the outer layer portion 19 . Specifically, as shown in FIG. 5, the concentration of manganese contained in the region L2 of the intermediate portion 18 increases with a first concentration gradient from the laminate 14 side toward the outer layer portion 19 side, The concentration of manganese contained in region L3 of portion 19 increases from the intermediate portion 18 side toward the surface of outer layer portion 19 with a second concentration gradient that is smaller than the first concentration gradient.

Here, the external dielectric 11 preferably contains more Mn (manganese) or Mg (magnesium) than the internal dielectric 16 in the range of 0.30 mol or more and 4.5 mol or less per 100 mol of Ti. If it is less than 0.30 mol, the surface of the outer layer portion 19 cannot be sufficiently densified, and if it exceeds 4.5 mol, Mn (manganese) or Mg (magnesium) diffuses into the internal dielectric 16, and the capacitance This is because the decrease in

Also, the outer dielectric 11 preferably contains more Si (silicon) than the inner dielectric 16 in the range of 0.00 mol or more and 2.8 mol or less per 100 mol of Ti. If it exceeds 2.8 mol, the dielectric particles forming the external dielectric 11 tend to grow, and the surface of the product may not be sufficiently densified, failing to secure the strength.

Further, the outer dielectric 11 preferably contains more B (boron) than the inner dielectric 16, within a range of 0.00 mol or more and 0.8 mol or less per 100 mol of Ti. If it exceeds 0.8 mol, the dielectric particles forming the outer dielectric 11 tend to grow, and the surface of the product may not be sufficiently densified, failing to secure the strength.

As sintering aids, Mn (manganese), Mg (magnesium), Si (silicon), and B (boron) are set within the above ranges, respectively, so that the internal electrode layers and the internal dielectric 16 shrink uniformly during firing. (simultaneously sintered). As a result, poor moisture resistance caused by the difference in sintering shrinkage behavior between the internal electrode layers and the internal dielectric 16 can be suppressed.

In addition, in thin-layer products in which the thickness of the internal dielectric 16 is less than 1 μm, such as a multilayer ceramic capacitor of 0603 shape (length 0.6 mm, width 0.3 mm, height 0.3 mm), the internal dielectric 16 is suppressed from being oversintered, thereby suppressing a decrease in the dielectric constant and making it possible to secure a desired capacitance.

Furthermore, since the outer dielectric 11 contains more sintering aid than the inner dielectric 16, the sinterability of the outer dielectric 11 can be improved more than the sinterability of the inner dielectric 16. can. As a result, oversintering of the internal dielectric 16 is suppressed, so that a decrease in dielectric constant is suppressed and the capacitance can be secured.

In addition, since the multilayer ceramic capacitor 10 of the present embodiment is configured such that the outer dielectric 11 contains more sintering aid than the inner dielectric 16, the outer dielectric 11 contains more sintering aid than the inner dielectric 16. , the hardness increases. As a result, the surface of the external dielectric 11 can be sufficiently densified, and the moisture resistance of the multilayer ceramic capacitor 10 can be ensured.

Specifically, when Vickers hardness is used as an index of hardness of the surface of the external dielectric 11, the Vickers hardness of the surface 20a of the side margin portion 20 and the surface 21a of the cover portion 21 shown in FIG. The ratio of the Vickers hardness of the surface 21a to the Vickers hardness of the surface 20a is set to 1.00 or more. With such a configuration, even if the laminated ceramic capacitor is subjected to stress due to bending of the substrate when mounted on the circuit board, cracks are less likely to occur.

A method for adjusting the Vickers hardness of the surfaces 20a and 21a is not particularly limited. For example, the hardness can be adjusted by adjusting the concentration of the sintering aid contained in the cover portion 21 and the side margin portion 20, the firing conditions, and the like.

For these reasons, according to the present embodiment, the outer dielectric 11 contains more sintering aid than the inner dielectric 16, so that the sinterability of the outer dielectric 11 is higher than that of the inner dielectric 16. improves. Therefore, according to the multilayer ceramic capacitor 10 of the present embodiment, it is possible to achieve both moisture resistance and capacitance.

[Action of Multilayer Ceramic Capacitor]
The multilayer ceramic capacitor 10 of the present embodiment configured as described above has the first external electrode 12 and the second external electrode 13 soldered to connection lands on the circuit board, respectively, so that the capacitive element has a predetermined capacitance. configure.

Furthermore, according to the present embodiment, the outer dielectric 11 contains more sintering aid than the inner dielectric 16 , so that the sinterability of the outer dielectric 11 is improved more than the sinterability of the inner dielectric 16 . Therefore, according to the multilayer ceramic capacitor 10 of the present embodiment, it is possible to achieve both moisture resistance and capacitance.

[Manufacturing method of multilayer ceramic capacitor]
(First manufacturing method)
A first method for manufacturing the multilayer ceramic capacitor 10 according to this embodiment will be described. The manufacturing method described below is an example, and the manufacturing method of the multilayer ceramic capacitor 10 is not limited to the method described below. 6 to 8 are schematic diagrams showing the manufacturing process of the multilayer ceramic capacitor 10. FIG.

FIG. 6(a) shows an internal dielectric 16 which is a ceramic green sheet formed from a slurry containing a ceramic material as its main component. The thickness of the internal dielectric 16 is not particularly limited, and can be, for example, about several μm.

As shown in FIG. 6B, strip-shaped first internal electrode layers 15 extending in the width direction are printed (laminated) on the internal dielectric 16 by a method such as screen printing. Thereby, a pattern of the first internal electrode layer 15 is formed on the internal dielectric 16 .

Subsequently, as shown in FIG. 6C, an internal dielectric 16 is laminated on the first internal electrode layer 15, and a second internal electrode layer 17 is laminated on the internal dielectric 16. Next, as shown in FIG. Then, the first internal electrode layers 15, the internal dielectrics 16, and the second internal electrode layers 17 are alternately laminated to form a laminate. Hereinafter, as shown in FIG. 6C, a laminate in which the first internal electrode layers 15, the internal dielectrics 16, and the second internal electrode layers 17 are alternately laminated is referred to as a first laminate 30. As shown in FIG.

Subsequently, as shown in FIG. 7A, a ceramic slurry having a sintering aid concentration lower than or equivalent to the ceramic slurry forming the internal dielectric 16 is applied to the front surface 30a and the rear surface 30b of the first laminate 30. The formed first inner layer 18a is laminated. Next, as shown in the figure, a first outer layer 19a is laminated on the first inner layer 18a. Hereinafter, a laminate obtained by laminating the first inner layer 18 a and the first outer layer 19 a on the first laminate 30 will be referred to as a second laminate 40 .

Subsequently, as shown in FIG. 7(b), the second laminate 40 is cut to obtain a chip 50. Next, as shown in FIG. Next, as shown in FIG. 7C, the second inner layer 18b is laminated on the first side cut surface 50a and the second side cut surface 50b of the chip 50. Next, as shown in FIG. The second inner layer 18b is formed from a ceramic slurry of the same material as the first inner layer 18a.

Next, as shown in FIG. 7(c), the second outer layer 19b is laminated on the second inner layer 18b. The second outer layer 19b is formed from a ceramic slurry of the same material as the first outer layer 19a.

The second inner layer 18b and the second outer layer 19b can be formed by coating or spraying ceramic slurry on the first side cut surface 50a and the second side cut surface 50b. from. A laminate in which the second internal layer 18 b and the second external layer 19 b are laminated on the chip 50 is referred to as a third laminate 60 .

Subsequently, the third laminate 60 is fired at a temperature of over 1,000° C. in a reducing atmosphere. The sintering aid diffuses into the third laminated body 60 after firing, and the laminated body 14, the intermediate portion 18 and the outer layer portion 19 are formed as shown in FIG. 8(a). Hereinafter, as shown in FIG. 8A, the chip in which the laminate 14, the intermediate portion 18 and the outer layer portion 19 are formed will be referred to as a fourth laminate 70. As shown in FIG.

Finally, as shown in FIG. 8B, the first external electrode 12 and the second external electrode 13 are formed on the fourth laminate 70, respectively. The first external electrode 12 and the second external electrode 13 are typically made of the same material as the first internal electrode layer 15 and the second internal electrode layer 17, for example, a paste of a base metal material such as Ni. It is formed by applying it to each end including the surface facing the X-axis direction of the laminate 70 and then baking it. After that, solder plating is applied to the surfaces of the first external electrode 12 and the second external electrode 13 as necessary. The first external electrode 12 and the second external electrode 13 can also be formed by firing at the same time as the fourth laminate 70 . A laminate in which the first external electrode 12 and the second external electrode 13 are formed on the fourth laminate 70 corresponds to the laminated ceramic capacitor 10, as shown in FIG. 8(b).

[Action of inner layer]
Addition of a sintering aid is effective in promoting the densification of the ceramic layer. However, the addition of a sintering aid lowers the dielectric constant of the dielectric, making it difficult to secure the desired capacitance. In addition, if the margin portion (cover layer, side margin layer) that protects the electrode intersection portion is sintered with a greater amount of the auxiliary agent component of the dielectric of the electrode intersection portion than the auxiliary agent component of the dielectric of the electrode intersection portion that is effective as a capacitor, the margin portion In some cases, the auxiliary agent component diffuses from the electrode intersections to the electrode intersections, lowering the dielectric constant of the dielectric at the electrode intersections. Therefore, it is very difficult to achieve both moisture resistance and capacitance.

On the other hand, the intermediate portion 18 of this embodiment is mainly composed of the first inner layer 18a and the second inner layer 18b, and the outer layer portion 19 is mainly composed of the first outer layer 19a and the second outer layer 19b. be done. Here, in the third laminate 60 immediately before the intermediate portion 18 and the outer layer portion 19 are formed, the first outer layer 19a and the second outer layer 19b are configured to be spaced from the inner dielectric 16 .

Specifically, as shown in FIG. 7C, the first internal layer 18a is interposed between the first external layer 19a and the internal dielectric 16, and the second external layer 19b and the internal dielectric 16 are interposed. The second inner layer 18b is interposed therebetween.

Here, since the concentration of the sintering aid in the first inner layer 18a and the second inner layer 18b is lower than that of the inner dielectric 16 and lower than that of the first outer layer 19a and the second outer layer 19b, the third laminate During firing of 60, sintering aids from inner dielectric 16, first outer layer 19a and second outer layer 19b will diffuse into first inner layer 18a and second inner layer 18b. On the other hand, the first inner layer 18a and the second inner layer 18b are interposed between the first outer layer 19a and the inner dielectric 16 and between the second outer layer 19b and the inner dielectric 16, respectively. Therefore, the first inner layer 18 a and the second inner layer 18 b function as buffer layers that suppress the penetration of the sintering aid derived from the first outer layer 19 a and the second outer layer 19 b into the inner dielectric 16 .

As a result, not only is the decrease in capacitance due to diffusion of the sintering aid into the internal dielectric 16 suppressed, but also the decrease in the denseness of the intermediate portion 18 and the outer layer portion 19 is suppressed. . Therefore, the monolithic ceramic capacitor 10 manufactured by the above-described method simultaneously secures desired capacitance and moisture resistance.

[Concentration change of sintering aid]
FIG. 9 is a diagram showing changes in concentration of the sintering aid for the third laminate 60, and FIG. 10 is a concentration curve for the sintering aid for the fourth laminate 70. As shown in FIG. In these figures, the curves in the regions Ld and Lg correspond to regions L4 (see FIGS. 7C and 8A) of the third laminate 60 and the fourth laminate 70, respectively. The same applies to L6.), and the curves in the regions Le and Lh are the concentration curves in the region L5 of the third laminated body 60 and the fourth laminated body 70, respectively. Curves in the regions Lf and Li are curves in the region L6 of the third laminated body 60 and the fourth laminated body 70, respectively.

As described above, the sintering aid diffuses into the third laminate 60 after firing. At this time, the sintering aid in the regions L4 and L6 of the third laminate 60 diffuses into the region L5. This reduces the concentration of the sintering aid in the regions L4 and L6, and increases the concentration of the sintering aid in the region L5. As a result, the sintering aid in the regions L4 to L6 of the third laminate 60 temporarily forms a concentration curve as shown in FIG. Dotted lines in regions Ld to Lf shown in FIG. 9 indicate concentrations of sintering aids in regions L4 to L6 of the third laminate 60 before firing.

The third laminate 60 in which the sintering aid has finished diffusing becomes the fourth laminate 70 in which the intermediate portion 18 and the outer layer portion 19 are formed as described above. Here, the sintering aid in the regions L4 to L6 of the fourth laminate 70 forms a concentration curve as shown in FIG. A region L4 of the fourth laminate 70 is a region related to the end portion of the laminate 14, and a region L5 is a region related to the intermediate portion 18. As shown in FIG. A region L6 is a region related to the outer layer portion 19. As shown in FIG.

That is, when the third laminate 60 is fired to form the fourth laminate 70 having the intermediate portion 18 and the outer layer portion 19, the sintering aid contained in the regions L4 to L6 of each laminate is , the density curve shown in FIG. 9 is formed on the way from the straight line shown in FIG. Finally, as shown in FIG. 10, a concentration curve is formed in which the concentration of the sintering aid increases at a predetermined gradient from the end portion of the laminate 14 toward the outer layer portion 19 . In this way, the first inner layer 18a and the second inner layer 18b function as buffer layers that suppress the penetration of the sintering aids derived from the first outer layer 19a and the second outer layer 19b into the inner dielectric 16. do.

(Second manufacturing method)
The multilayer ceramic capacitor 10 according to this embodiment can also be manufactured by a method different from the first manufacturing method described above. 11 to 13 are schematic diagrams showing another manufacturing process of the laminated ceramic capacitor 10. FIG.

FIG. 11(a) shows an internal dielectric 16 which is a ceramic green sheet formed from a slurry containing a ceramic material as its main component. The thickness of the internal dielectric 16 is not particularly limited, and can be, for example, about several μm.

As shown in FIG. 11B, a plurality of strip-shaped first internal electrode layers 15 are printed on the internal dielectric 16 by a method such as screen printing while being spaced apart from each other in the Y-axis direction. Thereby, a pattern of the first internal electrode layer 15 is formed on the internal dielectric 16 . The width direction of each first internal electrode layer 15 is parallel to the Y-axis direction, and the length direction thereof is parallel to the X-axis direction.

Next, as shown in FIG. 11(c), a plurality of first relaxation layers 18c, which are ceramic green sheets, having a predetermined width are formed on the internal dielectric 16 in the width direction (Y-axis direction) of each first internal electrode layer 15. Next, as shown in FIG. are laminated so as to be adjacent to both sides of the . The first relaxation layer 18c is formed from a ceramic slurry that has a lower concentration of sintering aid than or equal to the ceramic slurry that forms the inner dielectric 16 .

Subsequently, as shown in FIG. 12A, a plurality of second relieving layers 19c, which are ceramic green sheets, are laminated on the inner dielectric 16 next to each first relieving layer 18c. The second relaxation layer 19c is formed from a ceramic slurry having a higher concentration of sintering aid than the ceramic slurry forming the inner dielectric 16 . The surface of the internal dielectric 16 is covered with the first internal electrode layer 15, the first relaxing layer 18c and the second relaxing layer 19c. Hereinafter, as shown in FIG. 12A, the internal dielectric 16, the first internal electrode layer 15, the first relaxation layer 18c and the second relaxation layer 19c are referred to as a third internal layer 22. As shown in FIG. Similarly, the internal dielectric 16, the second internal electrode layer 17, the first relaxation layer 18c and the second relaxation layer 19c are used as a fourth internal layer 23. FIG.

Subsequently, as shown in FIG. 12(b), the fourth internal layer 23 is laminated on the third internal layer 22. Next, as shown in FIG. Next, as shown in FIG. 12(c), the third internal layers 22 and the fourth internal layers 23 are alternately laminated to form a laminate. Hereinafter, as shown in FIG. 12(c), a laminate in which the third internal layers 22 and the fourth internal layers 23 are alternately laminated is referred to as a fifth laminate 80. As shown in FIG.

Subsequently, as shown in FIG. 13A, the fifth internal layer 18d made of the same material as the first relaxation layer 18c is laminated on the entire front surface 80a and rear surface 80b of the fifth laminate 80. Then, as shown in FIG. Next, as shown in the figure, a third outer layer 19d made of the same material as the second relaxation layer 19c is laminated on the fifth inner layer 18d. Hereinafter, as shown in FIG. 13A, a laminate obtained by laminating a fifth inner layer 18d and a third outer layer 19d on a fifth laminate 80 is referred to as a sixth laminate 90. As shown in FIG.

Subsequently, as shown in FIG. 13B, the chip 100 is obtained by cutting the sixth laminate 90 . At this time, the sixth stacked body 90 is cut along the dotted line P passing through the center of the second relaxation layer 19c in the Y-axis direction (width direction) shown in FIG. 13(a).

Next, the chip 100 is fired at a temperature of several hundred degrees Celsius in a reducing atmosphere. After firing, the sintering aid diffuses to form the intermediate portion 18 and the outer layer portion 19, thereby obtaining the fourth laminate 70 shown in FIG. 8(a). Finally, the first external electrodes 12 and the second external electrodes 13 are formed by the same method as described above to obtain the multilayer ceramic capacitor 10 . That is, by using this method, it is possible to obtain the laminated ceramic capacitor 10 (having a buffer function) having the intermediate portion 18 shown in FIG. 2, as in the first manufacturing method. That is, the above-described method (second manufacturing method) can also provide the same effects as those of the first manufacturing method.

<Second embodiment>
14 is a perspective view of a multilayer ceramic capacitor 200 of this embodiment, and FIG. 15 is a cross-sectional view taken along line AA of FIG. 14. As shown in FIG. Hereinafter, the same reference numerals will be given to the same configurations as in the first embodiment, and the description will be omitted or simplified.

A multilayer ceramic capacitor 200 of this embodiment has a first external electrode 12, a second external electrode 13, a laminate 14 and an external dielectric 110, as shown in FIGS. The first external electrode 12, the second external electrode 13, and the laminate 14 have the same configurations as in the first embodiment described above.

Differences from the first embodiment described above are as follows. That is, in the first embodiment, the cover portion 21 of the external dielectric 11 is composed of the third covering layer 11e and the fourth covering layer 11f (see FIG. 4). On the other hand, in the laminated ceramic capacitor 200 of the present embodiment, as shown in FIG. 15, the cover portion 210 constituting the external dielectric 110 is made of a single layer and is made of the same material as the second covering layer 11d. be done. In other words, the multilayer ceramic capacitor 200 is configured such that the first covering layer 11c serves as the intermediate portion, and the second covering layer 11d and the cover portion 210 serve as the outer layer portion.

Also in the multilayer ceramic capacitor 200 of the present embodiment configured as described above, it is possible to achieve the same effects as in the above-described first embodiment, that is, to achieve both moisture resistance and capacitance. An internal electrode layer is interposed between the cover portion 210 of the external dielectric 110 and the internal dielectric 16 . This makes it relatively difficult for the sintering aid derived from the external dielectric 110 to diffuse into the laminate 14 . However, the side margin portions 20 are in direct contact with the outer dielectric 110 and the inner dielectric 16 . Therefore, a phenomenon in which the sintering aid derived from the external dielectric 110 diffuses into the laminate 14 is relatively likely to occur. Therefore, the diffusion of the sintering aid into the laminated body 14 can be suppressed by forming the first coating layer 11c, which becomes the intermediate portion, at least in the side margin portions.

Examples of the present invention will be described below.

[Example 1]
1005-shaped chips were fabricated and evaluated.

(Preparation of ceramic slurry)
Barium titanate (BaTiO ₃ ) is the main component, and Si (silicon): 0.5 mol per 100 mol of Ti, Mg (magnesium): 0.5 mol per 100 mol of Ti, Mn (manganese): per 100 mol of Ti as a sintering aid A first ceramic slurry containing 0.5 mol of V (vanadium): 0.1 mol per 100 mol of Ti was prepared. Next, a second ceramic slurry containing barium titanate as a main component and containing Si (silicon): 0.1 mol per 100 mol of Ti and Mg (magnesium): 0.1 mol per 100 mol of Ti as sintering aids; Si (silicon): 1.0 mol per 100 mol of Ti, Mg (magnesium): 1.0 mol per 100 mol of Ti, Mn (manganese): 1.0 mol per 100 mol of Ti, V (vanadium): 0.0 mol per 100 mol of Ti. A third ceramic slurry containing 2 mol was prepared.

(Preparation of 1005-shaped chip)
First ceramic green sheets having a thickness of 1.0 μm were produced from the first ceramic slurry, and internal electrode layers were laminated on the first ceramic green sheets (see FIG. 6B).

Subsequently, the first ceramic green sheets and the internal electrode layers were alternately laminated to form a laminate A (see FIG. 6(c)). At this time, each internal electrode layer was made to have different polarities alternately.

Subsequently, the second ceramic green sheets formed from the second ceramic slurry are laminated on the front and back surfaces of the laminate A, and the third ceramic green sheets formed from the third ceramic slurry are laminated on the second ceramic green sheets. was laminated to form a cover portion having a thickness of 50 μm on the laminate A (see FIG. 7A).

Next, the laminate A on which the cover portion was laminated was diced (cut) to obtain an unfired chip (see FIG. 7(b)). Subsequently, a second ceramic slurry whose viscosity was adjusted with a predetermined solvent was dipped on the side cut surface of the green chip and dried to form a second slurry layer.

Subsequently, a third slurry layer made of a third ceramic slurry whose viscosity was adjusted with a predetermined solvent was laminated on the second slurry layer to form a side margin portion having a thickness of 50 μm on the green chip. , to obtain a laminate B (see FIG. 7(c)).

Laminate B was then fired at 1280° C. in a reducing atmosphere. After firing, the sintering aid was diffused to obtain a 1005-shaped chip (hereinafter referred to as a first chip) in which an intermediate portion made of the second ceramic slurry and an outer layer portion made of the third ceramic slurry were formed. (See FIG. 8(a)). In addition, in Example 1, the thicknesses of the second slurry layer and the third slurry layer were varied to produce the first chip having different thicknesses in the intermediate portion and the outer layer portion.

(Preparation of laminate C and laminate D)
A laminate C having no intermediate portion was produced by the same method as described above, except that the third slurry layer was directly laminated on the side cut surface of the unfired chip. Furthermore, a laminate D having no outer layer portion was produced in the same manner as described above, except that the third slurry layer was not laminated on the second slurry layer.

(Characteristic test of first chip, laminate C and laminate D)
The characteristics (moisture resistance, capacitance) of the first chip having different thicknesses in the intermediate portion and the outer layer portion obtained by the above method, and the laminates C and D were evaluated. FIG. 16 is a table showing the results.

Specifically, the number of pieces = 500, test temperature = 125 ° C., relative humidity = 95% RH, applied voltage = 5 Vdc (direct current), time = 100 hours. , and the resistance value was measured when the temperature returned to room temperature. Then, those having a resistance value of less than 1 MΩ were determined to be defective in moisture resistance, and the defect rate was examined. In this test, only those with a defect rate of 0% were judged to have moisture resistance.

Sample No. 1 shown in FIG. 16 is a laminate C in which an intermediate portion is not formed. As shown in the figure, it was confirmed that the laminate C had sufficient moisture resistance and capacitance.

Further, as shown in FIG. 16, the first chips of sample numbers 2 to 5 having an intermediate portion had a capacitance of 10 μF or more and a defect rate of 0%. However, since the capacitance of the first chip of sample number 2 is lower than that of sample number 3, it was confirmed that the thickness of the intermediate portion is preferably 2 μm or more. .

In addition, as shown in FIG. 16, the first chip of sample number 6, in which the thickness of the intermediate portion was thickened, was confirmed to have poor moisture resistance. It is presumed that this is because the sinterability deteriorated due to the thin outer layer portion. Sample No. 7 shown in FIG. 16 is a laminate D in which an outer layer portion is not formed. As shown in the figure, the laminate D had a defective rate of 80%. Therefore, it was confirmed from these results that the maximum thickness of the intermediate portion is preferably 30 μm.

[Example 2]
A 1608-shaped chip was fabricated and evaluated.

(Preparation of ceramic slurry)
Barium titanate (BaTiO ₃ ) is the main component, and Si (silicon): 0.56 mol per 100 mol of Ti, Mn (manganese): 0.15 mol per 100 mol of Ti, V (vanadium): per 100 mol of Ti as a sintering aid A fourth ceramic slurry containing 0.1 mol of Ho (holmium): 0.4 mol per 100 mol of Ti was prepared. Next, barium titanate is also the main component, and as a sintering aid, Si (silicon): 1.0 mol per 100 mol of Ti, Mg (magnesium): 0.95 mol per 100 mol of Ti, Mn (manganese): per 100 mol of Ti 0.375 mol, V (vanadium): 0.2 mol per 100 mol of Ti, Ho (holmium): 0.8 mol per 100 mol of Ti, Ca (calcium): 0.3 mol per 100 mol of Ti, B (boron): 100 mol of Ti Si (silicon): 0.135 mol per Ti100 mol, Mg (magnesium): 0.5 mol per Ti100 mol, Mn (manganese): per Ti100 mol A sixth ceramic slurry containing 0.0375 mol, V (vanadium): 0.1 mol per 100 mol of Ti, and Ho (holmium): 0.4 mol per 100 mol of Ti was prepared.

(Preparation of 1608-shaped chip)
A fourth ceramic green sheet was prepared from the fourth ceramic slurry to a thickness of 1 μm after sintering, and a fourth ceramic green sheet was screen-printed onto the fourth ceramic green sheet so that the thickness after sintering would be 0.5 μm. An internal electrode layer was formed with a sufficient thickness (see FIG. 6(b)).

Subsequently, 400 fourth ceramic green sheets having internal electrode layers formed thereon were stacked to form a laminate E (see FIG. 6(c)). At this time, each internal electrode layer was made to have different polarities alternately.

Subsequently, a fifth ceramic green sheet made of a sixth ceramic slurry was laminated on the front and back surfaces of the laminate E to form a cover portion of the laminate E with a thickness of 50 μm.

Next, the laminated body E with the cover portion formed thereon was diced (cut) to obtain unfired chips. Subsequently, the side cut surface of the green chip was dipped in the fifth ceramic slurry and dried to form a BT paste.

Subsequently, a fifth slurry layer made of the sixth ceramic slurry was laminated on the BT paste to form a side margin portion having a thickness of 50 μm on the unfired chip, thereby obtaining a laminate F.

Next, the laminate F was fired at a predetermined temperature in a reducing atmosphere with a hydrogen concentration of 0.06%. After firing, the sintering aid was diffused to obtain a 1608-shaped chip (hereinafter referred to as a second chip) in which an intermediate portion made of the fifth ceramic slurry and an outer layer portion made of the sixth ceramic slurry were formed. (See FIG. 15). In this example, the second chip was manufactured with different Mn concentrations in the cover portion and the side margin portion and different firing temperatures.

(Characteristic test of second chip)
In the second chip obtained by the above method, the Vickers hardness of the surface of the cover portion (side A) and the surface of the side margin portion (side B) and the moisture resistance defect rate of the chip were examined. The humidity resistance load test was performed under the conditions of number = 500, test temperature = 85°C, relative humidity = 85% RH, applied voltage = 6.3 Vdc, and time = 14 hours. Evaluation of the defect rate and the like was performed in the same manner as in the first example.

First, the characteristics of the second chip, in which the content of Mn (manganese) in the side margin portion was fixed at 0.075 mol per 100 mol of Ti and the content of Mn (manganese) in the cover portion was different, were examined. FIG. 17 is a table showing the results.

Next, the characteristics of the second chip in which the content of Mn (manganese) contained in the cover portion is fixed at 1.125 mol with respect to 100 mol of Ti, and the content of Mn (manganese) contained in the side margin portions is different. examined. FIG. 18 is a table showing the results.

As shown in FIGS. 17 and 18, when both sides A and B have a Vickers hardness of 650 or more and the ratio of the Vickers hardness of the A side to the B side is 1.00 or more, the product can be produced without poor moisture resistance. confirmed to be possible. Therefore, from this result, it was confirmed that the moisture resistance of the second chip was ensured when the cover portion and the side margin portion had a predetermined hardness.

Next, the characteristics of chips with different concentrations of Mn contained in the BT paste and different firing temperatures were examined. FIG. 19 is a table showing the results. From these results, it was confirmed that the method of controlling the Vickers hardness by changing the firing temperature affects the entire product, resulting in a shortened product life. Therefore, it is desirable to adjust the sinterability by, for example, adding a manganese compound such as manganese oxide to the cover portion and the side margin portions.

In this example, the 1608-shaped chip was explained as an example, but the chip size is not limited to this, and products of other shapes (or sizes) such as 1005-shaped are evaluated by the same index. It is possible to

[Example 3]
A multilayer ceramic capacitor (MLCC) according to Example 3 was produced.

(Preparation of ceramic slurry)
First, barium titanate (BaTiO ₃ ) powder with an average particle size of 100 nm was prepared as raw material powder for the internal dielectric and external dielectric (cover portion and side margin portion).

Next, a seventh ceramic slurry was prepared, which contained this barium titanate as a main component and was used as the basis of the internal dielectric. The seventh ceramic slurry contains 1.15 mol of Si (silicon) per 100 mol of Ti, 0.08 mol of Mn (manganese) per 100 mol of Ti, and 0.13 mol of B (boron) per 100 mol of Ti as sintering aids. , 0.1 mol of V (vanadium) per 100 mol of Ti, and 1.0 mol of Ho (holmium) per 100 mol of Ti. Also, Ba/Ti and A/B were set to 1.0100 and 1.0050, respectively.

Further, an eighth ceramic slurry was prepared, which also contained barium titanate as a main component and was used as a base for the external dielectric. In the eighth ceramic slurry, as sintering aids, Si (silicon) is 2.00 mol per Ti 100 mol, Mn (manganese) is 2.25 mol per Ti 100 mol, and B (boron) is 0.26 mol per Ti 100 mol. , 0.1 mol of V (vanadium) per 100 mol of Ti, and 1.0 mol of Ho (holmium) per 100 mol of Ti. Also, Ba/Ti and A/B were set to 1.0100 and 1.0075, respectively.

(Preparation of MLCC molded body)
Subsequently, using the seventh ceramic slurry and the eighth ceramic slurry, MLCC molded bodies were produced. A detailed manufacturing method is shown below.

First, a seventh ceramic green sheet having a thickness of 1.0 μm was produced from the seventh ceramic slurry by a doctor blade method. Then, a conductive paste film containing Ni was formed on the seventh ceramic green sheet in a predetermined pattern by screen printing.

Subsequently, an eighth slurry layer made of eighth ceramic slurry and having the same thickness as the conductive paste film was formed by screen printing on the seventh ceramic green sheet on which the conductive paste film was formed. At this time, a gap of 5 μm was formed between the conductive paste film and the eighth slurry layer.

Subsequently, 201 sheets of the seventh slurry layer on which the conductive paste film and the eighth slurry layer were formed were stacked so that the sides from which the conductive paste film was pulled out were alternated to obtain a laminate G. Next, a plurality of ninth slurry layers made of the eighth ceramic slurry were laminated on the upper and lower surfaces of the laminate G to form a cover portion having a thickness of 20 μm.

Subsequently, the laminated body G having the cover portion formed thereon was cut into a predetermined size to obtain a rectangular parallelepiped laminated body H. Next, by laminating a plurality of ninth slurry layers on both side surfaces of the laminate H to form side margin portions having a thickness of 40 μm, the length direction, width direction and height direction are each 0.000. MLCC moldings of 6 mm, 0.3 mm and 0.3 mm were obtained.

(Fabrication of multilayer ceramic capacitor)
A laminated ceramic capacitor was produced using the MLCC molded body obtained by the above method. Specifically, after removing the binder from the MLCC molded body at 300° C. in a nitrogen atmosphere, the temperature was raised from 1150° C. to 1250° C. at a rate of 600° C./hr in a reducing atmosphere containing H ₂ (hydrogen), It was baked by holding for 10 minutes to 2 hours. After the temperature was lowered, the temperature was raised from 800° C. to 1050° C. in a nitrogen atmosphere, and reoxidation was performed while maintaining the temperature at 1050° C. to obtain an MLCC sintered body.

Next, a Ni paste containing glass frit was applied to both end surfaces of the MLCC sintered body where the internal electrode layers were exposed. Then, a baking process was performed in a nitrogen atmosphere to form external electrodes to obtain a multilayer ceramic capacitor (see FIG. 8(b)).

[Example 4]
A multilayer ceramic capacitor (MLCC) according to Example 4 was produced.

First, barium titanate (BaTiO ₃ ) obtained by the same method as in Example 3 was used to prepare a ninth ceramic slurry that serves as a base for the internal dielectric. In the ninth ceramic slurry, as sintering aids, Si (silicon) is 1.15 mol per Ti 100 mol, Mn (manganese) is 0.08 mol per Ti 100 mol, and B (boron) is 0.13 mol per Ti 100 mol. , 0.093 mol of V (vanadium) per 100 mol of Ti, and 0.75 mol of Ho (holmium) per 100 mol of Ti.

Next, a tenth ceramic slurry was prepared which also contained barium titanate as a main component and was used as a base for the external dielectric. The tenth ceramic slurry contains 1.15 mol of Si (silicon) per 100 mol of Ti, 0.08 mol of Mn (manganese) per 100 mol of Ti, and 0.13 mol of B (boron) per 100 mol of Ti as sintering aids. , 0.093 mol of V (vanadium) per 100 mol of Ti, 0.75 mol of Ho (holmium) per 100 mol of Ti, and 1.00 mol of Mg (magnesium) per 100 mol of Ti.

Subsequently, in the same manner as in Example 3, the 9th ceramic slurry and the 10th ceramic slurry were used to produce an MLCC molded body, and then a multilayer ceramic capacitor was obtained.

[Comparative Examples 1 to 3]
Multilayer ceramic capacitors according to Comparative Examples 1 to 3 were produced.

A laminated ceramic capacitor according to Comparative Example 1 was produced in the same manner as in Example 3, except that the outer dielectric contained only Si (silicon) in a larger amount than the inner dielectric.

A laminated ceramic capacitor according to Comparative Example 2 was produced in the same manner as in Example 3, except that the outer dielectric contained more Si (silicon) and B (boron) than the inner dielectric.

A laminated ceramic capacitor according to Comparative Example 3 was produced in the same manner as in Example 3, except that the content of each sintering aid contained in the outer dielectric and the inner dielectric was the same.

[Characteristic test of multilayer ceramic capacitor]
The characteristics (capacity, capacitance ratio, moisture resistance defect rate) of the multilayer ceramic capacitor obtained by the above method were investigated. FIG. 20 shows the ratio of the sintering aid contained in the internal dielectric and the external dielectric of the multilayer ceramic capacitors according to Examples 3 and 4 and Comparative Examples 1 to 3, and the results of characteristic tests of each multilayer ceramic capacitor. It is a table showing

Comparing Example 3 and Comparative Example 3, it was confirmed that poor moisture resistance was improved when the outer dielectric contained more sintering aid than the inner dielectric.

In addition, as shown in Example 4 of FIG. 20, it can be seen that even in a structure in which the outer dielectric contains more magnesium than the inner dielectric, the moisture resistance is improved, and the capacitance to capacitance ratio is maintained.

Further, when comparing Example 3 with Comparative Examples 1 and 2, it can be seen that the structure of Example 3 is improved not only in terms of moisture resistance, but also in capacity and capacity ratio. As a result, compared to the structure in which the external dielectric contains more Mg than the internal dielectric, the structure containing a large amount of multiple types of sintering aids including Mn (manganese) as in Example 3 has a higher moisture resistance. It was confirmed that not only defects but also capacity and capacity ratio could be improved.

DESCRIPTION OF SYMBOLS 10, 200... Laminated ceramic capacitor 11, 110... External dielectric 12... 1st external electrode 13... 2nd external electrode 14... Laminated body 15... 1st internal electrode layer 16 Inner dielectric 17 Second internal electrode layer 18 Intermediate portion 19 Outer layer portion 20 Side margin portion 21, 210 Cover portion

Claims (4)

through an internal dielectric formed of a ceramic dielectric containing a sintering aid consisting of at least one of manganese and magnesium and at least one of silicon, boron, holmium, calcium, and vanadium; Internal electrode layers and second internal electrode layers are alternately laminated, and have a first surface that is a surface in the lamination direction, a second surface that is a surface opposite to the first surface, and the first surface. and a third surface perpendicular to the second surface and from which the first internal electrode layers and the second internal electrode layers are drawn, and a surface opposite to the third surface, the A fourth surface from which the first internal electrode layers and the second internal electrode layers are drawn, and the first surface, the second surface, the third surface, and the fourth surface are orthogonal to each other. and a fifth surface from which the first internal electrode layers are drawn, and a sixth surface opposite to the fifth surface and from which the second internal electrode layers are drawn. and a cover portion made of a ceramic dielectric containing a larger amount of the sintering aid than the internal dielectric and covering the first surface and the second surface. ,
A first side-cut surface including the third surface of the chip and a second side-cut surface including the fourth surface are formed of a ceramic dielectric containing a larger amount of the sintering aid than the internal dielectric. a side margin portion covering the
a first external electrode covering the fifth surface and electrically connected to the first internal electrode layer;
a second external electrode covering the sixth surface and electrically connected to the second internal electrode layer;
The side margin portion is composed of a first inner layer and a first outer layer, and the first outer layer has a higher concentration of the sintering aid than the first inner layer.
Multilayer ceramic capacitor. The multilayer ceramic capacitor according to claim 1,
The cover portion is composed of a second inner layer and a second outer layer, and the second outer layer has a higher concentration of the sintering aid than the second inner layer.
Multilayer ceramic capacitor. The multilayer ceramic capacitor according to claim 1 or 2,
A multilayer ceramic capacitor, wherein the inner dielectric, the cover portion, and the side margin portion contain at least one of silicon and vanadium. A multilayer ceramic capacitor according to any one of claims 1 to 3,
Vickers hardness of the cover portion and the side margin portion is 650 or more,
A multilayer ceramic capacitor, wherein a ratio of the Vickers hardness of the cover portion to the Vickers hardness of the side margin portion is 1.00 or more.

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