CN1770343A - Multilayered chip capacitor array - Google Patents
Multilayered chip capacitor array Download PDFInfo
- Publication number
- CN1770343A CN1770343A CNA2005101154101A CN200510115410A CN1770343A CN 1770343 A CN1770343 A CN 1770343A CN A2005101154101 A CNA2005101154101 A CN A2005101154101A CN 200510115410 A CN200510115410 A CN 200510115410A CN 1770343 A CN1770343 A CN 1770343A
- Authority
- CN
- China
- Prior art keywords
- conductive via
- internal electrode
- group
- chip capacitor
- capacitor array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors
- H01G4/385—Single unit multiple capacitors, e.g. dual capacitor in one coil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
Abstract
Disclosed herein is a multilayered chip capacitor array, including a capacitor body having a plurality of dielectric layers, a plurality of pairs of first and second inner electrodes which are formed on the plurality of dielectric layers such that one electrode of one pair of inner electrodes faces the other electrode of the one pair of inner electrodes with one of the plurality of dielectric layers interposed therebetween, at least one first outer terminal and a plurality of second outer terminals formed on at least one surface of a top surface and a bottom surface of the capacitor body, and at least one first conductive via and a plurality of second conductive vias formed in a stacking direction of the capacitor body and connected to the first outer terminal and the second outer terminal, respectively.
Description
Technical field
A kind of multi-layer chip capacitor of relate generally to of the present invention, and more particularly, relate to a kind of multi-layer chip capacitor that a plurality of capacitors are provided in monolithic.
Background technology
Multi-layer chip capacitor (MLCC) has the structure of being made up of the internal electrode that is folded between a plurality of dielectric layers, and this is known to those skilled in the art.Because small size, big capacity and easy-to-install advantage, MLCC has been widely used in various electronic installations.
Recently,, need a kind of multilayered chip capacitor array, it is characterized in that, in monolithic, make two or more capacitors with identical or different static capacity for size and the realization that reduces part is easy to installation process.
Fig. 1 a and 1b are respectively decomposition diagram and the perspective schematic view that traditional multilayered chip capacitor array is shown.
Shown in the decomposition diagram of Fig. 1 a, two first internal electrode 12a and 12b and two second internal electrode 13a and 13b are respectively formed on a plurality of dielectric layer 11a and the 11b.The first and second internal electrode 12a, 12b, 13a and 13b have lead-in wire 14a, 14b, 15a and the 15b that extends from the one side. Dielectric layer 11a and 11b with the first and second internal electrode 12a, 12b, 13a and 13b shown in Fig. 1 a pile up each other, to form the capacitor body 11 shown in Fig. 1 b.In addition, obviously find out, be provided with external terminal 16a, the 16b, 17a and the 17b that are connected to lead-in wire 14a, 14b, 15a and 15b, thereby obtained multi-layer chip capacitor 10 from Fig. 1 b.
Like this, at first and second internal electrode 12a and the 13a of structure one side, and the effect of playing the independent capacitance device at the first and second internal electrode 12b and the 13b of another example.Traditional multilayered chip capacitor array 10 of describing among Fig. 1 a and the 1b is included in the capacitor that horizontal direction is arranged, therefore, when using three or more capacitors, is difficult to reduce its size.
In addition, traditional multilayered chip capacitor array 10 need have less equivalent series inductance (ESL), to be used as the decoupling capacitor between the power supply that is connected in semiconductor chip and the LSI power circuit especially.
In order to reduce equivalent series inductance, United States Patent (USP) the 5th, 880 discloses the structure of a plurality of lead-in wires in the arranged crosswise of the lead-in wire with opposite polarity No. 925.Yet above-mentioned structure is not suitable for having traditional multilayered chip capacitor array of the internal electrode of a plurality of horizontal arrangement.That is, under the situation that the number of leads on the side of the single internal electrode of the multilayered chip capacitor array shown in Fig. 1 a doubles, the quantity of capacitor has increased twice.Therefore, be difficult in limited space, increase the quantity of lead-in wire, to obtain the effect that reduces ESL of expectation.
In addition, traditional multilayered chip capacitor array is disadvantageous, because its size is because structural limitations and can not reducing, and its limitation has influenced for reducing the change of the pin configuration that ESL makes.
Summary of the invention
Therefore, the present invention is intended to solve the problems referred to above that exist in the prior art, and an object of the present invention is to provide a kind of multilayered chip capacitor array, it is characterized in that, the a plurality of capacitors that use at conductive via that forms on the stacking direction (conductive via) and the external terminal that forms on the end face of capacitor body and bottom surface are provided, and conductive via is by suitable setting, to realize reducing the effect of ESL.
Another object of the present invention is for multilayered chip capacitor array provides a kind of wiring construction, and it has the suitable inner connecting structure that uses with above-mentioned multilayered chip capacitor array.
In order to realize above-mentioned purpose, the invention provides a kind of multilayered chip capacitor array, comprising: capacitor body has a plurality of dielectric layers that are stacked; A plurality of first and second internal electrodes are right, are formed on a plurality of dielectric layers, make a electrode surface another electrode in pair of internal electrodes in the pair of internal electrodes to insert and put in a plurality of dielectric layers between it; At least one first external terminal and a plurality of second external terminal are formed at least one surface of the end face of capacitor body and bottom surface; And at least one first conductive via and a plurality of second conductive via, be formed on the fabrication orientation of capacitor body, and be connected to first external terminal and second external terminal respectively, wherein, at least one first conductive via be connected to first internal electrode and with the second internal electrode electric insulation, a plurality of second conductive vias are divided into k (k 〉=2) group, every group has one second conductive via at least, and second internal electrode be divided into k group, every group has one second internal electrode at least, and every group of second conductive via be connected to every group of second internal electrode and with other group and first internal electrode electric insulations of second internal electrode.
Preferably, first and second conductive vias are set, feasible magnetic field by the induction by current that flows into connected internal electrode is cancelled, thereby reduces ESL.
In reducing the preferred embodiment of ESL,, be set to uniformly-spaced to separate with first conductive via of being scheduled to predetermined every group second adjacent conductive via of first conductive via.In addition, a plurality of first conductive vias are set, wherein, first and second conductive vias are separately positioned on the angle of regular square, to reduce ESL.Especially, in the present embodiment, first conductive via is arranged on the diagonal on two angles respect to one another, and second conductive via is arranged on other two angles.
According to this embodiment, be connected to one group of second internal electrode of second conductive via, with other components of second conductive via from and electric insulation, make two groups of internal electrodes not be connected to the second identical conductive via group.On the contrary, MLCC comprises second conductive via that is connected to two group of second internal electrode at least.
In addition, every group second internal electrode has equal quantity, makes each capacitor have identical static capacity.On the contrary, at least one group second internal electrode has and is different from the quantity that other organize second internal electrode, and at least one capacitor has different static capacities thus.Similarly, at least one group second conductive via has the quantity that is different from second other groups of conductive via.
The present invention also provides a kind of wiring construction of multilayered chip capacitor array, comprising: base board (baseboard) has at least two power lines and an earth connection; And multilayered chip capacitor array bag, be installed on the base board and have the wiring substrate, this wiring substrate has microprocessor unit (MPU) chip and is installed in the multilayered chip capacitor array of wiring below the substrate, wherein, multilayered chip capacitor array comprises: capacitor body has a plurality of dielectric layers that are stacked; A plurality of first and second internal electrodes are right, are formed on a plurality of dielectric layers, make an electrode surface another electrode in inner electrode pair of internal electrode centering, are gripped with of a plurality of dielectric layers between it; At least one first external terminal and a plurality of second external terminal are formed at least one surface of the end face of capacitor body and bottom surface; And at least one first conductive via and a plurality of second conductive via, be formed on the fabrication orientation of capacitor body, and be connected to first external terminal and second external terminal respectively, wherein, described at least one first conductive via be connected to first internal electrode and with the second internal electrode electric insulation, wherein, a plurality of second conductive vias are divided into k (k 〉=2) group, every group has one second conductive via at least, and second internal electrode is divided into the k group, every group has one second internal electrode at least, and each group of second conductive via be connected to second internal electrode each group and with second internal electrode other group and first internal electrode electric insulations, wherein, earth connection is connected to first external terminal, and power line is connected to second external terminal respectively, each second external terminal is connected to each group that k organizes second conductive via, and wherein, in power line and the earth connection at least one first and second conductive vias by multi-layer chip capacitor corresponding one be connected to the MPU chip.
Description of drawings
From below in conjunction with being more readily understood above-mentioned and other purposes of the present invention, feature and other advantages the detailed description of accompanying drawing, in the accompanying drawings,
Fig. 1 a and 1b are respectively the decomposition diagram and the perspective schematic view of traditional multilayered chip capacitor array;
Fig. 2 a and 2b are respectively according to the perspective schematic view of the multilayered chip capacitor array of the first embodiment of the present invention and side cross-sectional view;
Fig. 3 a to 3c illustrates the conductive via of each dielectric layer that is applied to the multilayered chip capacitor array shown in Fig. 2 b and the schematic diagram of internal electrode;
Fig. 4 a and 4b illustrate the schematic diagram that the ESL in multilayered chip capacitor array according to the present invention reduces effect;
Fig. 5 a to 5c is the vertical view and the sectional view of multilayered chip capacitor array according to a second embodiment of the present invention;
Fig. 6 a and 6b are respectively the vertical view and the sectional views of the multilayered chip capacitor array of a third embodiment in accordance with the invention;
Fig. 7 shows the embodiment of the wiring construction of multilayered chip capacitor array of the present invention;
Fig. 8 shows another of wiring construction of multilayered chip capacitor array of the present invention
Embodiment.
Embodiment
Below, describe multilayered chip capacitor array of the present invention with reference to the accompanying drawings in detail.
Fig. 2 a and 2b are respectively according to the perspective schematic view of the multilayered chip capacitor array of the first embodiment of the present invention and side cross-sectional view.According to first embodiment, multilayered chip capacitor array comprises two capacitors.Shown in Fig. 2 a, multilayered chip capacitor array 20 comprises capacitor body 21, is formed with first external terminal 27 and two group of second external terminal 26a and 26b on capacitor body.First external terminal 27 is connected to negative electrode and is connected to two capacitors.One group of second external terminal 26a is set to the anode terminal of a capacitor, and another organizes the anode terminal that the second external terminal 26b is set to another capacitor.In Fig. 2 a, show the end face of capacitor body.Its bottom surface can be formed with external terminal 26a, 26b and 27, corresponding to the external terminal of its end face.
According to first embodiment, can be by vertical conduction via hole 25,24a and the 24b that in Fig. 2, can see, realize being connected between first and second external terminals 27,26a and 26b and internal electrode 22a, 22b, 23a and the 23b.Fig. 2 b is the sectional view along the line A-A ' in the multilayered chip capacitor array 20 shown in Fig. 2 a.
Shown in Fig. 2 b, the capacitor body 21 of multilayered chip capacitor array 20 comprises a plurality of dielectric layer 21a-21e that are stacked.The first internal electrode 23a and 23b and the second internal electrode 22a and 22b alternately arrange, make dielectric layer 21b-21d be interposed in respectively between the first and second internal electrode 22a, 23a, 22b and the 23b.
First conductive via 25 is connected to two first internal electrode 23a and 23b, and the first outer cloth terminals 27 are electrically connected with the first internal electrode 23a and 23b thus.Yet first conductive via 25 is by open region (open region) and two second internal electrode 22a and 22b electric insulation.
Shown in the C among Fig. 2 b, one second conductive via 24a is connected to one second internal electrode 22a, therefore the second internal electrode 22a is electrically connected with the second outer cloth terminals 26a.In addition, shown in the O among Fig. 2 b, the second conductive via 24a is by open region and the first internal electrode 23a and 23b and another second internal electrode 22b electric insulation.Like this, another second conductive via 24b is connected to another second internal electrode 22b, makes the second internal electrode 22b be electrically connected with the second external terminal 26b.In addition, the second above-mentioned conductive via 24b is by open region and the first internal electrode 23a and 23b and another second internal electrode 22a electric insulation.
Fig. 2 b shows the external terminal foremost row on A-A ' direction and the syndeton of internal electrode, and wherein internal electrode is connected to external terminal by conductive via.Like this, other of external terminal worked and use conductive via and have syndeton with internal electrode.
Just, shown in Fig. 2 b, when first external terminal 27 was connected to the first internal electrode 23a and 23b by first conductive via 25, itself and the second internal electrode 22a and 22b electricity disconnected.Formation relates to the second external terminal 26a of first positive polarity and relates to the second external terminal 26b of second positive polarity, only to be electrically connected with the minimum second internal electrode 22a and another second internal electrode 22b respectively.
In particular with reference to Fig. 3 a to 3c the syndeton shown in Fig. 2 b is described.
Fig. 3 a to 3c shows conductive via 24a, the 24b and 25 and the arrangement of internal electrode 22a, 22b, 23a and the 23b of dielectric layer 21a, 21b, 21c and 21d of the multilayered chip capacitor array 20 that is applied to Fig. 2 b.
Fig. 3 a shows the second internal electrode 22a on the first dielectric layer 21a that is formed on Fig. 2 b.As shown in FIG., the second internal electrode 22a only is connected with the second conductive via 24a that relates to first positive polarity, and by open region and first conductive via 25 and the disconnection of another second conductive via 24b electricity.
Shown in Fig. 3 b, the second internal electrode 22b that is formed on the 3rd dielectric layer 21c only is connected with the second conductive via 24b that relates to second positive polarity, and by open region and first conductive via 25 and the disconnection of another second conductive via 24a electricity.
In addition, shown in Fig. 3 c, be respectively formed at first internal electrode 23a and the 23b on the second dielectric layer 21b and the 4th dielectric layer 21d, be connected, and disconnect with all second conductive via 24a and 24b electricity with first conductive via 25 that relates to negative polarity.
Layout according to first embodiment is favourable, and this is compensated because of the magnetic field by the induction by current that flows into internal electrode.Just, shown in Fig. 3 a or 3b, first and second conductive vias 25,24a and 24b are separately positioned on the angle of regular square.In addition, first conductive via 25 is arranged in four angles along on diagonal two angles respect to one another, and another organizes the second conductive via 24a and 24b (relating to first positive polarity and second positive polarity) is arranged on two other angles.Like this, first and second conductive vias 25,24a and the 24b that relates to opposite polarity is set to adjacent regularly, and thus as shown by arrows, the sense of current may be opposite at the corresponding first and second internal electrode 22a, 23a, 22b and 23b.Therefore, the result of effective compensation in the magnetic field that is produced is significantly reducing of ESL.
Fig. 4 a and 4b illustrate the schematic diagram that ESL in the multilayered chip capacitor array of the present invention reduces effect.
Shown in Fig. 4 a, in the multilayered chip capacitor array shown in Fig. 2 b, when when first external terminal 27 applies voltage with the second external terminal 26a that relates to first positive polarity, be connected to the second conductive via 24a of the second external terminal 26a, and first conductive via 25 adjacent with above-mentioned via hole 24a produces the opposite magnetic flux that can be used as compensation.In addition, shown in Fig. 4 b, when when first external terminal 27 applies voltage with the second external terminal 26b that relates to second positive polarity, be connected to the second conductive via 24b of the second external terminal 26b and first conductive via 25 adjacent and produce the opposite magnetic flux that can be used as compensation with above-mentioned via hole 24b.Therefore, passing in conductive via 24a, 24b and 25 the vertical syndeton according to of the present invention, magnetic field reduces between the adjacent conductive vias of opposite polarity having, and has therefore effectively reduced ESL.
With predetermined every group second adjacent conductive via of first conductive via, can be set to uniformly-spaced to separate with first conductive via of being scheduled to.Similarly, shown in Fig. 5 a to 5c, the layout that can change conductive via is to be easy to connect external terminal and external circuit.
Fig. 5 a to 5c is the vertical view and the sectional view of multilayered chip capacitor array 50 according to a second embodiment of the present invention.
Shown in Fig. 5 a, the end face of capacitor body 51 is formed with first external terminal 57 that relates to negative polarity, relates to second external terminal 56a of first positive polarity and second external terminal that relates to second positive polarity.Similarly, eight first external terminals 57 are arranged in two row in a side of the end face of capacitor body 51, and the second external terminal 56a and 56b be divided into group, and wherein per four with the regular square arrangements in other two row.
Fig. 5 b shows along the sectional view of Fig. 5 a center line B-B '.Shown in Fig. 5 b, first conductive via 55 that is connected with first external terminal 57 and the second conductive via 54a that is connected with the second external terminal 56a that relates to first positive polarity are connected to the first and second internal electrode 52a, 53a and 53b.
First conductive via 55 is connected to two first internal electrode 53a and 53b, being electrically connected with first external terminal 57 and the first internal electrode 53a and 53b, and by open region and two second internal electrode 52a and 52b electric insulation.In addition, the second conductive via 54a is connected to one second internal electrode 52a, so that the second internal electrode 52a is electrically connected to second external terminal 56, and this second conductive via is by the open region and first internal electrode 53 and another the second internal electrode 52b electric insulation.
Fig. 5 c is the sectional view along Fig. 5 a center line C-C '.Shown in Fig. 5 c, first conductive via 55 that is connected with first external terminal 57 and the second conductive via 54b that is connected with the second external terminal 56b with second positive polarity are connected to the first and second internal electrode 52b, 53a and 53b.
First conductive via 55 with Fig. 5 b in identical mode be connected to two first internal electrode 53a and 53b, so that first external terminal 57 is electrically connected with the first internal electrode 53a and 53b, and this first conductive via is by open region and two second internal electrode 52a and 52b electric insulation.In addition, the second conductive via 54b is connected to one second internal electrode 52b, so that the second internal electrode 52b is electrically connected with the second external terminal 56b, and this second conductive via is by open region and the first internal electrode 53a and 53b and another second internal electrode 52a electric insulation.
Multilayered chip capacitor array according to second embodiment is disadvantageous, because desired ESL reduce effect only two adjacent in the middle of in the row, these two adjacent in the middle of row between first external terminal 57 and the second external terminal 56a and 56b, have opposite polarity; But the multilayered chip capacitor array according to second embodiment is again favourable, easily finishes installation process because can arrange by simple terminal.
Similarly, first and second conductive vias plural number that is set to equate.This situation is exemplary, so that explain.Alternatively, because first conductive via has common polarity, therefore only need to use one first conductive via.
Although described the multilayered chip capacitor array with two capacitors, it can have three or more capacitors.In this case, make such multilayered chip capacitor array by realizing above-mentioned syndeton, wherein syndeton is used a plurality of second conductive vias and a plurality of second internal electrode of the group that is divided into the quantity that equals capacitor.
Fig. 6 a and 6b are respectively the vertical view and the sectional views of the multilayered chip capacitor array with three capacitors 60 of a third embodiment in accordance with the invention.Multilayered chip capacitor array 60 comprises three capacitors, and it has the syndeton that only forms respectively for positive polarity when having common cathodic.
In Fig. 6 a, the end face of capacitor body 61 (or bottom surface) is formed with first external terminal 67 that relates to negative polarity and the second external terminal 66a, 66b and the 66c that relates to positive polarity.Second external terminal that relates to positive polarity is divided into the second external terminal 66a, 66b and the 66c that relates to first to the 3rd positive polarity.
Arrange as for the external terminal according to the 3rd embodiment, the external terminal of positive polarity is positioned on the angle of regular square, and the external terminal of negative polarity is positioned at the core of regular square.
Fig. 6 b is the sectional view along Fig. 6 a center line D-D '.In Fig. 6 b, following syndeton has been described: first conductive via 65 that is connected with first external terminal 67, and the second conductive via 64a, the 64b and the 64c that are connected with 66c with the second external terminal 66a, the 66b that relate to first to the 3rd positive polarity.
First conductive via 65 is connected to three first internal electrode 63a, 63b and 63c, so that first external terminal 67 is electrically connected with the first internal electrode 63a, 63b and 63c, and this first conductive via disconnects by open region and three second internal electrode 62a, 62b and 62c electricity.
In addition, each the second conductive via 64a, the 64b and the 64c that relate to first to the 3rd polarity are connected to one second internal electrode 62a, 62b or 62c, and by open region and the first internal electrode 63a, 63b and 63c and two other second internal electrode 62b and 62c, 62a and 62c or 62a and the disconnection of 62b electricity.
According to the 3rd embodiment, the second conductive via 64c that relates to the 3rd positive polarity may be more than second conductive via 64a and the 64b that relates to another positive polarity.The second conductive via 64c that relates to the 3rd positive polarity is connected to the second internal electrode 62c (its equal to be connected to the internal electrode 62a of another second conductive via 64a or 64b or the quantity of 62b), and is connected to the both sides of the wide interval that is separated from each other simultaneously.
Similarly, one group of second internal electrode that is connected to second conductive via that relates to positive polarity can have the quantity of the internal electrode that is different from other groups, to demonstrate different static capacities.In addition, although in the present embodiment, second internal electrode is set to not overlapping state with the corresponding second conductive via group, organizes second conductive via but at least one second internal electrode can be connected to another that relate to positive polarity, to realize multiple array of capacitors structure.
In the above-described embodiment, first and second external terminals are set to correspond respectively to the quantity of first and second conductive vias.Alternatively, the same external group of terminals with identical polar can be connected to each other, and therefore, it can be by partly integrated.For example, in Fig. 3 a, can be on to the angular direction printing conductive material in addition, therefore, the same external group of terminals with identical polar can be connected to each other.In Fig. 6 a, can be on column direction printing conductive material in addition, external terminal can be connected according to group thus.
Be shown and be described as square shape according to the MLCC of the foregoing description and (see Fig. 2, Fig. 3 a-3c, Fig. 5 a and Fig. 6 a).Yet MLCC can comprise other shapes, for example rectangle.For the MLCC of rectangular shape, the quantity of the conductive via that lists can be different from the quantity of the conductive via on the row.In this case, be appreciated that above-mentioned regular square shape is the part of rectangular shape MLCC.
Multilayered chip capacitor array of the present invention need have new wiring construction, so that it can use as decoupling capacitor in practice.For example, the multilayered chip capacitor array shown in Fig. 2 a and 2b need be fit to relate to first external terminal 27 of negative polarity and relate to second external terminal 26a of first and second positive polaritys and the wiring construction of 26b.Preferably, wiring construction allows to shorten circuit by first and/or second conductive via that forms by multilayered chip capacitor array, minimizes stray inductance thus.
Fig. 7 and 8 shows the different embodiment of such wiring construction.Can be understood as the multilayered chip capacitor array of describing with reference to Fig. 2 A and 2B at the multilayered chip capacitor array of this employing, but be not limited thereto.
At first with reference to Fig. 7, the wiring construction 100 of multi-layer chip capacitor comprises base board 91 (for example, PC plate) and multilayered chip capacitor array bag 80.
Multilayered chip capacitor array bag 80 comprises: wiring substrate 81 has interior circuit element 83a, 83b, 84a, 84b, 87a, 87b, 87c, 88a, 88b and 88c; And microprocessor unit (MPU) 85, be installed in the wiring substrate 81 the top.Wiring substrate 81 also has the cavity zone C that is formed on its underpart, and it provides the space that is used for installing therein multilayered chip capacitor array 20.
The first and second power line PWL1 and PWL2 and earth connection GND are installed on the base board 91.Earth connection GND is set to pass base board 91, and is connected to second external terminal 27 that is positioned at below the multilayered chip capacitor array 20 by electrical connector (for example welding S).Earth connection GND also is connected to first external terminal 27 that is positioned at multilayered chip capacitor array 20 tops by the conductive via 25 of multilayered chip capacitor array 20, and by interior circuit element 84c, the 87c of wiring substrate 81 and the chip terminal 86 that 88c is connected to MPU 85.
The first and second power line PWL1 and PWL2 are connected to the terminal 86 of MPU chip 85 and the terminal 26a and the 26b of multi-layer chip capacitor 20 by interior circuit element 83a, 83b, 84a, 84b, 87a, 87b, 88a and 88b, and MPU chip 85 is connected to multi-layer chip capacitor 20 by interior circuit element 84a, 84b, 87a, 87b, 88a and 88b.
Like this, when MPU chip 85 was connected to base board 91 by first conductive via 25, multilayered chip capacitor array 20 and MPU chip 85 can be shortened with the access path of earth connection GND.This can simplified wiring substrate 81 manufacturing process, and owing to the shortening to the access path of earth connection GND reduces stray inductance.
Though having described, embodiment shown in Figure 7 has two capacitor parts, and wherein external terminal is set to the multi-layer chip capacitor 20 of two groups of 26a and 26b, but wiring construction 100 of the present invention can be applied to have the multilayered chip capacitor array of three or more capacitor parts similarly.More particularly, can the power line of base board 91 be installed in addition and use syndeton shown in Figure 7, realize suitable wiring construction by quantity (quantity of external terminal group) according to capacitor part.
As mentioned above, by the MPU chip being connected to many power lines, can suitably select capacitor volume according to adjustable electric current through multilayered chip capacitor array.
Only earth connection GND is by first conductive via, 25 connected layouts though present embodiment has been described wherein, and at least one among the first and second power line PWL1 and the PWL2 can additionally or optionally be connected to MPU chip 85 by the second conductive via 24a and 24b.
In addition, all first and second power line PWL1 can be connected with 24b by first and second conductive vias 25, the 24a of multilayered chip capacitor array 20 with PWL2 and earth connection GND, the circuit element 83a and the 83b of the wiring substrate 81 that interrelates with further omission and the first and second power line PWL1 and PWL2.
With reference to Fig. 8, the wiring construction 130 of multilayered chip capacitor array comprises base board 121 (for example PC plate) and multilayered chip capacitor array bag 110.Multilayered chip capacitor array bag 110 comprises: wiring substrate 111 has vertical Connection Element 117a, 117b and 117c such as conductive via; And microprocessor unit (MPU) 115, be installed in the wiring substrate 111 the top.Cavity zone C is arranged on the bottom of wiring substrate 111, and it provides the space that is used for installing therein multilayered chip capacitor array 20.
The first and second power line PWL1 and PWL2 and earth connection GND are installed on the base board 121.Be set to pass all first and second power line PWL1 and the PWL2 and the earth connection GND of base board 121, by be connected to external terminal 26a, the 26b and 27 below multilayered chip capacitor array 20 such as the electrical connector S that welds.More particularly, earth connection GND is connected to first external terminal that relates to negative polarity, the first power line PWL1 is connected among the second external terminal 26a that relates to first positive polarity, and second source line PWL2 is connected among the second external terminal 26b that relates to second positive polarity another.
The result, base board wired PWL1 and PWL2 and line GND by first and second conductive vias 25,24a and the 24b of multilayered chip capacitor array 20, be connected to first and second external terminals 27,26a and 26b on the top of multilayered chip capacitor array 20.At external terminal 27,26a and the 26b at top also by vertical Connection Element 117a, the 117b of wiring substrate 31 and the terminal 116 that 117c is connected to MPU chip 115.
As mentioned above, the first and second conductive via 24a, the 24b and 25 of multilayered chip capacitor array 20 can shorten the access path between MPU chip 115 and the base board 121, thus simplified manufacturing technique.The access path that reduces can reduce stray inductance equally.
In addition, first and second external terminals 27,26a and the 26b of the multilayered chip capacitor array of this embodiment has with the layout of the terminal 116 of MPU chip 115 and roughly the same at interval layout and at interval, makes interior (circuit) element of wiring substrate only to be formed by vertical Connection Element 117a, 117b and 117c such as conductive via.As a result, the inner track of wiring substrate 111 can be simplified or shorten extraly, thereby has more effectively reduced stray inductance.
As mentioned above, the invention provides a kind of multilayered chip capacitor array, it is characterized in that: a plurality of capacitors are not horizontal arrangement, but vertically connect by conductive via, and therefore the layout by conductive via has reduced ESL effectively.In addition, wiring construction of the present invention allows by the conductive via of multilayered chip capacitor array at least one power line and earth connection to be connected directly to the MPU chip, thereby optionally adjusts the electric capacity of decoupling capacitor according to adjustable current source.This can also further simplify wiring construction, thereby reduces stray inductance effectively.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (16)
1. multilayered chip capacitor array comprises:
Capacitor body has a plurality of dielectric layers that are stacked;
A plurality of first and second internal electrodes are right, are formed on described a plurality of dielectric layer, make an electrode surface of an internal electrode centering to another electrode of described internal electrode centering, and are gripped with a dielectric layer in described a plurality of dielectric layer between it;
At least one first external terminal and a plurality of second external terminal are formed in the end face of described capacitor body and the bottom surface at least one surface; And
At least one first conductive via and a plurality of second conductive via are formed on the stacking direction of described capacitor body, and are connected to described first external terminal and described second external terminal respectively,
Wherein, described at least one first conductive via is connected to described first internal electrode, and with the described second internal electrode electric insulation,
Described a plurality of second conductive via is divided into k (k 〉=2) group, every group has at least one second conductive via, and described second internal electrode is divided into the k group, every group has at least one second internal electrode, and every group of second conductive via be connected to every group of second internal electrode and with other group and described first internal electrode electric insulations of second internal electrode.
2. multilayered chip capacitor array according to claim 1 wherein, is provided with described first and second conductive vias, and feasible magnetic field by the induction by current that flows into the described internal electrode that is connected with described first and second conductive vias is compensated.
3. multilayered chip capacitor array according to claim 2, wherein, every group of described second conductive via adjacent with the first predetermined conductive via is set to, uniformly-spaced to separate with the described first predetermined conductive via.
4. multilayered chip capacitor array according to claim 1, wherein, described first conductive via is set to a plurality of.
5. multilayered chip capacitor array according to claim 4, wherein, described first and second conductive vias are separately positioned on the foursquare angle.
6. multilayered chip capacitor array according to claim 5, wherein, described first conductive via is arranged in the described angle along on diagonal two angles respect to one another, and another group of described second conductive via is arranged on two other angle.
7. multilayered chip capacitor array according to claim 1, wherein, at least one group second conductive via has and is different from the quantity that other organize second conductive via.
8. multilayered chip capacitor array according to claim 1, wherein, every group of second internal electrode is connected to the second different conductive vias respectively.
9. multilayered chip capacitor array according to claim 1, wherein, every group of second internal electrode comprises that at least one is connected to the internal electrode of the second identical conductive via.
10. multilayered chip capacitor array according to claim 1, wherein, every group of second internal electrode has equal quantity.
11. multilayered chip capacitor array according to claim 1, wherein, at least one group second internal electrode has and is different from the quantity that other organize second internal electrode.
12. the wiring construction of a multilayered chip capacitor array comprises:
Base board has at least two power lines and an earth connection; And
The multilayered chip capacitor array bag is installed on the described base board, and has the wiring substrate, and described wiring substrate has microprocessor unit (MPU) chip and is installed in the following multilayered chip capacitor array of described wiring substrate,
Wherein, described multilayered chip capacitor array comprises:
Capacitor body has a plurality of dielectric layers that are stacked;
A plurality of first and second internal electrodes are right, are formed on described a plurality of dielectric layer, make an electrode surface of an internal electrode centering to another electrode of described internal electrode centering, and are gripped with a dielectric layer in described a plurality of dielectric layer between it;
At least one first external terminal and a plurality of second external terminal are formed on the end face of described capacitor body and at least one surface in the bottom surface; And
At least one first conductive via and a plurality of second conductive via are formed on the stacking direction of described capacitor body, and are connected to described first external terminal and described second external terminal respectively,
Wherein, described at least one first conductive via is connected to described first internal electrode, and with the described second internal electrode electric insulation,
Described a plurality of second conductive via is divided into k (k 〉=2) group, every group has at least one second conductive via, and described second internal electrode is divided into the k group, every group has at least one second internal electrode, and every group of second conductive via be connected to every group of second internal electrode and with other group and first internal electrode electric insulations of second internal electrode
Wherein, described earth connection is connected to described first external terminal, and described power line is connected to described second external terminal respectively, and each of described second external terminal is connected to described k and organizes every group of second conductive via, and
Wherein, in described first and second conductive vias of at least one in described power line and the described earth connection by described multi-layer chip capacitor corresponding one be connected to described MPU chip.
13. wiring construction according to claim 12, wherein, described first and second external terminals relevant with described first or second conductive via are formed on the end face and bottom surface of described capacitor body, wherein, described first or second conductive via is connected to described MPU chip with at least one in described power line and the earth connection.
14. wiring construction according to claim 12, wherein, the described power line of described wiring substrate is organized second conductive via by described k respectively and is connected to the MPU chip.
15. wiring construction according to claim 14, wherein, the described earth connection of described wiring substrate is connected to described MPU chip by described first conductive via.
16. wiring construction according to claim 12, described first and second external terminals of described multilayered chip capacitor array have layout and the interval roughly the same with described MPU chip.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020040089314 | 2004-11-04 | ||
| KR1020040089314A KR100674830B1 (en) | 2004-11-04 | 2004-11-04 | Multilayered chip capacitor array |
| KR1020040102609 | 2004-12-07 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1770343A true CN1770343A (en) | 2006-05-10 |
| CN100511511C CN100511511C (en) | 2009-07-08 |
Family
ID=36751531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101154101A Expired - Fee Related CN100511511C (en) | 2004-11-04 | 2005-11-03 | Multilayered chip capacitor array and wiring structure thereof |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR100674830B1 (en) |
| CN (1) | CN100511511C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104584158A (en) * | 2012-08-30 | 2015-04-29 | 艾里逊变速箱公司 | Method and system for reducing audible and/or electrical noise from electrically or mechanically excited capacitors |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2670212B1 (en) * | 2012-06-01 | 2016-03-09 | Electrolux Home Products Corporation N.V. | A half bridge induction heating generator and a capacitor assembly for a half bridge induction heating generator |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3337018B2 (en) * | 1999-11-19 | 2002-10-21 | 株式会社村田製作所 | Multilayer capacitors, wiring boards, decoupling circuits and high frequency circuits |
| JP3489729B2 (en) * | 1999-11-19 | 2004-01-26 | 株式会社村田製作所 | Multilayer capacitors, wiring boards, decoupling circuits, and high-frequency circuits |
-
2004
- 2004-11-04 KR KR1020040089314A patent/KR100674830B1/en not_active IP Right Cessation
-
2005
- 2005-11-03 CN CNB2005101154101A patent/CN100511511C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104584158A (en) * | 2012-08-30 | 2015-04-29 | 艾里逊变速箱公司 | Method and system for reducing audible and/or electrical noise from electrically or mechanically excited capacitors |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20060040101A (en) | 2006-05-10 |
| KR100674830B1 (en) | 2007-01-25 |
| CN100511511C (en) | 2009-07-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4437113B2 (en) | Multilayer capacitor array and wiring connection structure thereof | |
| CN1787136A (en) | Multilayered chip capacitor and multilayer chip capacitor array | |
| TWI342575B (en) | Multilayer capacitor | |
| US7312975B2 (en) | Laminated capacitor and manufacturing method thereof | |
| CN1779966A (en) | Semiconductor device | |
| CN1905099A (en) | Multilayer capacitor | |
| CN1397965A (en) | Ceramic electronic device with multi-terminal and multiple layers | |
| KR20090014445A (en) | Multilayer chip capacitor | |
| US20150022948A1 (en) | Capacitor structure | |
| CN1402274A (en) | Multilayer ceramic electronic device | |
| US8619407B2 (en) | Multilayered ceramic capacitor | |
| JP2010141350A (en) | Laminated chip capacitor | |
| KR20070092150A (en) | Multilayer capacitor and mounted structure thereof | |
| US7149071B2 (en) | Controlled resistance capacitors | |
| US9236189B2 (en) | Direct current capacitor module | |
| CN103000608A (en) | Chip packaging structure of a plurality of assemblies | |
| US20120050939A1 (en) | Multi-layered ceramic capacitor | |
| CN1941235A (en) | Feedthrough multilayer capacitor array | |
| CN1770343A (en) | Multilayered chip capacitor array | |
| JP2007115759A (en) | Multilayer capacitor, composite capacitor, capacitor module, and method of arranging capacitor | |
| KR20100104270A (en) | Multilayer chip capacitor and fabrication method of multilayer chip capacitor assembly | |
| CN1841732A (en) | Integrated circuit with multi joint type capacitor | |
| CN1498449A (en) | Offset pathway arrangements for energy conditioning | |
| KR20090066609A (en) | Laminated ceramic capacitor | |
| KR100674823B1 (en) | Wiring connection structure of multilayered chip capacitor array |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090708 Termination date: 20151103 |
|
| EXPY | Termination of patent right or utility model |