KR100655944B1 - 신뢰성을 개선하기 위하여 eeproms을 소거하는동안 감소된 일정한 전계를 제공하는 방법 - Google Patents
신뢰성을 개선하기 위하여 eeproms을 소거하는동안 감소된 일정한 전계를 제공하는 방법 Download PDFInfo
- Publication number
- KR100655944B1 KR100655944B1 KR1020027007781A KR20027007781A KR100655944B1 KR 100655944 B1 KR100655944 B1 KR 100655944B1 KR 1020027007781 A KR1020027007781 A KR 1020027007781A KR 20027007781 A KR20027007781 A KR 20027007781A KR 100655944 B1 KR100655944 B1 KR 100655944B1
- Authority
- KR
- South Korea
- Prior art keywords
- gate
- voltage
- source
- cell
- erase
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17232799P | 1999-12-17 | 1999-12-17 | |
US60/172,327 | 1999-12-17 | ||
US09/490,351 US6160740A (en) | 1999-12-17 | 2000-01-24 | Method to provide a reduced constant E-field during erase of EEPROMs for reliability improvement |
US09/490,351 | 2000-01-24 | ||
PCT/US2000/033044 WO2001045113A1 (en) | 1999-12-17 | 2000-12-05 | Method to provide a reduced constant e-field during erase of eeproms for reliability improvement |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20030011066A KR20030011066A (ko) | 2003-02-06 |
KR100655944B1 true KR100655944B1 (ko) | 2006-12-11 |
Family
ID=26867972
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020027007781A KR100655944B1 (ko) | 1999-12-17 | 2000-12-05 | 신뢰성을 개선하기 위하여 eeproms을 소거하는동안 감소된 일정한 전계를 제공하는 방법 |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1256117A1 (ja) |
JP (1) | JP4641697B2 (ja) |
KR (1) | KR100655944B1 (ja) |
CN (1) | CN1411602A (ja) |
WO (1) | WO2001045113A1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7450433B2 (en) | 2004-12-29 | 2008-11-11 | Sandisk Corporation | Word line compensation in non-volatile memory erase operations |
ATE457518T1 (de) * | 2005-03-31 | 2010-02-15 | Sandisk Corp | Löschen eines nichtflüchtigen speichers unter verwendung veränderlicher wortleitungsbedingungen zum ausgleichen langsamer schreibender speicherzellen |
KR100653718B1 (ko) * | 2005-08-09 | 2006-12-05 | 삼성전자주식회사 | 반도체소자의 소거 방법들 |
US8344475B2 (en) | 2006-11-29 | 2013-01-01 | Rambus Inc. | Integrated circuit heating to effect in-situ annealing |
US11244727B2 (en) | 2006-11-29 | 2022-02-08 | Rambus Inc. | Dynamic memory rank configuration |
WO2008067494A1 (en) * | 2006-11-29 | 2008-06-05 | Rambus Inc. | Integrated circuit with built-in heating circuitry to reverse operational degeneration |
KR101972167B1 (ko) * | 2012-05-29 | 2019-04-24 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그것의 동작 방법 |
CN103065684A (zh) * | 2012-12-27 | 2013-04-24 | 清华大学 | 一种存储单元的擦除方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0831963A (ja) * | 1994-07-19 | 1996-02-02 | Nippon Steel Corp | 不揮発性半導体記憶装置 |
US5485423A (en) * | 1994-10-11 | 1996-01-16 | Advanced Micro Devices, Inc. | Method for eliminating of cycling-induced electron trapping in the tunneling oxide of 5 volt only flash EEPROMS |
JPH10261292A (ja) * | 1997-03-18 | 1998-09-29 | Nec Corp | 不揮発性半導体記憶装置の消去方法 |
JP3915177B2 (ja) * | 1997-06-18 | 2007-05-16 | ソニー株式会社 | 不揮発性半導体記憶装置 |
US5838618A (en) * | 1997-09-11 | 1998-11-17 | Taiwan Semiconductor Manufacturing Company Ltd. | Bi-modal erase method for eliminating cycling-induced flash EEPROM cell write/erase threshold closure |
JP3324691B2 (ja) * | 1998-04-03 | 2002-09-17 | 日本電気株式会社 | 不揮発性半導体記憶装置および不揮発性半導体記憶装置のデータ書き換え方法 |
US5978277A (en) * | 1998-04-06 | 1999-11-02 | Aplus Flash Technology, Inc. | Bias condition and X-decoder circuit of flash memory array |
-
2000
- 2000-12-05 KR KR1020027007781A patent/KR100655944B1/ko not_active IP Right Cessation
- 2000-12-05 CN CN00817240A patent/CN1411602A/zh active Pending
- 2000-12-05 EP EP00983940A patent/EP1256117A1/en not_active Withdrawn
- 2000-12-05 WO PCT/US2000/033044 patent/WO2001045113A1/en not_active Application Discontinuation
- 2000-12-05 JP JP2001545318A patent/JP4641697B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR20030011066A (ko) | 2003-02-06 |
CN1411602A (zh) | 2003-04-16 |
EP1256117A1 (en) | 2002-11-13 |
JP4641697B2 (ja) | 2011-03-02 |
WO2001045113A1 (en) | 2001-06-21 |
JP2003517176A (ja) | 2003-05-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100761091B1 (ko) | 소프트 프로그래밍이 vt 분포의 폭을 좁힐 수 있게 하는 게이트 램핑 기술 | |
US6777292B2 (en) | Set of three level concurrent word line bias conditions for a NOR type flash memory array | |
US5416738A (en) | Single transistor flash EPROM cell and method of operation | |
JP3653186B2 (ja) | 不揮発性メモリ装置のプログラミング方法 | |
KR100621634B1 (ko) | 플래시 메모리 장치 및 그것의 프로그램 방법 | |
US6757196B1 (en) | Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device | |
US6847556B2 (en) | Method for operating NOR type flash memory device including SONOS cells | |
US6240016B1 (en) | Method to reduce read gate disturb for flash EEPROM application | |
KR100578582B1 (ko) | 플래시 메모리에 응용하기 위한 램프 또는 스텝 게이트 채널 소거 | |
US5521867A (en) | Adjustable threshold voltage conversion circuit | |
JP5059437B2 (ja) | 不揮発性半導体記憶装置 | |
US6469939B1 (en) | Flash memory device with increase of efficiency during an APDE (automatic program disturb after erase) process | |
US6646914B1 (en) | Flash memory array architecture having staggered metal lines | |
KR100558004B1 (ko) | 게이트 전극과 반도체 기판 사이에 전하저장층을 갖는비휘발성 메모리 소자의 프로그램 방법 | |
KR100639827B1 (ko) | Eeprom 응용을 위한 1 트랜지스터 셀 | |
US6285588B1 (en) | Erase scheme to tighten the threshold voltage distribution of EEPROM flash memory cells | |
KR100655944B1 (ko) | 신뢰성을 개선하기 위하여 eeproms을 소거하는동안 감소된 일정한 전계를 제공하는 방법 | |
US6510085B1 (en) | Method of channel hot electron programming for short channel NOR flash arrays | |
US6233175B1 (en) | Self-limiting multi-level programming states | |
US6160740A (en) | Method to provide a reduced constant E-field during erase of EEPROMs for reliability improvement | |
US6654283B1 (en) | Flash memory array architecture and method of programming, erasing and reading thereof | |
JPH08227589A (ja) | 不揮発性メモリ | |
US6768683B1 (en) | Low column leakage flash memory array | |
US6147907A (en) | Biasing scheme to reduce stress on non-selected cells during read | |
KR20060070724A (ko) | 플래쉬 메모리 소자의 프로그램 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20121129 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20131122 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20141121 Year of fee payment: 9 |
|
LAPS | Lapse due to unpaid annual fee |