KR100653980B1 - Method for forming poly-silicon plug - Google Patents

Method for forming poly-silicon plug Download PDF

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KR100653980B1
KR100653980B1 KR1020000043946A KR20000043946A KR100653980B1 KR 100653980 B1 KR100653980 B1 KR 100653980B1 KR 1020000043946 A KR1020000043946 A KR 1020000043946A KR 20000043946 A KR20000043946 A KR 20000043946A KR 100653980 B1 KR100653980 B1 KR 100653980B1
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forming
film
polysilicon
plug
interlayer insulating
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KR20020010297A (en
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김선우
김찬배
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

1차의 화학기계적 연마공정으로 폴리실리콘 플러그를 형성할 수 있도록 한 폴리실리콘 플러그 형성방법이 개시되어 있다. 이는, 반도체기판 상에 게이트산화막, 게이트전극 및 하드마스크막을 포함하는 게이트스택을 형성하는 단계와, 게이트스택이 형성된 반도체기판 상에, BPSG(Boron Phosphorus Silicate Glass)로 이루어진 층간절연막을 형성하는 단계와, 층간절연막을 식각하여 플러그(plug)를 형성하기 위한 콘택홀을 형성하는 단계와, 결과물 상에 폴리실리콘막을 형성하는 단계와, 폴리실리콘막을 소정 두께 에치백하는 단계, 및 폴리실리콘막에 대해 화학기계적 연마공정을 실시하여 폴리실리콘 플러그를 형성하는 단계를 포함하여 이루어진다.Disclosed is a method for forming a polysilicon plug capable of forming a polysilicon plug by a first chemical mechanical polishing process. The method may include forming a gate stack including a gate oxide film, a gate electrode, and a hard mask layer on a semiconductor substrate, and forming an interlayer insulating layer of BPSG (Boron Phosphorus Silicate Glass) on the semiconductor substrate on which the gate stack is formed. Forming a contact hole for forming a plug by etching the interlayer insulating film, forming a polysilicon film on the resultant, etching back the polysilicon film to a predetermined thickness, and chemically treating the polysilicon film. Performing a mechanical polishing process to form a polysilicon plug.

화학기계적 연마, 1회, 폴리실리콘, 플러그Chemical Mechanical Polishing, Once, Polysilicon, Plug

Description

폴리실리콘 플러그 형성방법{Method for forming poly-silicon plug} Method for forming poly-silicon plug             

도 1 내지 도 6은 종래 기술에 따른 폴리실리콘 플러그의 형성방법을 설명하기 위해 도시된 단면도들이다. 1 to 6 are cross-sectional views illustrating a method of forming a polysilicon plug according to the prior art.

도 7 내지 도 14은 본 발명에 따른 폴리실리콘 플러그의 형성방법을 설명하기 위해 도시된 단면도들이다. 7 to 14 are cross-sectional views illustrating a method of forming a polysilicon plug according to the present invention.

＊도면의 주요부분에 대한 부호의 설명＊＊ Description of symbols for main parts of the drawings ＊

100 ; 반도체기판 120 ; 하드마스크막100; Semiconductor substrate 120; Hard mask

140 ; 층간절연막 160 ; 전도성물질막140; Interlayer insulating film 160; Conductive material film

A-A', B-B', C-C'; 연마정지선
A-A ', B-B', C-C '; Polishing stop line

본 발명은 폴리실리콘 플러그의 형성방법에 관한 것으로서, 보다 자세하게는 1차의 화학기계적 연마공정으로 폴리실리콘 플러그를 형성할 수 있도록 한 폴리실리콘 플러그 형성방법에 관한 것이다. The present invention relates to a method for forming a polysilicon plug, and more particularly, to a method for forming a polysilicon plug capable of forming a polysilicon plug by a primary chemical mechanical polishing process.                         

도 1 내지 도 6은 종래 기술에 따른 폴리실리콘 플러그의 형성방법을 설명하기 위해 도시된 단면도들이다. 1 to 6 are cross-sectional views illustrating a method of forming a polysilicon plug according to the prior art.

우선, 도 1에 도시된 바와 같이 반도체기판(1) 상부에 게이트산화막 및 게이트전극물질층(2)을 형성한 후, 그 상부에 하드마스크막(3)을 형성하고, 스페이서공정을 실시하여 스페이서(4)를 형성한다.First, as shown in FIG. 1, the gate oxide film and the gate electrode material layer 2 are formed on the semiconductor substrate 1, and then the hard mask film 3 is formed on the semiconductor substrate 1. (4) is formed.

이후, 도 2에 도시된 바와 같이 상기 결과물에 BPSG(Boron Phosphorus Silicate Glass)를 이용하여 층간절연막(5)을 형성한 후, 화학기계적 연마공정으로 1차 평탄화공정을 실시한다. 이때, 1차 연마정지선은 화살표가 가리키는 A-A'선이다. Thereafter, as shown in FIG. 2, the interlayer insulating film 5 is formed on the resultant using BPSG (Boron Phosphorus Silicate Glass), and then a first planarization process is performed by a chemical mechanical polishing process. At this time, the primary polishing stop line is the line A-A 'indicated by the arrow.

이후, 도 3에 도시된 바와 같이 상기 결과물의 상부에 감광막(7)을 도포한 후, 상기 감광막(7)에 노광 및 현상공정을 실시하여 콘택영역을 형성하기 위한 감광막(7)패턴을 형성하고, 상기 감광막(7)패턴을 식각마스크로 상기 층간절연막(5)을 식각하여 콘택영역(8)을 형성한다.Thereafter, as shown in FIG. 3, after the photoresist film 7 is coated on the resultant product, the photoresist film 7 is exposed and developed to form a photoresist film 7 pattern for forming a contact region. In addition, the interlayer insulating layer 5 is etched using the photoresist 7 pattern as an etch mask to form a contact region 8.

이후, 도 4에 도시된 바와 같이 상기 결과물에 인을 함유하고 있는 폴리실리콘막을 이용하여 전도성물질막(9)을 증착한다. Thereafter, as shown in FIG. 4, the conductive material film 9 is deposited using a polysilicon film containing phosphorus in the resultant product.

이후, 도 5 및 도 6에 도시된 바와 같이 상기 결과물에 화학기계적 연마공정을 이용한 2차 평탄화공정을 실시하는데, 이때 2차 식각정지선은 화살표가 가리키는 B-B'선인데, 이는 플러그 콘택영역(8)간 즉 도 6에 "a"와 "b"로 표시된 부분을 분리하기 위함으로, 상기 하드마스크막(3)을 소정 두께 식각해낸다.Thereafter, as shown in FIGS. 5 and 6, the second planarization process using the chemical mechanical polishing process is performed on the resultant, wherein the secondary etch stop line is a B-B 'line indicated by an arrow, which is a plug contact region ( The hard mask film 3 is etched by a predetermined thickness in order to separate the portions indicated by " a " and " b "

삭제delete

하지만, 상기와 같은 방법으로 폴리실리콘 플러그 형성 시, 화학기계적 연마공정을 2차례 실시하게 되어 소자제작 원가에 많은 부담요인이 되었다.
However, when forming the polysilicon plug in the same manner as described above, the chemical mechanical polishing process is performed twice, which is a large burden on the device manufacturing cost.

상기와 같은 문제점을 해결하기 위하여 창안된 본 발명의 목적은 1차의 화학기계적 연마공정으로 폴리실리콘 플러그를 형성할 수 있도록 한 폴리실리콘 플러그 형성방법을 제공하는데 있다.
SUMMARY OF THE INVENTION An object of the present invention, which was devised to solve the above problems, is to provide a polysilicon plug forming method capable of forming a polysilicon plug by a primary chemical mechanical polishing process.

상기와 같은 목적을 달성하기 위한 본 발명은, 반도체기판 상에 게이트산화막, 게이트전극 및 하드마스크막을 포함하는 게이트스택을 형성하는 단계와, 게이트스택이 형성된 반도체기판 상에, BPSG(Boron Phosphorus Silicate Glass)로 이루어진 층간절연막을 형성하는 단계와, 층간절연막을 식각하여 플러그(plug)를 형성하기 위한 콘택홀을 형성하는 단계와, 결과물 상에 폴리실리콘막을 형성하는 단계와, 폴리실리콘막을 소정 두께 에치백하는 단계, 및 폴리실리콘막에 대해 화학기계적 연마공정을 실시하여 폴리실리콘 플러그를 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention for achieving the above object, the step of forming a gate stack comprising a gate oxide film, a gate electrode and a hard mask film on the semiconductor substrate, on the semiconductor substrate on which the gate stack is formed, BPSG (Boron Phosphorus Silicate Glass) Forming an interlayer insulating film, forming a contact hole for etching the interlayer insulating film, forming a polysilicon film on the resultant, and etching back the polysilicon film to a predetermined thickness. And performing a chemical mechanical polishing process on the polysilicon film to form a polysilicon plug.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다. 또한, 본 실시예는 발명의 권리범위를 제한하는 것이 아니고, 단지 예시로 제시된 것이다. Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, this embodiment does not limit the scope of the invention, but is presented by way of example only.

도 7 내지 도 13은 본 발명에 따른 폴리실리콘 플러그 형성방법을 설명하기 위해 도시된 단면도들이다. 7 to 13 are cross-sectional views illustrating a method for forming a polysilicon plug according to the present invention.

우선, 도 7에 도시된 바와 같이 반도체기판(100) 상부에 게이트산화막(110)을 형성하고, 그 상부에 폴리실리콘막(122) 및 하드마스크막(124)으로 이루어진 게이트스택(G)을 형성하고, 스페이서공정을 실시하여 상기 게이트스택의 측벽에 스페이서(130)를 형성한다.First, as shown in FIG. 7, the gate oxide film 110 is formed on the semiconductor substrate 100, and the gate stack G formed of the polysilicon film 122 and the hard mask film 124 is formed thereon. In addition, a spacer process is performed to form spacers 130 on sidewalls of the gate stack.

이때, 상기 폴리실리콘막(122) 및 하드마스크막(124)으로 이루어진 게이트스택(G)의 두께는 3500∼4200Å이다. In this case, the thickness of the gate stack G including the polysilicon film 122 and the hard mask film 124 is 3500 to 4200 kPa.

이후, 도 8에 도시된 바와 같이 상기 결과물에 BPSG(Boron Phosphorus Silicate Glass)막으로 된 층간절연막(140)을 형성한다. Subsequently, as shown in FIG. 8, an interlayer insulating layer 140 made of a boron phosphorous silica (BPSG) film is formed on the resultant.

이때, 상기 층간절연막(140)은 상기 게이트전극(G)두께의 120~200% 즉, 3000∼6000Å의 두께로 형성한다.In this case, the interlayer insulating layer 140 is formed to have a thickness of 120 to 200% of the thickness of the gate electrode G, that is, 3000 to 6000 μs.

그리고, 상기 BPSG막 내의 붕소와 인의 농도는 각각 3~5weight% 영역이다. 이때, 게이트간 거리가 0.4㎛ 이하인 경우에는 그 상부에 BPSG막을 증착하면 메모리셀 영역에서는 완전평탄화가 확보되므로 평탄화를 위해 화학기계적 연마공정을 실시하지 않아도 되지만, 주변영역에서는 도 8의 a"로 도시된 바와 같이 단차가 발생하게 된다. The concentrations of boron and phosphorus in the BPSG film are 3 to 5 weight%, respectively. In this case, when the distance between the gates is 0.4 μm or less, when the BPSG film is deposited on the upper portion, the planarization is secured in the memory cell region. Therefore, the chemical mechanical polishing process is not required for the planarization. As shown, a step occurs.

삭제delete

하지만, 주변영역의 하부셀은 동작하지 않는 더미(dummy)셀이어서 소자의 동작에는 영향을 미치지 않으므로 화학기계적 연마공정을 실시하지 않아도 된다. However, since the lower cell of the peripheral area is a dummy cell that does not operate, it does not affect the operation of the device, and thus, the chemical mechanical polishing process does not need to be performed.

상기와 같이 층간절연막을 형성한 후 화학기계적 연마공정을 실시하지 않고, 후속공정을 진행하게 되면 SAC(Self Align Contact)공정의 안정도를 높일 수 있으며, 종래에는 반도체기판 내의 불균일도가 10%정도였으나 5%정도의 값을 확보할 수 있게 된다. As described above, if the interlayer insulating film is formed and then the chemical mechanical polishing process is not performed and the subsequent process is performed, the stability of the SAC (Self Align Contact) process can be increased. In the past, the nonuniformity in the semiconductor substrate was about 10%. A value of about 5% can be obtained.

이후, 도 9에 도시된 바와 같이 상기 층간절연막(140')의 상부에 감광막(미도시)을 형성한 후, 상기 감광막에 노광 및 현상공정을 실시하여 콘택영역을 형성하기 위한 감광막패턴(미도시)을 형성하고, 상기 감광막패턴을 식각마스크로 상기 층간절연막(140')을 식각하여 콘택영역(150)을 형성한다.Subsequently, as shown in FIG. 9, after forming a photoresist film (not shown) on the interlayer insulating film 140 ′, a photoresist pattern (not shown) is formed to perform contact and development processes on the photoresist to form a contact region. ) And the interlayer insulating layer 140 'is etched using the photoresist pattern as an etch mask to form a contact region 150.

그리고, 도 10에 도시된 바와 같이 상기 감광막패턴을 제거한 후, 결과물 전면부에 전도성물질막(160)을 형성한다. After removing the photoresist pattern as illustrated in FIG. 10, the conductive material layer 160 is formed on the front surface of the resultant.

상기 전도성물질막(160)은 인을 함유하고 있는 N형 폴리실리콘막을 이용하여 형성하는데, 상기 N형 폴리실리콘막 내의 인의 농도는 1 ×1019/㎤ 이상이 되도록 한다.The conductive material film 160 is formed using an N-type polysilicon film containing phosphorus, so that the concentration of phosphorus in the N-type polysilicon film is 1 × 10 19 / cm 3 or more.

이때, 상기 전도성물질막(160)은 도 10에 도시된 바와 같이 2100~3100Å의 두께로 형성되거나, 도 13에 도시된 바와 같이 콘택영역을 채울 수 있을 만큼의 최소한의 두께 즉, 게이트간 거리의 50~120%인 1000~1500Å의 두께로 형성될 수 있다. In this case, the conductive material layer 160 is formed to a thickness of 2100 ~ 3100Å as shown in Figure 10, or as shown in Figure 13 of the minimum thickness that is enough to fill the contact area, that is, the distance between the gates 50 to 120% of the thickness can be formed of 1000 ~ 1500.

그래서, 2100~3100Å의 두께로 형성된 전도성물질막(160)에는 도 11에 도시 된 바와 같이 에치백공정을 실시한다. Thus, the conductive material film 160 formed to a thickness of 2100 ~ 3100Å is subjected to the etch back process as shown in FIG.

이때, 에치백공정을 실시할 때 전도성물질막(160)이 형성된 두께의 110~120%가 식각되면서 하부의 층간절연막(140')의 소정 두께가 식각되는데, 이는 콘택영역의 좁은 기하학적 형상으로 인해 좌우측벽에 증착된 전도성물질막(160)에 의해 서로 밀착되어 함몰되기 때문이다. At this time, when the etch back process is performed, 110 to 120% of the thickness of the conductive material layer 160 is etched, and a predetermined thickness of the lower interlayer insulating layer 140 'is etched due to the narrow geometric shape of the contact region. This is because the conductive material film 160 deposited on the left and right side walls is in close contact with each other and is recessed.

그리고, 콘택영역을 채울 수 있을 만큼의 최소한의 두께로 전도성물질막(160)이 형성된 경우에는 에치백공정을 실시하지 않고 후속공정을 진행하게 된다.In addition, when the conductive material layer 160 is formed to a minimum thickness enough to fill the contact region, the subsequent process is performed without performing an etch back process.

이후, 도 12에 도시된 바와 같이 상기 결과물에 화학기계적 연마공정을 이용한 평탄화공정을 실시하는데, 상기에서 에치백공정을 실시한 경우는 실시하지 않은 경우보다 연마시간이 1/2로 단축된다.Thereafter, as shown in FIG. 12, the resultant is subjected to a planarization process using a chemical mechanical polishing process. In the case where the etchback process is performed, the polishing time is reduced to 1/2 compared with that of the case where the etchback process is not performed.

이때 식각정지선은 도 11에서 화살표가 가리키는 C-C'선이 되는데, 이는 플러그 콘택 즉 도 12의 "c"와 "d"로 표시된 영역간 분리를 하기 위함으로, 상기 게이트전극물질층의 상부에 형성된 하드마스크막(124)을 소정 두께 식각해내게 된다.In this case, the etch stop line is a C-C 'line indicated by an arrow in FIG. 11, which is formed on the gate electrode material layer to separate the plug contact, that is, the region indicated by “c” and “d” in FIG. 12. The hard mask layer 124 is etched by a predetermined thickness.

이때, 하드마스크막(124), 전도성물질막(160) 및 층간절연막(140') 간의 식각비는 1:1.2~0.7:0.5 정도가 되도록 하는 것이 바람직하다.In this case, the etching ratio between the hard mask layer 124, the conductive material layer 160, and the interlayer insulating layer 140 ′ may be about 1: 1.2 to 0.7: 0.5.

삭제delete

상술한 본 발명에 의한 폴리실리콘 플러그 형성방법에 따르면, 1회의 화학기계적 연마공정으로 폴리실리콘 플러그를 형성할 수 있고, SAC공정 시 안정성을 확보할 수 있는 효과를 가진다.According to the method for forming a polysilicon plug according to the present invention described above, the polysilicon plug can be formed by one chemical mechanical polishing process, and has an effect of ensuring stability in the SAC process.

또한, 반도체소자 제작 시, 생산성을 향상시킬 수 있고, 소자의 신뢰성을 증가시킬 수 있다.In addition, when manufacturing a semiconductor device, it is possible to improve productivity and increase the reliability of the device.

Claims (10)

반도체기판 상에 게이트산화막, 게이트전극 및 하드마스크막을 포함하는 게이트스택을 형성하는 단계;Forming a gate stack including a gate oxide film, a gate electrode, and a hard mask film on a semiconductor substrate; 상기 게이트스택이 형성된 반도체기판 상에, BPSG(Boron Phosphorus Silicate Glass)로 이루어진 층간절연막을 형성하는 단계;Forming an interlayer insulating film made of boron phosphorus silicate glass (BPSG) on the semiconductor substrate on which the gate stack is formed; 상기 층간절연막을 식각하여 플러그(plug)를 형성하기 위한 콘택홀을 형성하는 단계;Etching the interlayer insulating layer to form a contact hole for forming a plug; 결과물 상에 폴리실리콘막을 형성하는 단계;Forming a polysilicon film on the resultant; 상기 폴리실리콘막을 소정 두께 에치백하는 단계; 및Etching back the polysilicon film to a predetermined thickness; And 상기 폴리실리콘막에 대해 화학기계적 연마(CMP) 공정을 실시하여 폴리실리콘 플러그를 형성하는 단계를 포함하는 것을 특징으로 하는 폴리실리콘 플러그 형성방법.And performing a chemical mechanical polishing (CMP) process on the polysilicon film to form a polysilicon plug. 제 1항에 있어서, The method of claim 1, 상기 층간절연막은 상기 게이트전극 두께의 120∼200%의 두께로 형성하는 것을 특징으로 하는 폴리실리콘 플러그 형성방법.And the interlayer insulating film is formed to a thickness of 120 to 200% of the thickness of the gate electrode. 제 1항에 있어서, The method of claim 1, 상기 BPSG막 내의 붕소와 인의 농도는 각각 3~5 weight% 의 영역인 것을 특징으로 하는 폴리실리콘 플러그 형성방법.The method of forming a polysilicon plug, characterized in that the concentration of boron and phosphorus in the BPSG film is a region of 3 to 5% by weight, respectively. 삭제delete 제 1항에 있어서, The method of claim 1, 상기 폴리실리콘막은 인이 1 ×1019/㎤ 의 농도로 도핑된 것을 특징으로 하는 폴리실리콘 플러그 형성방법.Wherein said polysilicon film is doped with phosphorus at a concentration of 1 × 10 19 / cm 3. 제 1항에 있어서, The method of claim 1, 상기 폴리실리콘막은 증착하거나 상기 반도체기판을 모재로 하여 성장시킨 것임을 특징으로 하는 폴리실리콘 플러그 형성방법.Wherein the polysilicon film is deposited or grown using the semiconductor substrate as a base material. 삭제delete 삭제delete 삭제delete 제 1항에 있어서,The method of claim 1, 상기 화학기계적연마공정을 실시할 때, 하드마스크막, 폴리실리콘막 및 층간절연막 간의 식각비는 1:1.2~0.7:0.5인 것을 특징으로 하는 폴리실리콘 플러그 형성방법.When the chemical mechanical polishing process is performed, the etching ratio between the hard mask film, the polysilicon film, and the interlayer insulating film is 1: 1.2 to 0.7: 0.5.
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KR19980044102A (en) * 1996-12-05 1998-09-05 김광호 Method for forming contact plug of semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980044102A (en) * 1996-12-05 1998-09-05 김광호 Method for forming contact plug of semiconductor device

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