KR100645177B1 - Method for fabricating flash memory device - Google Patents

Method for fabricating flash memory device Download PDF

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KR100645177B1
KR100645177B1 KR1020040112828A KR20040112828A KR100645177B1 KR 100645177 B1 KR100645177 B1 KR 100645177B1 KR 1020040112828 A KR1020040112828 A KR 1020040112828A KR 20040112828 A KR20040112828 A KR 20040112828A KR 100645177 B1 KR100645177 B1 KR 100645177B1
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trench
oxide film
film
semiconductor substrate
forming
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KR20060074178A (en
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박성조
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32105—Oxidation of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3211—Nitridation of silicon-containing layers

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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

본 발명은 플래쉬 메모리 소자의 제조방법에 관한 것으로, 반도체 기판과 라이너 질화막 사이에 형성하는 산화막을 트렌치 버텀부에서는 두껍게 형성하고 트렌치 탑부에서는 얇게 형성함으로써, 대기 전류(stand by current)와 누설(leakage)을 동시에 줄일 수 있다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, wherein an oxide film formed between a semiconductor substrate and a liner nitride film is formed thick in the trench bottom portion and thinly formed in the trench top portion, thereby providing stand-by current and leakage. Can be reduced at the same time.

STI, 대기 전류, 누설, 버퍼 산화막, 라이너 질화막STI, Standby Current, Leakage, Buffer Oxide, Liner Nitride

Description

플래쉬 메모리 소자의 제조방법{Method for fabricating flash memory device} Manufacturing method of flash memory device {Method for fabricating flash memory device}             

도 1a 내지 도 1h는 본 발명의 실시예에 따른 플래쉬 메모리 소자의 제조공정 단면도1A to 1H are cross-sectional views illustrating a manufacturing process of a flash memory device according to an exemplary embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10 : 반도체 기판 11 : 패드 산화막10 semiconductor substrate 11 pad oxide film

12 : 패드 질화막 13 : 트렌치12: pad nitride film 13: trench

14 : 제 1 산화막 15 : 버퍼 산화막14: first oxide film 15: buffer oxide film

16 : 라이너 질화막 17 : 제 2 산화막
16 liner nitride film 17 second oxide film

본 발명은 플래쉬 메모리 소자의 제조방법에 관한 것으로, 특히 대기 전류(stand by current)와 누설(leakage)을 줄이기 위한 플래쉬 메모리 소자의 제조방법에 관한 것이다. The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device for reducing stand by current and leakage.                         

플래쉬 메모리 소자에서 STI 구조의 소자분리막과 반도체 기판 사이에 버퍼 산화막(buffer oxide)을 형성하고, 상기 버퍼 산화막에 의한 누설(leakage) 감소를 위하여 상기 버퍼 산화막과 소자분리막 사이에 라이너 질화막(liner nitride)을 형성하고 있다. In the flash memory device, a buffer oxide is formed between an isolation layer and a semiconductor substrate of an STI structure, and a liner nitride is formed between the buffer oxide and the isolation layer in order to reduce leakage caused by the buffer oxide layer. To form.

그러나, 상기 라이너 질화막으로 인하여 페리 영역의 트랜지스터(Peri Transistor)의 대기 전류(stand by current)가 증가하는 문제가 발생된다.However, the liner nitride film causes a problem in that the stand-by current of the transistor in the ferry region increases.

이러한 대기 전류를 줄이기 위하여 버퍼 산화막의 두께를 증가시키면 반대로 누설이 증가되는 문제가 발생된다.
Increasing the thickness of the buffer oxide film in order to reduce the standby current, on the contrary, causes a problem of increased leakage.

따라서, 본 발명은 전술한 종래 기술의 문제점을 해결하기 위하여 안출한 것으로써, 대기 전류 및 누설(leakage)을 동시에 줄일 수 있는 플래쉬 메모리 소자의 제조방법을 제공하는데 그 목적이 있다.
Accordingly, an object of the present invention is to provide a method of manufacturing a flash memory device capable of simultaneously reducing standby current and leakage, which has been devised to solve the aforementioned problems of the prior art.

본 발명에 따른 플래쉬 메모리 소자의 제조방법은 (a)반도체 기판에 트렌치를 형성하는 단계와, (b)상기 트렌치 하부에 제 1 산화막을 형성하는 단계와, (c)상기 트렌치를 포함한 반도체 기판 표면상에 버퍼 산화막과 라이너 질화막을 차례로 형성하는 단계와, (d)상기 트렌치를 포함한 전면에 제 2 산화막을 형성하여 상기 트렌치를 완전히 매립하는 단계와, (e) 상기 트렌치를 제외한 영역에 형성된 제 2 산화막과, 라이너 질화막과 버퍼 산화막을 제거하여 상기 트렌치 내에 소자분리막을 형성하는 단계를 포함하여 형성한다.A method of manufacturing a flash memory device according to the present invention includes the steps of (a) forming a trench in a semiconductor substrate, (b) forming a first oxide film under the trench, and (c) a surface of the semiconductor substrate including the trench. Sequentially forming a buffer oxide film and a liner nitride film on the substrate; (d) forming a second oxide film on the entire surface including the trench to completely fill the trench; and (e) a second formed in the region excluding the trench. And removing the oxide film, the liner nitride film, and the buffer oxide film to form an isolation layer in the trench.

바람직하게, 상기 (a) 단계는 상기 반도체 기판상에 패드 산화막과 패드 질화막을 형성하는 단계와, 상기 패드 질화막과 패드 산화막을 선택적으로 제거하는 단계와, 상기 선택적으로 제거된 패드 질화막과 패드 산화막을 마스크로 반도체 기판을 식각하여 트렌치를 형성하는 단계를 포함하는 것을 특징으로 한다.Preferably, the step (a) includes forming a pad oxide film and a pad nitride film on the semiconductor substrate, selectively removing the pad nitride film and the pad oxide film, and removing the selectively removed pad nitride film and the pad oxide film. And etching the semiconductor substrate with a mask to form a trench.

바람직하게, 상기 (b) 단계는 상기 트렌치를 포함한 반도체 기판상에 제 1 산화막을 형성하여 상기 트렌치를 완전히 매립하는 단계와, 상기 CMP 공정으로 제 1 산화막을 식각하여 제 1 산화막을 트렌치 내부에만 남기는 단계와, 상기 제 1 산화막을 습식 식각하여 트렌치 하부에만 제 1 산화막을 남기는 단계를 포함하는 것을 특징으로 한다.Preferably, the step (b) includes forming a first oxide film on the semiconductor substrate including the trench to completely fill the trench, and etching the first oxide film by the CMP process to leave the first oxide film only inside the trench. And wet etching the first oxide layer to leave the first oxide layer only below the trench.

바람직하게, 상기 라이너 질화막을 형성한 다음에 어닐링 하는 단계를 더 포함하는 것을 특징으로 한다.Preferably, the method further comprises the step of annealing after forming the liner nitride film.

바람직하게, 상기 제 1, 제 2 산화막은 HDP 산화막인 것을 특징으로 한다.Preferably, the first and second oxide films are HDP oxide films.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명의 범위는 본원의 특허 청구 범위에 의해서 이해되어야 한다. Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.                     

도 1a 내지 도 1h는 본 발명의 실시예에 따른 플래쉬 메모리 소자의 제조공정 단면도이다.1A to 1H are cross-sectional views illustrating a manufacturing process of a flash memory device according to an exemplary embodiment of the present invention.

먼저, 도 1a에 도시하는 바와 같이 반도체 기판(10)상에 패드 산화막(11)과 패드 질화막(12)을 차례로 형성한다.First, as shown in FIG. 1A, a pad oxide film 11 and a pad nitride film 12 are sequentially formed on the semiconductor substrate 10.

어어, 도 1b에 도시하는 바와 같이, 포토 및 식각 공정으로 패드 질화막(12)과 패드 산화막(11)을 선택적으로 제거하고, 상기 선택적으로 제거된 패드 질화막(12)과 패드 산화막(11)을 마스크로 반도체 기판(10)을 식각하여 STI(Shallow Trench Isolation)용 트렌치(13)를 형성한다.For example, as illustrated in FIG. 1B, the pad nitride film 12 and the pad oxide film 11 are selectively removed by a photo and etching process, and the selectively removed pad nitride film 12 and the pad oxide film 11 are masked. The semiconductor substrate 10 is etched to form trenches 13 for shallow trench isolation (STI).

그런 다음, 도 1c에 도시하는 바와 같이 상기 트렌치(13)를 포함한 전면에 제 1 산화막(14)을 증착하여 상기 트렌치(13)를 매립한다.Then, as shown in FIG. 1C, the first oxide film 14 is deposited on the entire surface including the trench 13 to fill the trench 13.

이때, 상기 제 1 산화막(14)은 HDP(High Density Plasma) 산화막을 이용하여 형성한다.In this case, the first oxide film 14 is formed using an HDP (High Density Plasma) oxide film.

이어서, 도 1d에 도시하는 바와 같이 상기 패드 질화막(12)이 노출되도록 상기 제 1 산화막(14)을 CMP(Chemical Mechanical Polishing)하여 상기 제 1 산화막(14)이 트렌치(13) 내부에만 남게 되도록 한다.Subsequently, as shown in FIG. 1D, the first oxide film 14 is chemically mechanical polished (CMP) so that the pad nitride film 12 is exposed so that the first oxide film 14 remains only inside the trench 13. .

그러고 나서, 도 1e에 도시하는 바와 같이 산화막에 대한 선택적인 습식 식각(selective wet etch) 공정으로 트렌치(13) 내에 형성된 제 1 산화막(14)을 상부에서부터 일정두께 제거하여 상기 제 1 산화막(14)을 상기 트렌치(13) 하부에 잔류시킨다. Thereafter, as shown in FIG. 1E, the first oxide film 14 formed in the trench 13 is removed by a predetermined thickness from the top by a selective wet etch process on the oxide film. Is left at the bottom of the trench 13.

따라서, 상기 트렌치(13)의 상부가 드러나게 된다. Thus, the upper portion of the trench 13 is exposed.                     

이때, 차후에 형성하는 라이너 질화막의 저부가 소오스/드레인 접합보다 낮게 될 수 있도록 상기 제 1 산화막(14)이 제거되는 두께를 제어한다.At this time, the thickness of the first oxide film 14 is removed so that the bottom of the liner nitride film formed later may be lower than the source / drain junction.

그런 다음에, 도 1f에 도시하는 바와 같이 상기 드러난 트렌치(13)를 포함한 전 표면상에 버퍼 산화막(15)과 라이너 질화막(16)을 차례로 형성하고, 어닐링(annealing) 공정을 실시한다.Then, as shown in FIG. 1F, a buffer oxide film 15 and a liner nitride film 16 are sequentially formed on the entire surface including the exposed trench 13, and an annealing process is performed.

이어서, 상기 트렌치(13)를 포함한 반도체 기판(10)상에 제 2 산화막(17)을 형성하여 상기 트렌치(13)를 매립한다.Subsequently, a second oxide film 17 is formed on the semiconductor substrate 10 including the trench 13 to fill the trench 13.

여기서, 상기 제 2 산화막(17)은 HDP 산화막으로 형성한다.Here, the second oxide film 17 is formed of an HDP oxide film.

이어, 상기 패드 질화막(12)이 노출되도록 상기 제 2 산화막(17)과 라이너 질화막(16)과 버퍼 산화막(15)을 CMP한다.Next, the second oxide film 17, the liner nitride film 16, and the buffer oxide film 15 are CMP so that the pad nitride film 12 is exposed.

그런 다음, 도 1h에 도시하는 바와 같이 HF와 H3PO4를 사용한 습식식각 공정으로 상기 패드 질화막(12)과 패드 산화막(11)을 제거한다. Then, as shown in FIG. 1H, the pad nitride film 12 and the pad oxide film 11 are removed by a wet etching process using HF and H 3 PO 4 .

이로써, 제 1 산화막(14), 버퍼 산화막(15), 라이너 질화막(16), 제 2 산화막(17)으로 구성되는 본 발명에 따른 STI 구조의 소자분리막을 완성한다.
As a result, the device isolation film of the STI structure according to the present invention comprising the first oxide film 14, the buffer oxide film 15, the liner nitride film 16, and the second oxide film 17 is completed.

상술한 바와 같이, 본 발명은 다음과 같은 효과가 있다.As described above, the present invention has the following effects.

반도체 기판과 라이너 질화막 사이에 형성하는 산화막을 트렌치 버텀부에서는 두껍게 형성하고, 트렌치 탑부에서는 얇게 형성할 수 있으므로 대기 전류(stand by current)와 누설(leakage) 동시에 줄일 수 있다. Since the oxide film formed between the semiconductor substrate and the liner nitride film can be formed thick in the trench bottom portion and thin in the trench top portion, it is possible to simultaneously reduce stand-by current and leakage.

Claims (5)

(a) 반도체 기판에 트렌치를 형성하는 단계;(a) forming a trench in the semiconductor substrate; (b) 상기 트렌치 하부에 제 1 산화막을 형성하는 단계;(b) forming a first oxide film under the trench; (c) 상기 트렌치를 포함한 반도체 기판 표면상에 버퍼 산화막과 라이너 질화막을 차례로 형성하는 단계;(c) sequentially forming a buffer oxide film and a liner nitride film on the semiconductor substrate surface including the trench; (d) 상기 트렌치를 포함한 전면에 제 2 산화막을 형성하여 상기 트렌치를 완전히 매립하는 단계; 및(d) forming a second oxide film on the entire surface including the trench to completely fill the trench; And (e) 상기 트렌치를 제외한 영역에 형성된 제 2 산화막과, 라이너 질화막과 버퍼 산화막을 제거하여 상기 트렌치 내에 소자분리막을 형성하는 단계를 포함하여 형성하는 플래쉬 메모리 소자의 제조방법.(e) forming a device isolation film in the trench by removing the second oxide film, the liner nitride film, and the buffer oxide film formed in the region excluding the trench. 제 1항에 있어서,The method of claim 1, 상기 (a) 단계는 상기 반도체 기판상에 패드 산화막과 패드 질화막을 형성하는 단계;Step (a) may include forming a pad oxide film and a pad nitride film on the semiconductor substrate; 상기 패드 질화막과 패드 산화막을 선택적으로 제거하는 단계; 및Selectively removing the pad nitride film and the pad oxide film; And 상기 선택적으로 제거된 패드 질화막과 패드 산화막을 마스크로 반도체 기판을 식각하여 트렌치를 형성하는 단계를 포함하는 것을 특징으로 하는 플래쉬 메모리 소자의 제조방법.And etching the semiconductor substrate using the selectively removed pad nitride film and pad oxide film as a mask to form a trench. 제 1항에 있어서,The method of claim 1, 상기 (b) 단계는 상기 트렌치를 포함한 반도체 기판상에 제 1 산화막을 형성하여 상기 트렌치를 완전히 매립하는 단계;Step (b) may include forming a first oxide film on the semiconductor substrate including the trench to completely fill the trench; 상기 CMP 공정으로 제 1 산화막을 식각하여 제 1 산화막을 트렌치 내부에만 남기는 단계; 및Etching the first oxide film by the CMP process to leave the first oxide film only inside the trench; And 상기 제 1 산화막을 습식 식각하여 트렌치 하부에만 제 1 산화막을 남기는 단계를 포함하여 이루어지는 것을 특징으로 하는 플래쉬 메모리 소자의 제조방법.And wet etching the first oxide layer to leave the first oxide layer only in the lower portion of the trench. 제 1항에 있어서,The method of claim 1, 상기 라이너 질화막을 형성한 다음에 어닐링 하는 단계를 더 포함하는 것을 특징으로 하는 플래쉬 메모리 소자의 제조방법.And forming the liner nitride film and then annealing. 제 1항에 있어서,The method of claim 1, 상기 제 1, 제 2 산화막은 HDP 산화막인 것을 특징으로 하는 플래쉬 메모리 소자의 제조방법.And the first and second oxide films are HDP oxide films.
KR1020040112828A 2004-12-27 2004-12-27 Method for fabricating flash memory device KR100645177B1 (en)

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