KR100612592B1 - Light emitting diode having a thermal conductive substrate and method of fabricating the same - Google Patents

Abstract

Disclosed are a light emitting diode having a thermally conductive substrate and a method of manufacturing the same. This light emitting diode comprises a thermally conductive substrate. Light emitting cells spaced apart from each other are positioned on the thermally conductive substrate. Each of the light emitting cells includes a lower semiconductor layer, an upper semiconductor layer positioned over a portion of the lower semiconductor layer, and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer. In addition, an insulating layer is interposed between the thermally conductive substrate and the light emitting cells. In addition, metal wires electrically connect the upper semiconductor layers of the light emitting cells and the lower semiconductor layers of the light emitting cells adjacent thereto. Accordingly, since the light emitting cells operate on the thermally conductive substrate, heat dissipation characteristics are improved.

Light-emitting diodes, light-emitting cells, thermally conductive substrates, semi-insulating layers

Description

LIGHT EMITTING DIODE HAVING A THERMAL CONDUCTIVE SUBSTRATE AND METHOD OF FABRICATING THE SAME

1 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.

2 to 6 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.

7 to 10 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention.

The present invention relates to a light emitting diode and a method of manufacturing the same, and more particularly to a light emitting diode having a thermally conductive substrate and a method of manufacturing the same.

A light emitting diode is a photoelectric conversion semiconductor device having a structure in which an N-type semiconductor and a P-type semiconductor are bonded to each other, and emit light by recombination of electrons and holes. Such light emitting diodes are widely used as display devices and backlights. In addition, the light emitting diode consumes less power and has a longer lifespan than existing light bulbs or fluorescent lamps, thereby replacing its incandescent lamps and fluorescent lamps, thereby expanding its use area for general lighting.

The light emitting diode is repeatedly turned on and off in accordance with the direction of the current under AC power. Therefore, when the light emitting diode is directly connected to an AC power source, the light emitting diode does not emit light continuously and is easily damaged by reverse current.

In order to solve the problem of the light emitting diode, a light emitting diode that can be directly connected to a high voltage AC power source is disclosed in International Publication No. WO 2004/023568 (Al). EMITTING ELEMENTS, which was disclosed by SAKAI et. Al.

According to WO 2004/023568 (Al), the LEDs are two-dimensionally connected in series on an insulating substrate such as a sapphire substrate to form an LED array. These two LED arrays are connected in anti-parallel on the sapphire substrate. As a result, a single chip light emitting device that can be driven by an AC power supply is provided.

However, the sapphire substrate has a relatively low thermal conductivity, which leads to poor heat dissipation. This limit of heat dissipation leads to a limit of the maximum light output of the light emitting device. Therefore, it is required to improve heat dissipation characteristics in order to increase the maximum light output under high voltage AC power supply.

In addition, since the LED arrays alternately operate under an AC power source, the light emitting device has a significantly limited light output compared to the case where the light emitting cells operate simultaneously. Therefore, it is necessary to improve the light extraction efficiency of each light emitting cell in order to increase the maximum light output.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a light emitting diode which can be driven under an AC power source and has improved heat dissipation characteristics.

Another object of the present invention is to provide a light emitting diode having improved light extraction efficiency.

Another object of the present invention is to provide a method of manufacturing a light emitting diode having improved heat emission characteristics and / or light extraction efficiency.

In order to achieve the above technical problem, the present invention provides a light emitting diode having a thermally conductive substrate and a method of manufacturing the same. The light emitting diode according to one aspect of the invention comprises a thermally conductive substrate. The light emitting cells are spaced apart from each other on the thermally conductive substrate. Each of the light emitting cells includes a lower semiconductor layer, an upper semiconductor layer positioned over a portion of the lower semiconductor layer, and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer. In addition, an insulating layer or a semi-insulating layer is interposed between the thermally conductive substrate and the light emitting cells. Meanwhile, metal wires electrically connect the upper semiconductor layers of the light emitting cells and the lower semiconductor layers of the light emitting cells adjacent thereto. Accordingly, since the light emitting cells operate on the thermally conductive substrate, heat emission characteristics can be improved.

Here, the thermally conductive substrate means a substrate having a higher thermal conductivity than the sapphire substrate. The thermally conductive substrate may be a conductive substrate. On the other hand, a "semi-insulating layer" generally refers to a layer of high resistance material whose resistivity is at least about 10 ⁵ Ω · cm at room temperature. In the present specification, unless otherwise stated, the semi-insulating layer includes an insulating layer.

An electrode pad may be formed on the upper semiconductor layer and connected to the metal wiring. The electrode pad is in ohmic contact with the upper semiconductor layer. In addition, a transparent electrode layer may be interposed between the electrode pad and the upper semiconductor layer.

The lower semiconductor layer and the upper semiconductor layer of the light emitting cell may be P-type and N-type semiconductor layers, or N-type and P-type semiconductor layers. Preferably, the lower semiconductor layer is a P-type semiconductor layer, and the upper semiconductor layer is an N-type semiconductor layer. In addition, the top surface of each upper semiconductor layer may be roughened. As the upper surface of the upper semiconductor layer is formed to be rough, the light extraction efficiency of light emitted from the active layer to the upper semiconductor layer is improved.

A method of manufacturing a light emitting diode according to another aspect of the present invention includes forming semiconductor layers including a buffer layer, a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer on a first substrate. In addition, an insulating layer or a semi-insulating layer is formed on a second thermally conductive substrate separate from the first substrate. Thereafter, the semiconductor layers and the insulating layer or the semi-insulating layer are bonded so that the second conductive semiconductor layer and the insulating layer or the semi-insulating layer face each other. Subsequently, the first substrate is separated from the semiconductor layers. Thereafter, the semiconductor layers are patterned to emit light including lower semiconductor layers spaced apart from each other, an upper semiconductor layer positioned above a portion of each lower semiconductor layer, and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer. Cells are formed. Thereafter, metal interconnections are formed to electrically connect the upper semiconductor layers of the light emitting cells and the lower semiconductor layers of the light emitting cells adjacent thereto. Accordingly, a light emitting diode in which light emitting cells are formed on a thermally conductive substrate can be manufactured.

The semiconductor layers may be patterned to form lower semiconductor layers spaced apart from each other, and then the exposed insulating layer or semi-insulating layer may be removed. Accordingly, leakage current through the insulating layer or the semi-insulating layer is prevented.

The first conductive semiconductor layer and the second conductive semiconductor layer may be N-type and P-type semiconductor layers, or P-type and N-type semiconductor layers. Preferably, the first conductivity type semiconductor layer is an N type semiconductor layer, and the second conductivity type semiconductor layer is a P type semiconductor layer.

After separating the first substrate, the remaining buffer layer is removed. Accordingly, the top surface of the N-type semiconductor layer is exposed.

The exposed surface of the N-type semiconductor layer may be roughened to improve light extraction efficiency.

For example, roughening the surface of the N-type semiconductor layer may be performed using a photoelectrochemical (PEC) etching technique. Alternatively, roughening the surface of the N-type semiconductor layer may include forming a metal layer on the exposed N-type semiconductor layer. The metal layer may be heat-treated to form metal islands, and a portion of the N-type semiconductor layer may be etched using the islands as an etching mask. As a result, an N-type semiconductor layer having a rough surface is formed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to ensure that the spirit of the present invention can be fully conveyed to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. And, in the drawings, the width, length, thickness, etc. of the components may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 1, the semi-insulating layers 53 are spaced apart from each other on the thermally conductive substrate 51. The thermally conductive substrate 51 is not limited as long as the thermal conductivity is higher than that of the sapphire substrate, and may be a metal substrate or a conductive single crystal substrate.

The semi-insulating layer may be an insulating oxide film or a semi-insulating layer, and a material having high thermal conductivity is preferable. The semi-insulating layer may be formed of an undoped semiconductor layer. If the undoped semiconductor layer is an N-type or P-type semiconductor layer, the semi-insulating layer may be formed by counter-doping ions to compensate for this.

The light emitting cells 30 are positioned on the semi-insulating layers 53. The light emitting cell 30 includes a lower semiconductor layer 29a, an active layer 27a, and an upper semiconductor layer 25a. The upper semiconductor layer 25a is positioned on a portion of the lower semiconductor layer 29a, and the active layer 27a is interposed between the lower semiconductor layer 29a and the upper semiconductor layer 25a. The lower semiconductor layer and the upper semiconductor layer may be P-type and N-type semiconductor layers, or N-type and P-type semiconductor layers. Here, the case where the lower semiconductor layer 29a is a P-type semiconductor layer and the upper semiconductor layer 25a is an N-type semiconductor layer 25a will be described.

N-type semiconductor layer (25a) may include a cladding layer N-type _{Al x In y Ga 1 -x- y} N may have a (0≤x, y, x + y≤1 ), N -type. In addition, the P-type semiconductor layer 29a may be formed of P-type Al _x In _y Ga _{1- xy} N (0 ≦ x, y, x + y ≦ 1), and may include a P-type cladding layer. The N-type semiconductor layer 25a may be formed by doping silicon (Si), and the P-type semiconductor layer 29a may be formed by doping zinc (Zn) or magnesium (Mg).

The active layer 27a is a region where electrons and holes are recombined, and includes InGaN. The emission wavelength emitted from the light emitting cell is determined according to the type of material constituting the active layer 27a. The active layer 27a may be a multilayer film in which a quantum well layer and a barrier layer are repeatedly formed. The barrier layer and the well layer may be binary to quaternary compound semiconductor layers represented by general formula Al _x In _y Ga _{1 −x− y} N (0 ≦ x, y, x + y ≦ 1).

In general, a buffer layer is interposed between the thermally conductive substrate 51 and the light emitting cell 30, but in the embodiments according to the present invention, the buffer layer is not interposed and the semi-insulating layer 53 is interposed.

Meanwhile, the metal wires 57 electrically connect the N-type semiconductor layer 25a and the P-type semiconductor layer 29a of the light emitting cell adjacent thereto. To this end, an electrode pad 55a may be formed on each of the N-type semiconductor layers 25a. The electrode pad 55a is in ohmic contact with the N-type semiconductor layer 25a to lower the contact resistance. In addition, an electrode pad 55b may be formed on a portion of the P-type semiconductor layer 29a. The electrode pad 55b is in ohmic contact with the P-type semiconductor layer 29a to lower the contact resistance. Accordingly, the metal wiring 57 connects the electrode pad 55a on the N-type semiconductor layer 25a and the electrode pad 55b on the P-type semiconductor layer 29a, as shown in the figure, to emit light. Field 30 is electrically connected. The light emitting cells 30 form an array connected in series by the metal wires 57. Arrays of two or more series-connected light emitting cells may be formed on the substrate 51, and the arrays may be connected in reverse parallel to each other and driven by an AC power source.

Meanwhile, in the present embodiment, the semi-insulating layer 53 is described as being separated from each other, but the semi-insulating layer 53 may be connected to each other and may be continuous.

10 is a cross-sectional view for describing a light emitting diode according to another exemplary embodiment of the present invention. Here, the same reference numerals as those of Fig. 1 denote the same components. Therefore, a different point from the embodiment shown in FIG. 1 is demonstrated concretely.

Referring to FIG. 10, unlike the N-type semiconductor layer 25a of FIG. 1, the top surface of the N-type semiconductor layer 65a according to the present exemplary embodiment has a rough surface. Accordingly, the light emitting cell 70 has an upper surface of the rough surface, and as a result, the light extraction efficiency is improved by reducing the total reflection due to the difference in refractive index in the upper surface.

The rough surface may be formed on the entire surface of the N-type semiconductor layer 65a, and an electrode pad may be formed on a portion of the rough surface. Alternatively, the rough surface may be selectively formed in a region other than a partial region of the N-type semiconductor layer 65a, and an electrode pad 55a may be formed in the partial region.

According to the present embodiment, the surface of the N-type semiconductor layer 65a is formed to be rough, so that the extraction efficiency of light emitted upward from the light emitting cell 70 can be improved.

Hereinafter, a light emitting diode manufacturing method according to the present embodiments will be described in detail.

2 to 6 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 2, semiconductor layers including a buffer layer 23, a first conductive semiconductor layer 25, an active layer 27, and a second conductive semiconductor layer 29 are formed on a first substrate 21. do.

The first substrate 21 is transparent, like a sapphire substrate, and a substrate lattice matched to the semiconductor layers is advantageous.

The buffer layer 23 and the semiconductor layers 25, 27, and 29 may be formed using metal organic chemical vapor deposition (MOCVD), molecular beam growth (MBE), or hydride vapor deposition (HVPE). In addition, the semiconductor layers 25, 27, and 29 may be continuously formed in the same process chamber. The buffer layer 23 is not particularly limited as long as it can mitigate lattice mismatch between the first substrate 21 and the semiconductor layers 25, 27, and 29, and may be formed of, for example, undoped GaN. In addition, the first conductivity type and the second conductivity type semiconductor layers may be P-type and N-type semiconductor layers, or N-type and P-type semiconductor layers.

Meanwhile, a semi-insulating layer 53 is formed on the second thermally conductive substrate 51 separate from the first substrate 21. The second substrate 51 is a thermally conductive substrate, and has a higher thermal conductivity than the sapphire substrate. The second substrate 51 may be a metal substrate or a conductive substrate.

Referring to FIG. 3, the substrates are bonded so that the second conductivity-type semiconductor layer 29 and the semi-insulating layer 53 face each other.

Thereafter, the laser 31 is irradiated from the first substrate 21 side. The laser 31 may be a KrF (248 nm) laser, for example. Since the first substrate 21 is a light transmissive substrate like the sapphire substrate, the laser passes through the first substrate 21 and is absorbed by the buffer layer 23. Accordingly, the buffer layer 23 is decomposed by the absorbed radiation energy at the interface between the buffer layer 23 and the first substrate 21, so that the substrate 21 is separated from the semiconductor layers. do.

Referring to FIG. 4, after the substrate 21 is separated, the remaining buffer layer 23 is removed to expose the surface of the N-type semiconductor layer 25. The buffer layer 23 may be removed using an etching technique or a polishing technique.

Referring to FIG. 5, the semiconductor layers 25, 27, and 29 are patterned using photolithography and etching techniques to form light emitting cells 30 spaced apart from each other.

Each of the light emitting cells 30 includes a lower semiconductor layer 29a, an active layer 27a, and an upper semiconductor layer 25a. The upper semiconductor layer 25a is positioned above a portion of the lower semiconductor layer 29a, and the active layer 27a is interposed between the upper semiconductor layer 25a and the lower semiconductor layer 29a. As a result, a portion of the lower semiconductor layer 29a is exposed. On the other hand, the semi-insulating layer 53 may be formed after the lower semiconductor layer 29a and subsequently etched to isolate from each other.

Referring to FIG. 6, metal wires 57 are formed to electrically connect the upper semiconductor layer 25a of each light emitting cell 30 and the lower semiconductor layer 29a of the light emitting cell 30 adjacent thereto. The metal wires 57 connect the light emitting cells 30 to form an array of light emitting cells connected in series. Two or more such arrays may be formed, and there is provided a light emitting diode in which these arrays are connected in parallel and driven under an AC power source.

Meanwhile, electrode pads 55a and 55b may be formed on the upper semiconductor layer 25a and the lower semiconductor layer 29a before forming the metal wires. The electrode pad 55a is in ohmic contact with the upper semiconductor layer 25a, and the electrode pad 55b is in ohmic contact with the lower semiconductor layer 29a to reduce contact resistance. The metal wires 57 connect the electrode pads 55a and 55b.

According to the present embodiment, it is possible to form light emitting cells on a thermally conductive substrate, thereby providing a light emitting diode that can be driven under an AC power source and has improved heat dissipation characteristics.

In the present exemplary embodiment, when the first semiconductor layer is a P-type semiconductor layer, after the buffer layer 23 is removed, a transparent electrode may be formed on the P-type semiconductor layer.

7 to 10 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to another embodiment of the present invention.

Referring to FIG. 7, the light emitting diode manufacturing method of the present embodiment is subjected to the same process as described with reference to FIGS. 2 to 4. Accordingly, the semi-insulating layer 53 is positioned on the second substrate 51, and the second conductive semiconductor layer 29, the active layer 27, and the first conductive semiconductor layer are disposed on the semi-insulating layer 53. Semiconductor layers comprising 25 are bonded to one another.

In the present embodiment, it is preferable that the first conductive semiconductor layer 25 is an N-type semiconductor layer, and the second conductive semiconductor layer 29 is a P-type semiconductor layer.

Referring to FIG. 8, the exposed N-type semiconductor layer 25 is roughened to form an N-type semiconductor layer 65 having a rough surface. Roughening the surface of the N-type semiconductor layer may be performed using, for example, a photoelectrochemical (PEC) etching technique. The roughening of the surface of the N-type semiconductor layer by PEC etching technique is described in the article "Increase in the extraction efficiency of GaN-based light-emitting diodes via surface roughening" published on February 9, 2004 (APPLIED PHYSICS LETTERS, VOL 84, NO. 6, p855-857). According to this paper, the surface of the N-type semiconductor layer can be roughened by using PEC etching technique using KOH solution and Xe lamp, thereby improving the light extraction efficiency.

Alternatively, roughening the surface of the N-type semiconductor layer 25 may be performed using dry etching. That is, a metal layer is formed on the N-type semiconductor layer 25 and heat is applied to the metal layer to make the metal layer into metal islands. Thereafter, the N-type semiconductor layer 25 is etched using the metal islands as an etching mask to form an N-type semiconductor layer 65 having a rough surface. Residual metal islands are removed using, for example, wet etching.

Meanwhile, during the process, a flat portion may be formed using a mask on a portion of the N-type semiconductor layer 25.

Referring to FIG. 9, as described with reference to FIG. 5, the semiconductor layers 65, 27, and 29 are patterned using photolithography and etching techniques to form light emitting cells 70 spaced apart from each other. Each of the light emitting cells 70 includes a lower semiconductor layer 29a, an upper semiconductor layer 65a formed on a portion of the lower semiconductor layer 29a, and an active layer 27a interposed between the upper semiconductor layer and the lower semiconductor layer. ).

Meanwhile, after the lower semiconductor layer 29a is formed, the exposed semi-insulating layer 53 may be etched and removed. Accordingly, the thermally conductive substrate 51 between the light emitting cells 70 may be exposed.

Referring to FIG. 10, as described with reference to FIG. 6, the upper semiconductor layer 25a of the light emitting cells 70 and the lower semiconductor layer 29a of the light emitting cells 70 adjacent thereto are electrically connected. Metal wires 57 are formed. In addition, as described with reference to FIG. 6, electrode pads 55a and 55b may be formed. The electrode pad 55a may be formed on the flat region of the upper semiconductor layer 65a. When no flat area is formed on the upper semiconductor layer 65a, the electrode pad 55a is formed on the rough surface of the upper semiconductor layer 65a.

According to the present exemplary embodiment, a light emitting diode having an improved light extraction efficiency may be provided by forming a rough surface of the upper surface of the light emitting cell 70, that is, the N-type semiconductor layer.

According to the embodiments of the present invention, it is possible to provide a light emitting diode which can be driven under an AC power source and has improved heat dissipation characteristics, and in addition, a light emitting diode having improved light extraction efficiency can be provided. In addition, the present invention can provide a method for manufacturing a light emitting diode that can be driven under an AC power source and has improved heat emission characteristics and / or light extraction efficiency.

Claims (12)

Thermally conductive substrates; A light emitting cell disposed on the thermally conductive substrate and spaced apart from each other, and including a lower semiconductor layer, an upper semiconductor layer positioned over a portion of the lower semiconductor layer, and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer; field; An insulating layer or semi-insulating layer interposed between the thermally conductive substrate and the light emitting cells; And And metal wires electrically connecting upper semiconductor layers of the light emitting cells and lower semiconductor layers of light emitting cells adjacent to the light emitting cells. The method according to claim 1, And an electrode pad formed on each of the upper semiconductor layers and connected to the metal wiring. The method according to claim 1, Each lower semiconductor layer of the light emitting cells is a P-type semiconductor layer, the upper semiconductor layer is an N-type semiconductor layer. The method according to claim 3, The upper surface of each of the upper semiconductor layer is a light emitting diode formed rough to increase the light extraction efficiency. The method according to claim 1, The insulating layer or the semi-insulating layer is isolated from each other corresponding to the lower semiconductor layer. Forming semiconductor layers including a buffer layer, a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer on the first substrate, Forming an insulating layer or a semi-insulating layer on the second thermally conductive substrate, Bonding the semiconductor layers to the insulating layer or the semi-insulating layer such that the second conductive semiconductor layer and the insulating layer or the semi-insulating layer face each other; Separating the first substrate from the semiconductor layers, Patterning the semiconductor layers to form light emitting cells including lower semiconductor layers spaced apart from each other, an upper semiconductor layer positioned over a portion of each lower semiconductor layer, and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer and, And forming metal wires electrically connecting the upper semiconductor layers of the light emitting cells and the lower semiconductor layers of the light emitting cells adjacent thereto. The method according to claim 6, Patterning the semiconductor layers to form lower semiconductor layers spaced apart from each other, and then removing the exposed insulating layer. The method according to claim 6, The first conductive semiconductor layer is an N-type semiconductor layer, the second conductive semiconductor layer is a P-type semiconductor layer manufacturing method. The method according to claim 8, After removing the first substrate, removing the buffer layer to expose an N-type semiconductor layer. The method according to claim 9, The method of manufacturing a light emitting diode further comprising roughening the surface of the exposed N-type semiconductor layer. The method according to claim 10, Roughening the surface of the exposed N-type semiconductor layer is performed using a PEC etching technique. The method according to claim 10, Roughening the surface of the exposed N-type semiconductor layer is Forming a metal layer on the exposed N-type semiconductor layer, Heat treating the metal layer to form metal islands, And etching a portion of the N-type semiconductor layer by using the islands as an etching mask.

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