KR100601166B1 - a manufacturing method of a thin film transistor substrate for a liquid crystal display - Google Patents

Abstract

A gate insulating film, a semiconductor layer, a contact layer and a data conductive layer are successively deposited on the gate wirings, and a photosensitive film is coated on the data conductive layer. The coated photoresist is exposed and developed to form a photoresist pattern, followed by partial dry etching under conditions having an almost vertical etching angle, and when the bottom gate insulating film remains at a thickness of about 1,500 to 2,500 Å, Stops etching Subsequently, the lateral dryness is performed under conditions in which the etch selectivity between the semiconductor layer and the contact layer and the gate insulating film each consisting of amorphous silicon and n ⁺ amorphous silicon is high, that is, the semiconductor layer and the contact layer are rapidly etched while the gate insulating film is hardly etched. By etching, the semiconductor layer and the contact layer are removed on the gate line and the gate connection line. Next, the data conductive layer is etched by wet etching to remove the undercut structure between the semiconductor layer and the conductive layer. By using such a method, in the method of manufacturing a thin film transistor substrate using four masks in which multiple layers of a gate insulating film, a semiconductor layer, a contact layer and a data conductive layer must be simultaneously etched, the step difference near the edge of the pixel region can be reduced. As a result, rubbing defects at the edges of the pixel region can be reduced.

 Mask, four pieces, etching, rubbing, light leakage, step, thin film transistor, liquid crystal display

Description

A manufacturing method of a thin film transistor substrate for a liquid crystal display}

1 is a thin film transistor substrate for a liquid crystal display according to an embodiment of the present invention,

FIG. 2 is a cross-sectional view sequentially illustrating a layered structure cut along lines II-II, III-III, IV-IV ', and V-V' of FIG. 1.

3 is a cross-sectional view taken along the line VI-VI 'of FIG. 1,

4A, 5A, 6A and 4B, 5B and 6B are layout views and cross-sectional views in an intermediate process of manufacturing a structure according to the first embodiment of the present invention shown in FIGS. Will,

7A to 7C are cross-sectional views illustrating in detail an embodiment of a manufacturing process corresponding to steps of FIGS. 5A and 5B, centered on pixel electrode edges.

8A and 8B are cross-sectional views illustrating another embodiment of the manufacturing process corresponding to the steps of FIGS. 5A and 5B in detail with respect to the pixel edges;

9 is a cross-sectional view showing a state in which an alignment film is coated on a thin film transistor substrate surface with respect to the edge of the pixel region.

The present invention relates to a method for manufacturing a thin film transistor substrate for a liquid crystal display device, and more particularly, to a method for manufacturing a thin film transistor substrate for a liquid crystal display device using four masks.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

The substrate on which the thin film transistor is formed is generally manufactured through a photolithography process using a mask. Currently, five or six masks are commonly used. In this case, in order to reduce the production cost, it is preferable to reduce the number of masks, and a method of manufacturing a thin film transistor substrate using four masks has been disclosed. As the number of masks used decreases, more layers of multilayers must be deposited and etched simultaneously, which is very difficult to apply in practice. In addition, the level difference at the edge of the pixel region may be high, such that poor alignment film coating or poor rubbing may occur. Such defects cause light leakage around the pixel area.

An object of the present invention is to provide a method of manufacturing a thin film transistor substrate for a liquid crystal display device using four masks.

Another object of the present invention is to provide a method of manufacturing a thin film transistor substrate that solves a problem of light leakage caused by a step near a pixel edge of a liquid crystal display.

In order to achieve this object, in the present invention, after forming a photoresist pattern for patterning a gate insulating film, a semiconductor layer, a contact layer and a data conductive layer, the semiconductor layer, the contact layer and the data conductive layer are laterally oriented using the photoresist pattern. Dry etching and wet etching, or wet etching and dry etching of the data conductive layer, the semiconductor layer, and the contact layer in the lateral direction, respectively.

According to the present invention, a gate wiring is formed on an insulating substrate using a first mask, and a quadrant including a gate insulating film, a semiconductor layer, a contact layer, and a first conductive layer is deposited on the gate wiring, and then on the first conductive layer. Apply a photosensitive film. Second, the photoresist layer is exposed and developed by using a mask to form a photoresist pattern for patterning the quadrature layer, and the photoresist layer pattern is etched using the photoresist pattern as a mask to form a gate insulation layer pattern, a semiconductor layer pattern, a contact layer pattern, and a first conductive layer pattern. After the formation, the photoresist pattern is removed. Subsequently, a second conductive layer for forming a pixel electrode is deposited, and a second conductive layer is etched using a third mask to form a pixel electrode and a data wiring pattern overlapping with the gate wiring, and then covered with a data wiring pattern. The first conductive layer is etched to form a data line. At this time, the channel portion is formed. Fourth, a protective film is formed using a mask, and then the semiconductor layer of the portion not covered with the protective film is etched. Here, the gate insulating film pattern is formed to cover the gate wiring, and the semiconductor layer pattern, the contact layer pattern and the first conductive layer pattern are formed so as not to overlap the gate wiring and positioned inward of the edges of the photoresist pattern and the gate insulating film pattern. .

Here, the gate insulating film pattern, the semiconductor layer pattern, the contact layer pattern, and the first conductive layer pattern may dry-etch a predetermined thickness of the first conductive layer, the contact layer, the semiconductor layer, and the gate insulating film in the vertical direction using the photosensitive film pattern as a mask. Dry etching the semiconductor layer and the contact layer in the lateral direction, wet etching the first conductive layer in the lateral direction, and dry etching the remaining thickness of the remaining gate insulating layer, or forming the first conductive layer in the lateral direction. It may be formed by wet etching, dry etching the semiconductor layer and the contact layer in the lateral direction, and then dry etching the remaining thickness of the remaining gate insulating layer.

It is preferable to dry-etch the semiconductor layer, the contact layer, and the gate insulating film in the lateral direction in a state where the etching selectivity is large, so that only the semiconductor layer and the contact layer are etched without etching the gate insulating film. In addition, it is preferable that the edges of the semiconductor layer pattern and the contact layer pattern formed therefrom are located in the range of 4 μm to 6 μm from the edges of the photoresist pattern and the gate insulation layer pattern.

The gate line may include a double gate line and a gate connection line connecting the double gate line to be parallel to each other.

After forming the passivation layer, an alignment layer may be coated on the surface of the insulating substrate on which the passivation layer and the pixel electrode are formed, and rubbing may be performed. Therefore, the occurrence of defects during rubbing is reduced.

Then, the liquid crystal display according to an exemplary embodiment of the present invention and a manufacturing method thereof will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

First, the structure of the thin film transistor substrate for a liquid crystal display according to the first embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

1 is a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 is a layered structure taken along lines II-II, III-III, IV-IV ', and V-V' of FIG. 1. Are cross-sectional views sequentially shown, and FIG. 3 is a cross-sectional view taken along the line VI-VI 'of FIG. 1.

As shown in Figs. 1 to 3, a gate wiring made of a conductive material such as aluminum or an aluminum alloy is formed on the insulating substrate 10. The gate wiring is connected to the gate line 210 extending in the horizontal direction, the gate connection line 220 connecting the two gate lines 210 facing each other in the vertical direction, and the gate line 210 connected to the ends of the gate line 210. The gate pad 240 and a gate electrode 230 of the thin film transistor which is a part of the gate connection line 220 are applied to the gate line 240. As shown in FIG. 2, the gate line may be formed of a double layer 221; 222, 231; 232, 241, and 242, but may be formed of a single layer or a triple layer. In the case of forming a single layer, it is made of aluminum (Al) or aluminum (Al) -neodymium (Nd) alloy. In case of forming a double layer, the lower layer is made of aluminum (Al) -neodymium (Nd) alloy, and the upper layer is made of molybdenum ( Mo) -tungsten (W) alloy can be made.

A gate insulating layer 300 made of silicon nitride (SiN _x ) is formed on the gate wirings 210, 220, 230, and 240, and is removed from inside the pixel region surrounded by the gate line 210 and the gate connection line 220. The gate line 210 and the gate connection line 220 are covered.

The semiconductor layer 400 made of a semiconductor such as hydrogenated amorphous silicon is formed on the gate insulating layer 300 so as to remain in a net form outside the pixel region, that is, between the gate lines 210 of the adjacent pixels and the gate connection line 220. The gate pad 240 extends to the portion where the gate pad 240 and the data pad are to be formed. The semiconductor layer 400 is formed to have a predetermined width inward from the edge of the gate insulating layer 300, and does not overlap or partially overlap the gate line 210 and the gate connection line 220. In addition, the semiconductor layer 400 of the upper portion 40 of one gate line 210 of another pixel adjacent to the gate electrode 230 of one pixel is removed. This is to prevent a channel from being generated at a portion other than the lower portion of the gate electrode 230.

On the semiconductor layer 400, a contact layer 500 made of a material such as n + hydrogenated amorphous silicon that is heavily doped with n-type impurities is formed, and on the contact layer 500, such as chromium (Cr) or molybdenum-tungsten alloy, etc. Data wirings 610, 620, 630, 640, and 650 are formed. The data lines 610, 620, 630, 640, and 650 may include a data line 610 formed in a vertical direction between adjacent gate connection lines 220 of two pixels, and extend from the data line 610 so that the gate electrode ( First isolated data formed in the vicinity of the source electrode 620 and the gate electrode 230, the drain electrode 630 located opposite the source electrode 620, and the gate pad 240. The conductor 640 and a data pad 650 connected to one end of the data line 610 and receiving an image signal from the outside are included. The contact layer 500 is formed between the semiconductor layer 400 and the data lines 610, 620, 630, 640, and 650, and has almost the same shape as the data lines 610, 620, 630, 640, and 650. .

An opening 2 exposing the gate pad 240 is formed in the gate insulating layer 300, the semiconductor layer 400, the contact layer 500, and the first isolated data conductor 640 formed on the gate pad 240. have.

A transparent conductive material such as indium tin oxide (ITO) is disposed on the data lines 610, 620, 630, 640, and 650 and on the substrate 10 in the pixel region surrounded by the gate line 210 and the gate connection line 220. Conductor patterns 710, 720, 730, 740, 750, and 760 are formed. Of the conductor patterns 710, 720, 730, 740, 750, and 760, the first to third conductor patterns 710, 720, and 730 disposed on the data line 610 and the source and drain electrodes 620 and 630. ) Prevents disconnection of the data line, and the fourth conductor pattern 740 formed on the gate pad 240 is electrically connected to the outside of the gate pad 240 exposed through the opening 2. The fifth conductor pattern 750 formed on the data pad 650 supplements electrical contact between the data pad 650 and the outside. In addition, the fifth conductor pattern 760 formed in the pixel region serves as a pixel electrode, and the fifth conductor pattern 760 overlaps the gate line 210 and the gate connection line 220. It is formed on the insulating film 300. The first conductor pattern 710, the second conductor pattern 720, and the fifth conductor pattern 750 are connected to each other, and the third conductor pattern 730 and the sixth conductor pattern 760 are connected to each other. ) Are connected to each other, but the fourth conductor pattern 740 is separated from the other patterns 710, 720, 730, 750, and 760.

In this case, a transparent conductive material is used as the conductor pattern. However, in the case of a reflective liquid crystal display, an opaque conductive material may be used.

Finally, a passivation layer 800 formed of silicon nitride is formed on the entire surface of the structure, and the passivation layer 800 includes a fourth conductor pattern 740 on the gate pad 240 and a fifth conductive layer on the data pad 650. First to fourth portions exposing the body pattern 750, a part of the gate insulating layer 300 on the gate line 210 of the pixel adjacent to the gate electrode 230, and the sixth conductor pattern 760 that is the pixel electrode, respectively. Openings 2, 4, 6, and 8 are formed.

Next, a method of manufacturing a thin film transistor substrate for a liquid crystal display device having such a structure will be described with reference to FIGS. 1 to 3 and 4A to 6B.

4A, 5A, 6A and 4B, 5B, and 6B are layout and cross-sectional views of a thin film transistor substrate during an intermediate process of manufacturing a structure according to the first embodiment of the present invention shown in FIGS. Will be shown in turn.

First, as shown in FIGS. 4A and 4B, a first double-sided gate line 210 facing in parallel with each other using a mask, a gate electrode 230 that is part of the gate line 210, and a gate line 210. To form a gate line including a gate connection line 220 and a gate pad 26 connected to an end of the gate line 210. As described above, the gate wirings 210, 220, 230, and 240 may be made of a double layer of an aluminum-neodymium alloy film and a molybdenum-tungsten alloy film, and in this case, it is preferable to use dry etching. In addition, a double film of a chromium (Cr) film / aluminum-neodymium alloy film may be used, in which case wet etching is used.

Next, as shown in FIGS. 5A and 5B, the quadruple layer of the gate insulating film 300, the semiconductor layer 400, the contact layer 500, and the data conductive layer 600 made of chromium or aluminum-neodymium alloy is successively connected. Laminate and pattern by dry etching using a second mask. At this time, as shown in Figure 5a, to form a pattern in the form of a matrix or mesh extending in the horizontal and vertical direction between the adjacent pixels, the remaining portion is removed, the gate insulating film 300 of the quad layer of the pattern Cover 210 and the gate connection line 220. Referring to FIG. 5B, triple layers of the remaining semiconductor layer 400, the contact layer 500, and the data conductive layer 600 do not cover the gate line 210 and the gate connection line 220. Form inwards than the edges. An etching method for forming such an edge structure will be further described below with reference to FIGS. 7A to 8B. In addition, an opening 2 is formed in the data conductive layer 600, the contact layer 500, the semiconductor layer 400, and the gate insulating layer 300 to expose the gate pad 240 in the vicinity of the gate pad 240. .

Next, as illustrated in FIGS. 6A and 6B, ITO is deposited to form a transparent conductive layer, and patterned by dry and wet etching using a third mask to form transparent conductor patterns 710, 720, 730, 740, and 750. 760). Next, the data conductive layer 600 and the contact layer 500 are dry-etched, so that the data conductive layer 600 and the contact layer 500 are disposed only under the transparent conductor patterns 710, 720, 730, 740, 750, and 760. Leave the rest and remove the rest.

Lastly, as shown in FIGS. 1 to 3, the openings 2 exposing the conductor pattern 740 on the gate pad 240 by stacking a protective film 800 made of silicon nitride and patterning using a fourth mask. An opening 8 that is formed in the pixel region to expose a conductor pattern 760 to serve as a pixel electrode, an opening 4 to expose a conductor pattern 750 on the data pad 650, and a gate electrode 230. An opening 6 exposing the semiconductor layer 400 over the gate line 210 of the front end pixel adjacent to the gate is formed. The semiconductor layer 400 exposed under the opening 6 is then removed. In this case, etching of the passivation layer 800 and the semiconductor layer 400 may be continuously performed by using dry etching, and the etching gas may include chlorine (Cl ₂ ) / oxygen (etching ratio of silicon nitride to amorphous silicon of about 10: 1). O ₂ ) gas can be used.

After completing the manufacturing process of the thin film transistor substrate in this manner, an alignment film (not shown) is applied to the entire surface of the substrate 10 on which the thin film layer is formed, and rubbing is performed. In the thin film transistor substrate fabricated according to the embodiment of the present invention, since the step difference between the pixel electrodes is relatively small around the pixel region, rubbing can be stably performed.

This will be described in more detail with reference to FIGS. 7A to 8B and 9.

7A to 7C are cross-sectional views illustrating in detail an example of a manufacturing process corresponding to steps of FIGS. 5A and 5B with respect to the pixel electrode edges, and FIGS. 8A and 8B are manufacturing processes corresponding to steps 5A and 5B. Another embodiment of is a cross-sectional view showing in detail around the pixel edge.

First, the gate insulating film 300, the semiconductor layer 400, the contact layer 500, and the data conductive layer 600 are formed to have a thickness of 4,000 to 4,500 4, about 2500 Å, about 500 Å, and 1,000 to 2,000 Å over the gate wiring. It deposits continuously and a photosensitive film is apply | coated on the data conductive layer 600. FIG. The coated photosensitive film is exposed and developed to form a photosensitive film pattern 50 for forming the gate insulating film 300 pattern as shown in FIGS. 5A and 5B. Next, dry etching is performed until the bottommost gate insulating film 300 has a thickness of about 1,500 to 2,500 Å.

Subsequently, if the semiconductor layer 400 and the contact layer 500 and the gate insulating film 300 each made of amorphous silicon and n ⁺ amorphous silicon are dry-etched in the lateral direction under high conditions, as shown in FIG. 7A, While the gate insulating layer 300 is hardly etched, the semiconductor layer 400 and the contact layer 500 are rapidly etched so that the semiconductor layer 400 and the contact layer 500 are formed with the gate lines 211 and 212 and the gate connection line. Retreat outside (221, 222); That is, a thick portion of the gate insulating film 300 is covered on the gate lines 211 and 212 and the gate connection lines 221 and 222, and the semiconductor layer 400 and the contact layer 500 are removed.

As shown in FIG. 7B, the data conductive layer 600 is side-etched by wet etching to remove the undercut structure between the semiconductor layer 400 and the data conductive layer 600. At this time, in order to effectively reduce the step difference near the gate lines 211 and 212 and the gate connection lines 221 and 222, that is, at the edges of the pixel region, the length L of a skew occurring below the photoresist pattern 50 The etching should proceed so that is more than 5μm.

Next, as illustrated in FIG. 7C, after the gate insulating film 300 remaining outside the photoresist pattern 50 is removed by dry etching, the patterning of the gate insulating film 300 is completed, and then the photoresist pattern 50 is stripped. strip) to remove it.

8A and 8B, after the gate insulating film 300, the semiconductor layer 400, the contact layer 500, the data conductive layer 600 and the photosensitive film are formed in the same manner, the photosensitive film is exposed. And the photosensitive film pattern 50 is formed.

Next, as shown in FIG. 8A, the data conductive layer 600 is side-etched by wet etching.

As shown in FIG. 8B, in the same manner as in the above-described method, the semiconductor layer 400 and the contact layer 500 and the gate insulating layer 300 formed of amorphous silicon and n ⁺ amorphous silicon, respectively, have a high lateral selectivity under the high etch selectivity. Dry etching to remove the semiconductor layer 400 and the contact layer 500 on the gate lines 211 and 212 and the gate connection lines 221 and 222. Also in this embodiment, in order to effectively reduce the step difference near the gate lines 211 and 212 and the gate connection lines 221 and 222, that is, at the edges of the pixel region, the skew generated below the photosensitive film pattern 50 It should be etched so that length (L) is more than 5μm.

Next, as shown in FIG. 7C, the gate insulating film 300 remaining outside the photoresist pattern 50 is removed by dry etching to complete the patterning of the gate insulating film 300, and then the photoresist pattern 50 is removed by a strip process. do.

As such, after the steps of FIGS. 7A to 7C or 8A and 8B, the thin film transistor substrate may be manufactured by performing the same processes as those of FIGS. 6A to 6A and 6B and FIGS. 1 to 3.

FIG. 9 is a cross-sectional view showing a state in which an alignment layer is coated on a thin film transistor substrate surface manufactured by the method described above with the edge of a pixel region in the center. FIG.

As illustrated in FIG. 9, the gate insulating layer 300 covers the gate connection lines 221 and 222 surrounding the pixel region, and is removed from the inside of the pixel region, and the semiconductor layer 400 on the gate insulating layer 300. Remains outside the gate connection lines 221 and 222, that is, outside the pixel region. A transparent pixel electrode 760 is formed on the surface of the substrate 10 inside the pixel region, and an edge of the pixel electrode 760 extends to the gate insulating layer 300 on the gate connection lines 221 and 222, thereby forming a pixel electrode. A storage capacitor is formed between 760 and the gate connection lines 221 and 222. In addition, the passivation layer 800 is covered in portions except the pixel region. An alignment film 900 is applied to the passivation layer 800 and the pixel electrode 760 to give the alignment direction of the liquid crystal molecules, and the alignment layer 900 is rubbed. In the thin film transistor substrate manufactured according to the exemplary embodiment of the present invention, rubbing is relatively even in the edge portion A of the pixel region in which the step is determined only by the thickness of the gate insulating layer 300. Can effectively prevent light leakage. In the portion B having a relatively large step, such as at the top of the gate line or the gate connection line 221 and 222, a coating defect or rubbing defect of the alignment film 900 is likely to occur, but is formed on the upper color filter substrate. Since the part is covered by a light shielding film (not shown), it does not cause light leakage.

As described above, when the liquid crystal display device is manufactured according to the exemplary embodiment of the present invention, not only the thin film transistor substrate for the liquid crystal display device can be manufactured using four masks, but also the alignment film is reduced by reducing the step at the edge of the pixel region. And light leakage phenomenon can be prevented by reducing rubbing defects.

Claims (9)

Forming a gate wiring on the insulating substrate using a first mask, Depositing a quad layer comprising a gate insulating layer, a semiconductor layer, a contact layer, and a first conductive layer on the gate wiring; Applying a photosensitive film on the first conductive layer, Exposing and developing the photoresist using a second mask to form a photoresist pattern for patterning the quad layer; Etching the quad layer using the photoresist pattern as a mask to form a gate insulating layer pattern, a semiconductor layer pattern, a contact layer pattern, and a first conductive layer pattern; Removing the photoresist pattern; Depositing a second conductive layer for forming a pixel electrode on the first conductive layer pattern, Etching the second conductive layer using a third mask to form a pixel electrode and a data wiring pattern overlapping the gate wiring; Etching the first conductive layer not covered with the data wiring pattern to form a data wiring; Etching the contact layer not covered with the data line, Forming a protective film using a fourth mask, and Etching the semiconductor layer in a portion not covered with the protective film Including; And the semiconductor layer pattern, the contact layer pattern, and the first conductive layer pattern are positioned inward from edges of the photoresist pattern and the gate insulating layer pattern. In claim 1, Forming the gate insulating layer pattern, the semiconductor layer pattern, the contact layer pattern, and the first conductive layer pattern Dry etching the first thicknesses of the first conductive layer, the contact layer, the semiconductor layer, and the gate insulating layer in the vertical direction by using the photoresist pattern as a mask; Dry etching the semiconductor layer and the contact layer in a lateral direction to form the semiconductor layer pattern and the contact layer pattern; Wet etching the first conductive layer in a lateral direction to form the first conductive layer pattern, and And dry etching the remaining second thickness of the remaining gate insulating film to form the gate insulating film pattern. In claim 1, Forming the gate insulating layer pattern, the semiconductor layer pattern, the contact layer pattern, and the first conductive layer pattern Dry etching the first thicknesses of the first conductive layer, the contact layer, the semiconductor layer, and the gate insulating layer in the vertical direction by using the photoresist pattern as a mask; Wet etching the first conductive layer in a lateral direction to form the first conductive layer pattern; Dry etching the semiconductor layer and the contact layer in a lateral direction to form the contact layer pattern and the semiconductor layer pattern, and And dry etching the remaining second thickness of the remaining gate insulating film to form the gate insulating film pattern. The method of claim 2 or 3, And dry etching in the lateral direction is performed under conditions where an etching rate of the semiconductor layer and the contact layer is higher than an etching rate of the gate insulating layer. In claim 4, The edge of the semiconductor layer pattern and the contact layer pattern is positioned in the 4μm to 6μm from the edge of the photosensitive film pattern and the gate insulating film pattern in a thin film transistor substrate for a liquid crystal display device. In claim 4, The second thickness of the gate insulating film is a manufacturing method of a thin film transistor substrate for a liquid crystal display device. In claim 1, And said second conductive layer is formed of ITO. In claim 1, Applying an alignment layer to a surface of the insulating substrate on which the protective layer and the pixel electrode are formed; and A method of manufacturing a thin film transistor substrate for a liquid crystal display further comprising the step of rubbing the alignment layer. In claim 1, The gate line may include a double gate line formed in parallel with each other and a gate connection line connecting the double gate line.

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