KR100592236B1 - Driving device of plasma display panel with integrated driver - Google Patents

Abstract

The apparatus according to the present invention comprises: address electrode lines arranged parallel to each other on the front side of the rear substrate, and Y electrode lines and X electrode lines on the back side of the front substrate are aligned orthogonally to the address electrode lines, so that the Y electrode line In order to drive the plasma display panel in which the and the X electrode lines are drawn to face each other, the driving apparatus of the plasma display panel is arranged behind the rear substrate to drive the Y electrode lines and the X electrode lines. The device includes an integrated drive and an X connection. The integrated driver is disposed at a position adjacent to the extraction position of the Y electrode lines to drive the Y electrode lines and the X electrode lines. The X connection portion is disposed at a position adjacent to the extraction position of the X electrode lines to connect the X drive output line from the integrated driver to the X connection lines from the X electrode lines.

Description

Apparatus for driving plasma display panel with integrated driver

1 is an internal perspective view showing the configuration of a typical three-electrode plasma display panel.

FIG. 2 is a timing diagram showing typical driving signals applied to the panel of FIG. 1.

3 is a cross-sectional view illustrating a wall charge distribution of one display cell at a time point immediately after a gradual rising voltage is applied to the Y electrode lines in the reset period of FIG. 2.

4 is a cross-sectional view illustrating a wall charge distribution of one display cell at the end of the reset cycle of FIG. 2.

5 is a view illustrating a conventional driving device for generating the driving signals of FIG. 2.

6 shows an internal circuit of the Y drive of the device of FIG. 5.

7 shows an internal circuit of the X driver of the device of FIG. 5.

8 is a view showing a driving apparatus according to the present invention for generating the driving signals of FIG. 2.

FIG. 9 shows an internal circuit of the XY integrated driver of the apparatus of FIG. 8. FIG.

<Explanation of symbols for the main parts of the drawings>

1 ... plasma display panel, 10 ... front glass substrate,

11 dielectric layer, 12 magnesium monoxide layer,

13 ... back glass substrate, 14 ... discharge space,

16 fluorescent layers, 17 bulkheads,

X ₁ , ... X _n ... X electrode line, Y ₁ , ... Y _n ... Y electrode line,

A _R1 , A _G1 , ..., A _Gm , A _Bm ... address electrode line,

SF ... unit sub-field, PR ... reset period,

PA ... address cycle, PS ... fatty cycle,

W _Y1 , ..., W _Yn ... Y connection line, 41a, 41b ... Y output buffer section,

L _Y1 , ..., L _Yn ... Y output line, 42 ... XY integrated drive,

43 control unit, 44 power supply unit,

45 ... X connection, P3 ... power supply cable,

FPC ... X drive output line, S _CY ... Y drive control signal,

S _CX ... X drive control signal, W _X1 , ..., W _Xn ... X connection line.

The present invention relates to a driving apparatus for a plasma display panel, and more particularly, to a plasma disposed on a substrate arranged behind a rear substrate of a three-electrode surface discharge plasma display panel to drive Y electrode lines and X electrode lines. It relates to a drive device for a display panel.

1 shows a configuration of a typical three-electrode plasma display panel 1.

Referring to FIG. 1, between the front and rear glass substrates 10 and 13 of a typical three-electrode plasma display panel 1, the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm ), dielectric layers 11 and 15, Y electrode lines (Y ₁ , ... Y _n ), X electrode lines (X ₁ , ... X _n ), fluorescent layer 16, partition wall 17 ) And a magnesium monoxide (MgO) layer 12 as a protective layer.

The address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm are formed in a predetermined pattern on the front surface of the rear glass substrate 13. The lower dielectric layer 15 is entirely formed in front of the address electrode lines A _R1 , A _G1 ,..., A _Gm , and A _Bm . The barrier ribs 17 are formed on the front surface of the lower dielectric layer 15 in a direction parallel to the address electrode lines A _R1 , A _G1 ,..., A _Gm and A _Bm . These partitions 17 function to partition the discharge area of each display cell and prevent optical cross talk between each display cell. The fluorescent layer 16 is formed between the partition walls 17.

The X electrode lines X ₁ , ... X _n and the Y electrode lines Y ₁ , ... Y _n are address electrode lines A _R1 , A _G1 , ..., A _Gm , A _Bm It is formed in a predetermined pattern on the back of the front glass substrate 10 so as to be orthogonal. Each intersection defines a corresponding display cell. The upper dielectric layer 11 is formed behind the X electrode lines X ₁ , ... X _n and the Y electrode lines Y ₁ , ... Y _n . A magnesium monoxide (MgO) layer 12 for protecting the panel 1 from the strong electric field is formed on the backside of the upper dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

FIG. 2 shows typical drive signals applied to the panel of FIG. 1. In FIG. 2, reference numeral S _{AR1 ..ABm} denotes a drive signal applied to each address electrode line (A _R1 , A _G1 ,..., A _Gm , A _{Bm in} FIG. 1), and S _{X1 .. Xn} denotes an X electrode. The driving signal applied to the lines (X ₁ , ... X _{n in} FIG. 1), and S _Y1 , ..., S _Yn are the respective Y electrode lines (Y ₁ , ... Y _{n in} FIG. 1). Indicates a drive signal applied to. FIG. 3 shows a wall charge distribution of one display cell immediately after a gradual rising voltage is applied to the Y electrode lines Y ₁ , ... Y _n in the reset period PR of FIG. 2. 4 illustrates a wall charge distribution of one display cell at the end of the reset period PR of FIG. 2. 3 and 4, reference numerals X _na and Y _na denote transparent electrode lines made of a transparent conductive material such as indium tin oxide (ITO), and X _nb and Y _nb denote metal electrode lines for increasing conductivity.

Referring to FIG. 2, in the reset period PR of the unit sub-field SF, first, the voltage applied to the X electrode lines X ₁ ,..., X _n is _first divided from the ground voltage V _G. One voltage (V _E ) is continuously raised to, for example, 184 volts (V). Here, the ground voltage V _G is applied to the Y electrode lines Y ₁ ,..., Y _n and the address electrode lines A ₁ ..., A _m . Accordingly, between the X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), and the X electrode lines (X ₁ , ..., X) A weak discharge occurs between _n ) and the address electrode lines A ₁ , ..., A _m , and negative wall charges are formed around the X electrode lines X ₁ , ..., X _n . .

And then from the, Y electrode lines _{(Y 1, ..., Y n} ) , for the voltage is slightly below the second voltage (V _S) for example, less than the first voltage (V _E), 155 volts (V) applied to the the second voltage (V _S) by a higher peak voltage (V _SET + V _S) than the third voltage (V _SET), for example, and continue to rise up to 355 volts (V). Here, the ground voltage V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A ₁ ,..., A _m . Accordingly, a weak discharge occurs between the Y electrode lines (Y ₁ ,..., Y _n ) and the X electrode lines (X ₁ ,..., X _n ), while the Y electrode lines (Y ₁ , ..., Y _n ) and weaker discharge occurs between the address electrode lines A ₁ , ..., A _m . Here, Y electrode lines _{(Y 1, ..., Y n} ) and the address electrode lines _{(A 1, ..., A m} ) of discharge than Y electrode line between the (Y _1, ..., Y _The reason why the discharge between _n ) and the X electrode lines (X ₁ , ..., X _n ) becomes stronger is that the negative wall charges around the X electrode lines (X ₁ , ..., X _n ) Because they were formed. Accordingly, many negative wall charges are formed around the Y electrode lines (Y ₁ ,..., Y _n ), and positive wall charges are formed around the X electrode lines (X ₁ , ..., X _n ). Are formed, and less positive wall charges are formed around the address electrode lines A ₁ , ..., A _m (see FIG. 3).

Next, while the voltage applied to the X electrode lines X ₁ ,..., X _n is maintained at the first voltage V _E , the Y electrode lines Y ₁ ,..., Y _n The voltage applied to) is continuously lowered from the second voltage V _S to the ground voltage V _G. Here, the ground voltage V _G is applied to the address electrode lines A ₁ ,..., A _m . Accordingly, due to the weak discharge between the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), the Y electrode lines (Y ₁ ,. Some of the negative wall charges around..., Y _n ) move around the X electrode lines X ₁ ,..., X _n (see FIG. 4). Here, the address electrode lines _{(A 1, ..., A m} ) is applied, because the ground voltage (V _G), the address electrode lines positive wall charges around the _{(A 1, ..., A m} ) are Slightly increased.

Accordingly, in the subsequent addressing step PA, the display data signal is applied to the selected address electrode lines A ₁ ,..., A _m , and the fourth voltage V _SCAN lower than the second voltage V _S. As a scan signal of the ground voltage V _G is sequentially applied to the Y electrode lines Y ₁ ,..., And Y _n biased by), smooth addressing may be performed. The display data signal applied to each of the address electrode lines A _R1 , A _G1 , ..., A _Gm , A _Bm has a positive address voltage V _A when the display cell is selected, and a ground voltage V otherwise. _G ) is applied. Accordingly, when the display data signal of the positive address voltage V _A is applied while the scan pulse of the ground voltage V _G is applied, wall charges are formed by the address discharge in the corresponding display cell, and the wall charge in the other display cell. Are not formed. Here, for a more accurate and efficient address discharge, the first voltage V _E is applied to the X electrode lines X ₁ , X _n .

In the sustain discharge period PS that follows, the sustain discharge of the second voltage V _S is applied to all the Y electrode lines Y ₁ ,... Y _n and the X electrode lines X ₁ , ... X _n . Pulses are applied alternately, causing sustain discharge in display cells in which wall charges are formed in the corresponding address period PA.

Thus, as shown in FIG. 2, to drive the X electrode lines X ₁ , ... X _n and the Y electrode lines Y ₁ , ... Y _n , four power-voltages V _E , V _S , V _SET , V _SCAN ) is required.

Conventional driving apparatus of Figure 5, the plasma display panel (Fig. 1) are arranged on the back of the Y-electrode line of the back of the substrate 13 (FIG. 1 Y _1, a ... Y _n) and the X-electrode line of Drive them (X ₁ , ... X _{n in} FIG. ₁ ). Accordingly, in the driving apparatus of Figure 5, the address electrode lines (Fig. 1 of _R1 A, _G1 A, ..., A _{Gm, Bm} A) according to the display data from the array in a separate position control unit 33 The address driver to drive does not appear.

Referring to FIG. 5, a driving apparatus of a conventional plasma display panel includes Y output buffer units 31a and 31b, a Y driver 32, a controller 33, a power supply 34, and an X driver 35. . Here, Y output buffer portions (31a, 31b) and the Y-driver 32 is in a position adjacent to the take-off position of the Y electrode lines (Y _1, ... Y _n). In addition, the X driver 35 is at a position adjacent to the extraction position of the X electrode lines X ₁ , ... X _n .

The power supply unit 34 supplies three power-voltages V _S , V _SET , and V _SCAN to the Y driver 32 through the Y power supply cable P1. The control unit 33 inputs the Y drive control signal S _CY to the Y drive unit 32. Accordingly, the Y driver 32 outputs signals for driving the Y electrode lines Y ₁ , ... Y _n through the Y output lines L _Y1 ,..., L _Yn , and this signal. They are input to the corresponding Y electrode lines Y ₁ , ..., Y _n through the Y output buffer portions 31a, 31b and the Y connection lines W _Y1 ,..., W _Yn .

In addition, the power supply unit 34 supplies two power-voltages V _E and V _S to the X driver 35 through the X power supply cable P2. The controller 33 inputs the X drive control signal S _CX to the X driver 35. Accordingly, the X driver 35 inputs driving signals to the X electrode lines X ₁ ,..., Y _n through the X connection lines W _X1 ,..., W _Xn .

The internal circuit of the Y driver 32 of FIG. 6 will be described with reference to FIGS. 2 and 6 as follows.

When the ground voltage V _G is applied to all the Y output lines L _Y1 ,..., L _Yn in the reset period PR, the fourth switch SW4 of the Y-common driver 5 is turned on. It is turned on and all the tenth and fifteenth switches SW10 and SW15 of the scan driver 6 are turned on.

When the second voltage V _S is applied to all of the Y output lines L _Y1 ,..., L _Yn , the third switch SW3 of the Y-common driver 5 is turned on and scans. All tenth and fifteenth switches SW10 and SW15 of the driving unit 6 are turned on. In this way all the Y output lines as higher maximum second voltage (V _S) the third voltage than the second voltage (V _S) is applied in a state (V _SET) to (L _Y1, ..., _Yn L) To continuously raise the voltages of all the Y output lines L _Y1 , ..., L _{Yn up} to the voltage V _SET + V _S , all the ninth switches SW9 of the scan driver 6 must be _reset . It operates by one ramp rising signal RAMP1. Accordingly, in all the scan driving circuits SD1, SD2,..., SDn of the scan driver 6, the resistor R _SET , the diode D _SET , and the ninth switch are connected from the third voltage V _SET terminal. Through SW9, a continuously increasing current flows.

All scans of the scan driver 6 when the voltage applied to all Y output lines L _Y1 , ..., L _Yn is continuously lowered from the second voltage V _S to the ground voltage V _G. In the driving circuits SD1, SD2,. It works. Accordingly, the current flowing from each Y output line (L _Y1 ,..., L _Yn ) to the ground terminal through the fifteenth, tenth and eleventh switches SW15, SW10 and SW11 is continuously increased.

In the address period PR, a scan signal of the ground voltage V _G is sequentially applied to the Y output lines L _Y1 ,..., L _Yn biased with the fourth voltage V _SCAN . To this end, the twelfth and fourteenth switches SW12 and SW14 are turned on in the scan driving circuits corresponding to the non-scanned Y output lines. In contrast, in the scan driving circuit corresponding to any one Y electrode line to be scanned, the tenth, eleventh, and fifteenth switches SW10, SW11, and SW15 are turned on. Here, since the highest voltage of the second linear rising signal RAMP1 is applied to the ninth switches SW9, the ground voltage V _G is applied to the Y output line.

The Y-common driver 5 includes a charge / discharge capacitor C _SY , four switching elements SW1,..., SW4, a tuning coil LY, a current control diode, and the like. In the sustain discharge period PS, the first switching element SW1 is immediately before the sustain discharge pulse of the second voltage V _S is applied to all the Y output lines L _Y1 ,..., L _Yn . Charges that are turned on and collected in the charge / discharge capacitor C _SY are applied to the Y electrode lines Y ₁ ,... Y _n through the tuning coil LY and the scan driver 6. In addition, when the third switch SW3 is turned off, that is, when the sustain discharge pulse of the second voltage VS _S ends, the second switching device SW1 is turned on to display the plasma display. Unnecessary charges are collected in each display cell of the panel. The fourth switching element (SW4), the second voltage is turned off (Off), X electrode lines during applying the sustain discharge pulses of (V _S) to the Y electrode lines (Y _1, ... Y _n) On while the sustain discharge pulse of the second voltage V _S is applied to (X ₁ , ... X _n ).

Referring to FIG. 7, the X driver 35 of the apparatus of FIG. 5 includes a sixteenth switch SW16 and an X-common driver 35M. The X-common driver 4 includes a charge / discharge capacitor C _SX , four switching elements SW5,..., SW8, a tuning coil LX, a current control diode, and the like. In the reset period (PR in FIG. 2), the voltage applied to the X connection lines W _X1 ,..., X _Xn by the sixteenth switch SW16 is operated by the third slope rising signal RAMP3. The voltage is continuously raised from the ground voltage V _G to the first voltage V _E. On the other hand, in the sustain discharge period PS, the fifth switching element SW5 is immediately before the sustain discharge pulse of the second voltage V _S is applied to the X connection lines W _X1 and W _Xn . Charges that have been turned on and collected in the charge / discharge capacitor C _SX are applied to the X electrode lines X ₁ ,... X _n through the tuning coil LX. In addition, when the seventh switch SW7 is turned off, that is, when the sustain discharge pulse of the second voltage VS _S ends, the sixth switching element SW6 is turned on to display the plasma display. Unnecessary charges are collected in each discharge cell of the panel. The eighth switching element SW8 is turned off while the sustain discharge pulse of the second voltage V _S is applied to the X connection lines W _{X1 to} W _Xn , and the Y electrode lines ( On during the sustain discharge pulse of the second voltage V _S is applied to Y ₁ , ... Y _n ).

According to the conventional driving apparatus as described above (see US Patent No. 4,866,349), the X-common driving unit (35M in FIG. 7) and the Y-common driving unit (5 in FIG. 6) performing only similar functions in the same driving period are Separated separately. Accordingly, expensive charge / discharge capacitors C _SX and C _SY are used separately, thereby causing an uneconomic problem. In addition, since the power supply cables P1 and P2 from the power supply unit 34 in FIG. 5 must be connected to the Y driver unit 32 in FIG. 5 and the X driver unit 35 in FIG. There is a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a drive device capable of increasing the economy and efficiency in a drive device of a three-electrode surface discharge plasma display panel.

The apparatus of the present invention for achieving the above object, the address electrode lines arranged in parallel to each other on the front surface of the rear substrate, and the Y electrode lines and X electrode lines on the rear surface of the front substrate are aligned orthogonally to the address electrode lines Driving the plasma display panel arranged behind the rear substrate to drive the Y electrode lines and the X electrode lines so as to drive the plasma display panel in which the Y electrode lines and the X electrode lines are drawn to face each other. Device. The device includes an integrated drive and an X connection. The integrated driver is disposed at a position adjacent to the extraction position of the Y electrode lines to drive the Y electrode lines and the X electrode lines. The X connection part is disposed at a position adjacent to the extraction position of the X electrode lines to connect the X drive output line from the integrated driver to the X connection lines from the X electrode lines.

According to the driving apparatus of the plasma display panel of the present invention, the Y electrode lines and the X electrode lines are driven by the integrated driver disposed at a position adjacent to the extraction positions of the Y electrode lines. As a result, an expensive charge / discharge capacitor used for power recovery in the sustain discharge cycle, and a power supply cable from the power supply unit can be shared, thereby improving economic efficiency and efficiency.

Preferably, the X drive output line is a conductor of F. C. (Flexible Printed Circuit). Accordingly, the voltage drop in the X driving output line can be minimized.

Hereinafter, preferred embodiments according to the present invention will be described in detail.

A drive device according to the present invention of Figure 8, a plasma display panel (Fig. 1) are arranged on the back of the Y-electrode line of the rear substrate (13 of FIG. _1, Y 1, ... Y _n) and X The electrode lines (X ₁ , ... X _{n in} FIG. ₁ ) are driven. Accordingly, in the driving apparatus of Figure 5, the address electrode lines (Fig. 1 of _R1 A, _G1 A, ..., A _{Gm, Bm} A) according to the display data from the array in a separate position control unit 33 The address driver to drive does not appear.

Referring to FIG. 8, the driving apparatus of the plasma display panel according to the present invention includes the Y output buffer units 41a and 41b, the XY integrated driver 42, the control unit 43, the power supply unit 44, and the X connection unit 45. It includes. Here, Y output buffer portions (41a, 41b) and XY integrated driver 42 is at a position adjacent to the take-off position of the Y electrode lines (Y _1, ... Y _n). Further, the X connecting portion 45 is at a position adjacent to the withdrawal position of the X electrode lines X ₁ , ... X _n . The connecting portion X (45) X XY drive output lines (FPC) from the integrated driver 42 to the X electrode lines X wiring lines from the _{(X 1, ..., Y n} ) (W X1, ... , W _Xn ). Here, the X drive output line FPC is a conductor of F.C (Flexible Printed Circuit).
Here, F. C. conductor used as the X drive output line (FPC) forms a single line in a flexible printed circuit. That is, the X wiring lines W _X1 , ..., W _Xn are commonly connected through the conductors of F. P. C used as the X driving output line FPC.

The power supply unit 44 supplies four power-voltages V _E , V _S , V _SET and V _SCAN to the XY integrated driver 42 through the XY power supply cable P3. The control unit 43 inputs the Y drive control signal S _CY and the X drive control signal S _CX to the XY integrated drive unit 42. Accordingly, the XY integrated driver 42 outputs signals for driving the Y electrode lines Y ₁ , ... Y _n through the Y output lines L _Y1 ,..., L _Yn , These signals are input to the corresponding Y electrode lines Y ₁ , ..., Y _n through the Y output buffer portions 41a, 41b and the Y connection lines W _Y1 , ..., W _Yn . . In addition, the XY integrated driver 42 may be connected to the X electrode lines X ₁ ,... Through the X drive output line FPC, the X connection unit 45, and the X connection lines W _X1 ,..., W _Xn . ., Y _n ) to drive signals.

An internal circuit of the XY integrated driver 42 of FIG. 8 will be described with reference to FIGS. 2 and 9 as follows.

When the ground voltage V _G is applied to all of the Y output lines L _Y1 ,..., L _Yn in the reset period PR, the fourth switch SW4 of the Y-common driver 5 is turned on. It is turned on and all the tenth and fifteenth switches SW10 and SW15 of the scan driver 6 are turned on. Meanwhile, when the sixteenth switch SW16 is operated by the third slope rising signal RAMP3, the voltage applied to the X driving output line FPC is increased from the ground voltage V _G to the first voltage V _E. Continuously rising.

When the second voltage V _S is applied to all of the Y output lines L _Y1 ,..., L _Yn , the third switch SW3 of the Y-common driver 5 is turned on and scans. All tenth and fifteenth switches SW10 and SW15 of the driving unit 6 are turned on. In this way all the Y output lines as higher maximum second voltage (V _S) the third voltage than the second voltage (V _S) is applied in a state (V _SET) to (L _Y1, ..., _Yn L) To continuously raise the voltages of all the Y output lines L _Y1 , ..., L _{Yn up} to the voltage V _SET + V _S , all the ninth switches SW9 of the scan driver 6 must be _reset . It operates by one ramp rising signal RAMP1. Accordingly, in all the scan driving circuits SD1, SD2,..., SDn of the scan driver 6, the resistor R _SET , the diode D _SET , and the ninth switch are connected from the third voltage V _SET terminal. Through SW9, a continuously increasing current flows.

All scans of the scan driver 6 when the voltage applied to all Y output lines L _Y1 , ..., L _Yn is continuously lowered from the second voltage V _S to the ground voltage V _G. In the driving circuits SD1, SD2,..., SDn, the eleventh switch SW11 is driven by the second slope rising signal RAMP2 while the tenth and fifteenth switches SW10 and SW15 are turned on. It works. Accordingly, the current flowing from each Y output line (L _Y1 ,..., L _Yn ) to the ground terminal through the fifteenth, tenth and eleventh switches SW15, SW10 and SW11 is continuously increased.

In the address period PR, a scan signal of the ground voltage V _G is sequentially applied to the Y output lines L _Y1 ,..., L _Yn biased with the fourth voltage V _SCAN . To this end, the twelfth and fourteenth switches SW12 and SW14 are turned on in the scan driving circuits corresponding to the non-scanned Y output lines. In contrast, in the scan driving circuit corresponding to any one Y electrode line to be scanned, the tenth, eleventh, and fifteenth switches SW10, SW11, and SW15 are turned on. Here, since the highest voltage of the second linear rising signal RAMP1 is applied to the ninth switches SW9, the ground voltage V _G is applied to the Y output line.

In the sustain discharge period PS in which the XY-common drive unit 5 acts, the sustain discharge pulse of the second voltage V _S is applied to all the Y output lines L _Y1 ,..., L _Yn . Just before the first switching element SW1 is turned on, charges collected in the common charge / discharge capacitor C _S are transferred through the tuning coil LY and the scan driver 6 to the Y electrode lines Y ₁ ,. ..Y _n ) In addition, when the third switch SW3 is turned off (that is, when the sustain discharge pulse of the second voltage VS _S ends), the second switching device SW1 is turned on to display the plasma display. Unnecessary charges are collected in each display cell of the panel. The fourth switching element (SW4) is, Y electrode lines (Y _1, ... Y _n) and the second off (Off) during the application of the sustain discharge pulse of the voltage (V _S), the X electrode lines ( On during the sustain discharge pulse of the second voltage V _S is applied to X ₁ , ... X _n ). On the other hand, X wiring lines (W _X1, ... _Xn W) immediately before the application of the sustain discharge pulse of the second voltage (V _S), the fifth switch (SW5) is turned on (On) in the common charging and discharging kaepesiteo The charges collected at C _S are applied to the X electrode lines X ₁ ,... X _n through the tuning coil LX. In addition, when the seventh switch SW7 is turned off, that is, when the sustain discharge pulse of the second voltage VS _S ends, the sixth switching element SW6 is turned on to display the plasma display. Unnecessary charges are collected in each discharge cell of the panel. The eighth switching element SW8 is turned off while the sustain discharge pulse of the second voltage V _S is applied to the X connection lines W _{X1 to} W _Xn , and the Y electrode lines ( On during the sustain discharge pulse of the second voltage V _S is applied to Y ₁ , ... Y _n ).

As described above, according to the driving apparatus of the plasma display panel according to the present invention, the Y electrode lines and the X electrode lines are driven by an integrated driver disposed at a position adjacent to the extraction position of the Y electrode lines. As a result, an expensive charge / discharge capacitor used for power recovery in the sustain discharge cycle, and a power supply cable from the power supply unit can be shared, thereby improving economic efficiency and efficiency.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

Claims (2)

The address electrode lines arranged parallel to each other on the front side of the rear substrate, and the Y electrode lines and the X electrode lines on the back side of the front substrate are aligned orthogonally to the address electrode lines, so that the Y electrode lines and the X electrode lines In the driving device of the plasma display panel arranged in the rear of the rear substrate to drive the plasma display panel, which are drawn out to face each other, to drive the Y electrode lines and X electrode lines, An integrated driver disposed at a position adjacent to the extraction positions of the Y electrode lines to drive the Y electrode lines and the X electrode lines; And an X connection unit disposed at a position adjacent to the extraction positions of the X electrode lines to connect the X driving output line from the integrated driver to the X connection lines from the X electrode lines. The method of claim 1, wherein the X drive output line, A drive device for a plasma display panel that is a conductor of a flexible printed circuit.

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