KR100528931B1 - Discharge display apparatus wherein reset function is improved - Google Patents

Abstract

In the discharge display apparatus according to the present invention, the unit frame includes a plurality of subfields, and at least one of the plurality of subfields initially includes a reset period. Here, in the reset period, the potential applied to the electrode lines of the discharge display panel drops in stages. In addition, there are a plurality of capacitors that collect charges from all the discharge cells at the falling points of the applied potential. At least one of the plurality of capacitors is proportional to temperature. In addition, at least one of the plurality of capacitors is inversely proportional to temperature.

Description

Discharge display apparatus wherein reset function is improved}

The present invention relates to a discharge display apparatus, and more particularly, to a discharge display apparatus in which a unit frame includes a plurality of subfields, and a reset period is initially included in at least one of the plurality of subfields. will be.

In a typical discharge display device, for example, a plasma display device, time division driving in which a unit frame includes a plurality of subfields is performed (see US Pat. No. 5,541,618). In each subfield, reset, addressing, and display-sustain cycles are performed sequentially. In the reset period, the charge states of all the discharge cells become uniform. In the addressing period, the set wall voltage is generated in the selected discharge cells. In the sustain-discharge cycle, discharge cells in which a set wall voltage is formed in the addressing cycle cause sustain-discharge.

In the driving cycles of the discharge display device as described above, the charge states of each discharge cell are not uniform at the start of the reset period, and the operation characteristics of each discharge cell are not uniform. Accordingly, there is a problem in that the charge states of each discharge cell are not uniform at the end of the reset period due to the presence of the discharge cells causing overdischarge in the reset period. In this case, erroneous discharges may occur in the addressing and sustaining-discharging cycles, thereby degrading display performance.

It is an object of the present invention to provide a discharge display device in which display performance can be improved as the reset function is improved.

In the discharge display apparatus of the present invention for achieving the above object, the unit frame includes a plurality of subfields, and at least one of the plurality of subfields initially includes a reset period. Here, in the reset period, the potential applied to the electrode lines of the discharge display panel drops in stages. In addition, there are a plurality of capacitors that collect charges from all the discharge cells at the falling points of the applied potential. At least one of the plurality of capacitors is proportional to temperature. In addition, at least one of the plurality of capacitors is inversely proportional to temperature.

According to the discharge display device of the present invention, since the potential applied to the electrode lines of the discharge display panel does not fall continuously in the reset period, but falls in stages, the time for which the same voltage is applied to all the discharge cells periodically exists. do. Accordingly, the discharge cells causing the overdischarge in the reset period can be minimized and the charge states of each discharge cell can be made uniform. In addition, since the composite capacitance of the plurality of capacitors becomes constant with respect to temperature, the charge states of each discharge cell can be made more uniform. Accordingly, erroneous discharge can be prevented in the addressing and sustain-discharge cycles, thereby increasing display performance.

Hereinafter, preferred embodiments according to the present invention will be described in detail.

1 shows the structure of a three-electrode surface discharge plasma display panel 1 as a display panel of a discharge display device according to the present invention. FIG. 2 shows an example of one discharge cell of the plasma display panel 1 of FIG. 1. 1 and 2, between the front and rear glass substrates 10 and 13 of the conventional surface discharge plasma display panel 1, the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm ), dielectric layers 11 and 15, Y electrode lines (Y ₁ , ..., Y _n ), X electrode lines (X ₁ , ..., X _n ), fluorescent layer 16, The partition 17 and the magnesium monoxide (MgO) layer 12 as a protective layer are provided.

The address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is entirely applied in front of the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm . These partitions 17 function to partition the discharge area of each discharge cell and prevent optical cross talk between each discharge cell. The fluorescent layer 16 is formed between the partition walls 17.

The X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ) are the address electrode lines (A _R1 , A _G1 , ..., A _Gm , A _Bm ) is formed in a constant pattern on the back of the front glass substrate 10 to intersect. Each intersection sets a corresponding discharge cell. Each X electrode line (X ₁ , ..., X _n ) and each Y electrode line (Y ₁ , ..., Y _n ) is a transparent electrode line of a transparent conductive material such as indium tin oxide (ITO) or the like (FIG. 2). X _na , Y _na ) and a metal electrode line (X _nb , Y _nb of FIG. 2) for increasing conductivity are formed. The front dielectric layer 11 is formed by applying the entire surface to the rear of the X electrode lines X ₁ ,..., X _n and the Y electrode lines Y ₁ ..., Y _n . A protective layer 12 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

In the driving method basically applied to such a plasma display panel, reset, address, and display-sustain steps are sequentially performed in the unit subfield. In the reset step, the charge states of all the discharge cells become uniform. In the addressing step, a predetermined wall voltage is generated in the selected discharge cells. In the sustain-discharge step, a predetermined alternating voltage is applied to all XY electrode line pairs, so that the discharge cells in which the wall voltage is formed in the addressing step cause sustain-discharge. In this sustain-discharge step, plasma is formed in the discharge space (14 in FIGS. 1 and 2), that is, the gas layer, of the selected discharge cells causing the sustain-discharge, and the fluorescent layer (16 in FIGS. 1 and 2) is formed by the ultraviolet radiation. ) Is excited to generate light.

3 illustrates a method of driving the discharge display panel of FIG. 1 in the discharge display apparatus according to the present invention. Referring to FIG. 3, each unit frame is divided into _eight subfields SF ₁ ,..., SF ₈ to realize time division gray scale display. In addition, each subfield SF ₁ , ..., SF ₈ has a reset period R ₁ , ..., R ₈ , an addressing period A ₁ , ..., A ₈ , and a sustain-discharge period. (S ₁ , ..., S ₈ ).

The discharge conditions of all the discharge cells become uniform in each reset period (R ₁ , ..., R ₈ ) while being adapted to the addressing to be performed in the next step. In this reset period (R ₁ , ..., R ₈ ), the time when the potential applied to the Y electrode lines (Y ₁ , ..., Y _n ) falls in steps (t ₃ to t in FIG. 4). ₄ ) is present.

Each addressing period _{(A 1, ..., A 8} ), the address electrode lines (Fig. 1 A _R1, ..., A _Bm) display data signals are applied at the same time as soon each Y electrode lines in the (Y _1, ..., Y _n ), the scanning pulses are sequentially applied. Accordingly, when high level display data signals are applied while the scan pulse is applied, wall charges are formed by the addressing discharge in the corresponding discharge cell, and wall charges are not formed in the discharge cell that is not.

In each sustain-discharge period S ₁ , ..., S ₈ , all Y electrode lines Y ₁ , ..., Y _n and all X electrode lines X ₁ , ..., X _n The sustain-discharge pulses are alternately applied to generate display discharges in the discharge cells in which wall charges are formed in the corresponding addressing periods A ₁ ,..., A ₈ . Therefore, luminance of the plasma display panel is kept occupied in a unit frame-discharge cycle is proportional to the length _{(S 1, ..., S 8} ). The length of the sustain-discharge periods S ₁ , ..., S ₈ occupied in the unit frame is 255T (T is unit time). Therefore, it can be displayed in 256 gray levels, including the case where it is not displayed once in a unit frame.

Here, in the sustain-discharge period S ₁ of the first subfield SF ₁ , a time 1T corresponding to 2 ⁰ is in the sustain-discharge period S _{2 of} the second subfield SF ₂ . The time 2T corresponding to 2 ¹ is maintained in the sustain-discharge period S ₃ of the third subfield SF ₃ , and the time 4T corresponding to 2 ² is maintained in the fourth subfield SF ₄ . In the discharge period S ₄ , a time 8T corresponding to 2 ³ , and in the sustain-discharge period S ₅ of the fifth subfield SF ₅ , a time 16T corresponding to 2 ⁴ is provided. maintenance of the sub-fields (SF ₆₎ - discharge period (S _6), the time (32T) corresponding to 2 ^5, 7 keep the sub-fields (SF ₇₎ - the discharge period (S ₇₎ corresponding to ²⁶ The time 64T and the time 128T corresponding to 2 ⁷ are set in the sustain-discharge period S ₈ of the eighth subfield SF ₈ , respectively.

Accordingly, if the subfield to be displayed among the eight subfields is appropriately selected, the display of 256 gray levels can be performed including all zero (zero) gray levels that are not displayed in any of the subfields.

4 illustrates signals applied to electrode lines of the plasma display panel 1 of FIG. 1 in the unit sub-field SF of FIG. 3. In FIG. 4, reference numeral S _{AR1 ..ABm} denotes a drive signal applied to each address electrode line (A _R1 , A _G1 ,..., A _Gm , A _{Bm in} FIG. 1), and S _{X1 .. Xn} denotes an X electrode. The driving signal applied to the lines (X ₁ , ... X _{n in} FIG. 1), and S _Y1 , ..., S _Yn are the respective Y electrode lines (Y ₁ , ... Y _{n in} FIG. 1). Indicates a drive signal applied to. FIG. 5A illustrates a wall charge state of each discharge cell at time t ₃ of FIG. 4. 5B illustrates the wall charge state of each discharge cell at time t ₄ of FIG. 4. In Figs. 5A and 5B, the same reference numerals as in Fig. 2 indicate the objects of the same function.

4 to 5B, in the first time t ₁ to t ₂ of the reset period R of the unit sub-field SF, first, the X electrode lines X ₁ ,..., X _n The potential applied to is continuously raised from the ground potential V _G to the second potential V _S. Here, the ground potential V _G is applied to the Y electrode lines Y ₁ ,..., Y _n and the address electrode lines A _R1 ,..., A _Bm . Accordingly, between the X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), and the X electrode lines (X ₁ , ..., X) A weak discharge occurs between _n ) and the address electrode lines A ₁ , ..., A _m , and negative wall charges are formed around the X electrode lines X ₁ , ..., X _n . .

In the second time t ₂ to t ₃ as the wall charge accumulation time, the potential applied to the Y electrode lines Y ₁ ,..., Y _n is changed from the second potential V _S to the second potential V. _It is continuously raised to the first potential V _SET + V _{S which} is higher by the fourth potential V _SET than _S ). Here, the ground potential V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 ,..., A _Bm . Accordingly, a weak discharge occurs between the Y electrode lines (Y ₁ ,..., Y _n ) and the X electrode lines (X ₁ ,..., X _n ), while the Y electrode lines (Y ₁ , A weaker discharge occurs between ..., Y _n ) and the address electrode lines A _R1 , ..., A _Bm . Here, Y electrode lines (Y _1, ..., Y _n) and the address electrode lines _{(A R1, ..., A Bm} ) than the discharge electrode line Y between the (Y _1, ..., Y _n) and the X-electrode lines (X _1, ..., X _n) because the discharge is stronger between is, the X electrode lines (X _1, ..., X _n) of negative polarity wall around Because the charges were formed. Accordingly, many negative wall charges are formed around the Y electrode lines (Y ₁ , ..., Y _n ), and positive wall charges are formed around the X electrode lines (X ₁ , ..., X _n ). Are formed, and less positive wall charges are formed around the address electrode lines A _R1 , ..., A _Bm (see FIG. 5A).

In the third time t ₃ to t ₄ as the wall charge distribution time, in a state where the potential applied to the X electrode lines X ₁ ,..., X _n is maintained at the second potential V _S , The potential applied to the Y electrode lines Y ₁ ,..., Y _n is stepped down from the second potential V _S to the ground potential V _G as the third potential. Here, the ground potential V _G is applied to the address electrode lines A _R1 ,..., A _Bm . Accordingly, due to the weak discharge between the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), the Y electrode lines (Y ₁ ,. Some of the negative wall charges around .., Y _n ) move around the X electrode lines X ₁ ,..., X _n . Accordingly, the wall electric-potential of the X electrode lines X ₁ , ..., X _n is lower than the wall potential of the address electrode lines A _R1 , ..., A _Bm and the Y electrode Higher than the wall potential of the lines Y ₁ , ..., Y _n (see FIG. 5B). As a result, the addressing voltage V _A -V _G required for the counter discharge between the selected address electrode lines and the Y electrode line in the following addressing period A may be lowered.

In the third time (t ₃ to t ₄ ) as the wall charge distribution time, the potential applied to the Y electrode lines (Y ₁ ,..., Y _n ) does not fall continuously but falls in stages. There is a period of time during which the same voltage is applied to the discharge cells. Accordingly, the discharge cells causing overdischarge at the third time (t ₃ to t ₄ ) as the wall charge distribution time can be minimized while the charge states of each discharge cell can be made uniform. As a result, erroneous discharge is prevented in the addressing period A and the sustaining-discharging period S, thereby increasing display performance.

In the following addressing period A, the display data signal is applied to the address electrode lines, and the Y electrode lines Y ₁ ,... _{Biased to} the fifth potential V _SCAN lower than the second potential V _S. , Y _n ), as the scan signals of the ground potential V _G are sequentially applied, smooth addressing may be performed. The display data signals applied to each of the address electrode lines A _R1 , ..., A _Bm become the positive addressing potential V _A when the discharge cell is selected and the ground potential V _G otherwise. . Accordingly, when the display data signal of the positive addressing potential V _A is applied while the scan pulse of the ground potential V _G is applied, wall charges are formed by the addressing discharge in the corresponding discharge cell. Wall charges do not form. Here, for a more accurate and efficient addressing discharge, the second potential V _S is maintained at the X electrode lines X ₁ ,... X _n .

In the subsequent sustain-discharge period _S , the maintenance of the second potential V _{S at} all the Y electrode lines Y ₁ , ... Y _n and the X electrode lines X ₁ , ... X _n . -The discharge pulses are applied alternately, causing sustain-discharge in the discharge cells in which wall charges are formed in the corresponding addressing period A. FIG.

Referring to FIG. 6, a plasma display apparatus as a discharge display apparatus according to the present invention includes the plasma display panel 1, an image processor 66, a controller 62, an address driver 63, an X driver 64, and a Y. The drive unit 65 is included. The image processing unit 66 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The controller 62 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 66. The address driver 63 generates a display data signal according to the address signal S _A among the driving control signals S _A , S _Y , and S _X from the controller 62, and addresses the generated display data signal. Applied to the electrode lines. The X driver 64 is applied to the X electrode lines according to the X drive control signal S _X among the drive control signals S _A , S _Y , and S _X from the controller 62. The Y driver 65 applies the Y electrode lines according to the Y drive control signal S _Y among the drive control signals S _A , S _Y , and S _X from the controller 62.

FIG. 7 shows a scan driving circuit AC and a switching output circuit SIC of the Y driver 65 of FIG. 6. 4 and 7, the Y driver 65 includes a switching output circuit SIC, a reset / hold circuit RSC, and a scan drive circuit AC. The scan driving circuit AC includes the capacitor C _SP , the upper scan circuits D _U and S _SCH , the lower scan circuit S _SCL , and the first switching circuit S _SSU1 , S _SSU2 ), and a second switching circuit S _SSL .

In the switching output circuit SIC, the upper transistors YU1, ..., YUn and the lower transistors YL1, ..., YLn are arranged so that the common output lines of each upper transistor and each lower transistor are respectively. Are connected to correspond to the Y electrode lines (Y ₁ , ..., Y _n ). All transistors YU1, ..., YUn, YL1, ..., YLn of the switching output circuit SIC are field effect transistors. An internal diode is formed in each of the field effect transistors YU1, ..., YUn, YL1, ..., YLn. The anode of this internal diode is connected to the source of the field effect transistor. The cathode of the internal diode is connected to the drain of the field effect transistor. The source of all the top transistors YU1, ..., YUn of the switching output circuit SIC, and the drain of all the bottom transistors YL1, ..., YLn are each Y electrode line Y ₁ ,. .., Y _n ).

The reset / hold circuit RSC outputs drive signals O _RS necessary in the reset and sustain-discharge stages.

A capacitor C _SP is connected between the upper scan circuit D _U , S _SCH and the lower scan circuit S _SCL . Kaepesiteo (C _SP) potential by the charging of the upper transistor of the output switching circuit (SIC) via the field effect transistor (S _SCH) of the upper scanning circuit (D _U, S _SCH) of (YU1, ..., YUn) Is applied to the common power line.

The upper scanning circuits D _U and S _SCH are connected to the common power line of all the upper transistors YU1,..., YUn of the switching output circuit SIC, so that the Y electrode lines are not scanned in the addressing step. The scanning bias potential V _SCAN is applied to the. A field effect transistor (S _SCH) is, all the top transistors in the output switching circuit (SIC) of the common power supply line for injection of bias potential (YU1, ..., YUn) of the upper scanning circuit (D _U, S _SCH) ( V _SCAN ) terminal is connected or disconnected. An internal diode is formed in the field effect transistor S _SCH . The anode of this internal diode is connected to the source of the field effect transistor S _SCH , and the cathode of the internal diode is connected to the drain of the field effect transistor S _SCH . The source of the field effect transistor S _SCH is connected to the common power supply line of all the upper transistors YU1,..., YUn of the switching output circuit SIC. A diode D _U as a one-way current control element is connected between the drain of the field effect transistor S _SCH and the terminal of the scanning bias potential V _SCAN . The cathode of this diode D _U , one end of the capacitor C _SP , and the drain of the field effect transistor S _SCH are connected in common.

The lower scanning circuit S _SCL is connected to the common power line of all the lower transistors YL1,... YLn of the switching output circuit SIC, so that the ground potential V is connected to the Y electrode lines scanned in the addressing step. _G ) is applied. More specifically, the field effect transistor S _SCL is connected between the other end of the capacitor C _SP and the terminal of the ground potential V _G. An internal diode is formed in this field effect transistor S _SCL . The anode of the internal diode is connected to the source of the field effect transistor S _SCL , and the cathode of the internal diode is connected to the drain of the field effect transistor S _SCL . The source of the field effect transistor S _SCL is connected to the terminal of the ground potential V _G , and the drain of the field effect transistor S _SCL is connected to the other end of the capacitor C _SP .

First switching circuit S _SSU1 , S _SSU2 connects or disconnects the common power line of all upper transistors YU1,..., And UnUn of the switching output circuit SIC with the output terminal of the reset / hold circuit RSC. First switching circuit S _SSU1 , S _SSU2 is the first and second transistors connected between the common power line of all the upper transistors YU1,..., And Un of the switching output circuit SIC and the output terminal of the reset / sustain circuit RCS. S _SSU1 , S _SSU2 ). First and second transistors S _SSU1 which are field effect transistors, Internal diodes are formed in each of S _SSU2 ). The anode of each of these internal diodes is provided with the first and second field effect transistors S _SSU1,. S _SSU2 ) is connected to each source. The cathode of each of the internal diodes may include the first and second field effect transistors S _SSU1,. S _SSU2 ) is connected to each drain. The drain of the first field effect transistor S _SSU1 is connected to the output terminal of the reset / sustain circuit _RCS . The drain of the second field effect transistor S _SSU2 is connected to the common power line of all the upper transistors YU1,..., YUn of the switching output circuit SIC. The source of the first field effect transistor (S _SSU1) is connected to the source of the second field effect transistor (S _SSU2). Meanwhile, the first and second field effect transistors S _SSU1 , In the addressing step in which S _SSU2 is turned off, the internal diode of the first field effect transistor S _SSU1 has a scan voltage V _SC of all the upper transistors YU1,..., And YUn. no longer applied to the common power supply line, and the internal diode of the second field effect transistor (s _SSU2) is injection bias voltage (V _{SC_H)} is applied to the common power supply line of all the lower transistor (YL1, ..., YLn) Do not become. Therefore, the first switching circuit S _SSU1 , S _SSU2 has two transistors S _SSU1 , S _SSU2 ) is required.

The second switching circuit S _SSL connects or disconnects the common power line of all the lower transistors YL1,..., YLn of the switching output circuit SIC to the output terminal of the reset / hold circuit RSC. Accordingly, the drive signals O _RS from the reset / hold circuit RSC are connected to the Y electrode lines through the internal diodes of all the lower transistors YL1,..., YLn of the switching output circuit SIC. Y ₁ , ..., Y _n ) may be controlled. For example, a field effect transistor (S _SSL) is turned off (turn off) mixture maintained that - in the discharge period (MS4 in Fig. 5), the field-effect transistor (S _SSL) is from a reset / hold circuit (RSC) Blocks the drive signals O _RS .

The second switching circuit S _SSL is a field effect transistor connected between the common power line of all the lower transistors YL1,..., YLn of the switching output circuit SIC and the output terminal of the reset / hold circuit RSC. (S _SSL ) The field-effect transistor (S _SSL) is formed with an internal diode, is connected to the source of enoic lifting field effect transistor (S _SSL) of the internal diode, the cathode of the internal diode is connected to the drain of the field effect transistor (S _SSL) do. The source of the field effect transistor S _SSL is connected to the common power line of all the lower transistors YL1, ..., YLn of the switching output circuit SIC, and the drain thereof is an output terminal of the reset / hold circuit RSC. Is connected to.

Referring to FIGS. 4 and 7, the operation process of the Y driver of FIG. 7 will be described.

A reset period (R) and hold-in discharge period (S), the field-effect transistor of the field effect transistor (S _SCL), the upper scanning circuit (D _U, S _SCH) of the lower scanning circuit (S _SCL) (S _SCH) , And the first switching circuit S _SSU1 , The field effect transistor of _SSU2 S) (S _SSU1, S _SSU2 is turned off. In addition, the field effect transistor S _{SSL of} the second switching circuit S _SSL is turned on. Accordingly, the drive signals O _RS from the reset / hold circuit RSC are applied to the common power line of all the lower transistors YL1,..., YLn of the switching output circuit SIC. In addition, all lower transistors YL1, ..., YLn of the switching output circuit SIC are turned on and all upper transistors YU1, ..., YUn are turned off. do. Accordingly, the driving signals O _RS from the reset / sustain circuit RCS are transferred through all the lower transistors YL1,..., YLn to all Y electrode lines Y ₁ ,..., Y _n. Is applied.

In the addressing period (A), the upper scanning circuit (D _U, S _SCH) of a field effect transistor (S _SCH), the lower scanning circuit (S _SCL) field effect transistor (S _SCL), and a second switching circuit (S in a field effect transistor (S _SSL) for _SSL) is turned on (turn on). In addition, the first switching circuit S _SSU1 , The field effect transistor of _SSU2 S) (S _SSU1, S _SSU2 is turned off. Accordingly, the scanning bias potential V _SCAN due to the charging of the capacitor C _SP passes through the upper transistors YU1,..., Of the switching output circuit SIC through the upper scanning circuits D _U and S _SCH . YUn) is applied to the common power supply line. In addition, the ground potential V _G as a scanning potential is applied to the lower transistors YL1,..., YLn of the switching output circuit SIC through the lower scanning circuit S _SCL and the second switching circuit S _SSL . Is approved. Here, the lower transistor connected to the Y electrode line to be scanned is turned on and the upper transistor is turned off. In addition, the bottom transistors connected to all remaining Y electrode lines that are not to be scanned are turned off and the top transistors are turned on. Accordingly, the ground potential V _G as a scanning potential is applied to one Y electrode line to be scanned, and the scanning bias potential V _SCAN is applied to all the other Y electrode lines that are not to be scanned.

In the addressing period A, the display data signal is applied to the address electrode lines A _R1 , ..., A _Bm when the ground potential V _G as the scanning potential is applied to one Y electrode line to be scanned. At the time point at which the display data signal is applied to the address electrode lines A _R1 ,..., And A _Bm , and the ground potential V _G as the scanning potential is applied to the Y electrode line to be scanned. The current paths at the end point are as follows.

First, when a ground potential V _G as a scanning potential is applied to one Y electrode line to be scanned, one lower transistor of the switching output circuit SIC from discharge cells (electrical capacitors) connected to the one Y electrode line to be scanned. And a current flows through the second switching circuit S _SSL to the lower scanning circuit S _SCL .

Second, when the display data signal is applied to the address electrode lines A _R1 ,..., A _Bm , the discharge current flows from the address electrode lines to which the selection voltage is applied to the Y electrode line being scanned. , the non-injection balance of Y electrode lines, the upper transistor of a switching output circuit (SIC), a field effect transistor (s _SCH), the lower scanning through the kaepesiteo (C _SP) of the upper scanning circuit (D _U, s _SCH) Current flows through the circuit S _SCL .

Third, when the application of the display data signal to the address electrode lines A _R1 , ..., A _Bm is terminated, the upper scan circuits D _U , S from the capacitor C _SP of the scan drive circuit AC. _SCH) of a field effect transistor (s _SCH), the output switching circuit (SIC) of the upper transistor, through the Y-electrode line address electrode lines (a _R1, a ..., a _Bm), the current flows into.

Fourth, at the time when the application of the ground potential V _G as the scan potential to the one Y electrode line to be scanned is terminated, the upper scan circuits D _U and S _SCH from the capacitor C _SP of the scan drive circuit AC. Current flows to the discharge cells (electric capacitors) through the field effect transistor S _SCH , the upper transistors of the switching output circuit SIC, and the Y electrode lines.

FIG. 8 shows the reset / hold circuit RSC of FIG. 7. FIG. 9 shows the internal circuit of the falling circuit section 81 of FIG. In FIG. 8, the third to sixth transistors ST3,..., ST6, the falling circuit unit 81, and the eighth transistor ST8 are applied to the Y electrode lines in the reset period (R of FIG. 4). Generate the drive signal O _RS . In addition, the power regeneration capacitor C _SY , the first through fifth transistors ST1,..., ST5, the tuning coil L _Y , and the eighth transistor ST8 have a sustain-discharge cycle (FIG. 5). In S), a driving signal O _RS to be applied to the Y electrode lines is generated. The eighth transistor ST8 causes the output driving signal O _RS to be in a floating state in the addressing period (A of FIG. 4). An operation of the reset / hold circuit RSC of FIG. 7 will be described with reference to FIGS. 4, 8, and 9 as follows.

In the reset period R, the _second potential V whose potential applied to the X electrode lines X ₁ ,..., X _n is equal to the sustain-discharge potential V _S from the ground potential V _{G. Only} the fourth, fifth, and eighth transistors ST4, ST5, and ST8 are turned on at a time t ₁ to t _{2 that} is continuously raised to _S ). Accordingly, the ground voltage V _G is applied to all of the Y electrode lines Y ₁ ,..., Y _n .

In the wall charge formation time t ₂ to t ₃ , only the third, sixth, and eighth transistors ST3, ST6, and ST8 are turned on, and the drain of the sixth transistor ST6 is turned on. The third voltage V _SET is applied. Here, since the control potential that is continuously raised to the gate of the sixth transistor ST6 is applied, the channel resistance value of the sixth transistor ST6 is continuously reduced. In addition, since the second potential V _S is applied to the source of the third transistor ST3, due to the action of a capacitor connected between the source of the third transistor ST3 and the drain of the sixth transistor ST6, the second potential V _S is applied. A potential that is continuously raised from the second potential V _S to the highest potential V _SET + V _S is applied to the drain of the six transistor ST6. Accordingly, a potential that is continuously raised from the second potential V _S to the highest potential V _SET + V _S is applied to all of the Y electrode lines Y ₁ ,..., Y _n . Here, the ground potential V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 ,..., A _Bm . Accordingly, a weak discharge occurs between the Y electrode lines (Y ₁ ,..., Y _n ) and the X electrode lines (X ₁ ,..., X _n ), while the Y electrode lines (Y ₁ , A weaker discharge occurs between ..., Y _n ) and the address electrode lines A _R1 , ..., A _Bm . Here, Y electrode lines (Y _1, ..., Y _n) and the address electrode lines _{(A R1, ..., A Bm} ) than the discharge electrode line Y between the (Y _1, ..., Y _n) and the X-electrode lines (X _1, ..., X _n) because the discharge is stronger between is, the X electrode lines (X _1, ..., X _n) of negative polarity wall around Because the charges were formed. Accordingly, many negative wall charges are formed around the Y electrode lines (Y ₁ , ..., Y _n ), and positive wall charges are formed around the X electrode lines (X ₁ , ..., X _n ). Are formed, and less positive wall charges are formed around the address electrode lines A _R1 , ..., A _Bm (see FIG. 5A).

In the wall charge distribution time t ₃ to t ₄ , initially, only the third, fifth, and eighth transistors ST3, ST5, and ST8 are turned on so that the second potential V _S is turned on. Is applied to all Y electrode lines (Y ₁ , ..., Y _n ).

Next, the falling circuit unit 81 operates while only the fifth and eighth transistors ST5 and ST8 are turned on, so that the Y electrode lines Y ₁ ,..., Y _n The driving signal (O _RS ) to be applied to) is stepped down from the second potential (V _S ) to the ground potential (V _G ) as the third potential. That is, the potential fall time and the coin hold time alternately pass. Here, the ground potential V _G is applied to the address electrode lines A _R1 ,..., A _Bm . Accordingly, the wall electric-potential of the X electrode lines X ₁ , ..., X _n is lower than the wall potential of the address electrode lines A _R1 , ..., A _Bm and the Y electrode Higher than the wall potential of the lines Y ₁ , ..., Y _n (see FIG. 5B). As a result, the addressing voltage V _A -V _G required for the counter discharge between the selected address electrode lines and the Y electrode line in the following addressing period A may be lowered.

The following describes the potential lowering operation and the coin operation.

As the ninetieth transistor ST91 of the falling circuit unit 81 is turned on, charges of the discharge cells are transferred from the Y electrode lines Y ₁ ,..., Y _n to the eighth transistor ST8, The first and second capacitors C _DP and C _DN are charged through the fifth transistor ST5 and the 91st transistor ST91 of the falling circuit unit 81. As a result, the source potential of the ninety-ninth transistor ST91 increases. When the source potential of the 91st transistor ST91 rises, the 91st transistor ST91 is automatically turned off.

Next, when the 91st transistor ST91 is turned off, the output potential S _FA of the gate signal generator 91 is controlled to be lower than the source potential of the 91st transistor ST91. The charges charged in the first and second capacitors C _DP and C _DN are discharged to the gate signal generator 91 through the discharge diode D _D. When the discharge is completed, the gate signal generator 91 turns on the 91st transistor ST91 and the above steps are repeatedly performed.

In summary, the turn-on time of the 91st transistor ST91 becomes the potential fall time, and the turn-off time of the 91st transistor ST91 becomes the coincidence holding time. That is, in the wall charge distribution time (t ₃ ~ t _4), so that the potential applied to the Y electrode lines (Y _1, ..., Y _n) without continuous fall in a stepwise lowered, all the discharge cells There is a period of time during which the same voltage is applied. Accordingly, the discharge cells causing overdischarge at the wall charge distribution times t ₃ to t ₄ may be minimized and the charge states of the respective discharge cells may be uniform. As a result, erroneous discharge is prevented in the addressing period A and the sustaining-discharging period S, thereby increasing display performance. In FIG. 9 the resistors R _G1 , R _G2 , R _D , R _PD set the potential drop rate, and the two diodes D _DG , D _D remove the noise.

Here, if the combined capacitance of the first capacitor C _DP and the second capacitor C _DN is changed, the accuracy of the control of the gate signal generator 91 will be reduced. However, the combined capacitance of the first capacitor C _DP and the second capacitor C _DN connected in parallel with each other does not change with temperature. This is because the capacitance of the first capacitor C _DP is proportional to the temperature, and the capacitance of the second capacitor C _DN is inversely proportional to the temperature. Accordingly, the charge states of each discharge cell can be made more uniform. Accordingly, erroneous discharge is prevented in the addressing period A and the sustain-discharge period S, so that display performance can be higher.

In the addressing period A, all the transistors of the reset / hold circuit RSC are turned off, so that the output of the reset / hold circuit RSC is electrically floating.

In the unit pulse applied to all the Y electrode lines in the sustain-discharge period S, the second and fifth at the time of falling from the second potential V _S as the display-hold potential to the ground potential V _G. , And only the eighth transistors ST2, ST5, ST8 are turned on. Accordingly, charges that remain unnecessarily in the display cells (electrical capacitors) are collected in the power regenerative capacitor C _SY . The charges thus collected are applied and recycled to all or selected Y electrode lines at a time rising from the ground potential V _G to the second potential V _S. This will be described step by step as follows.

In the unit pulse applied to all the Y electrode lines in the sustain-discharge period S, the first, fifth and eighth transistors at a time rising from the ground potential V _G to the second potential V _S. Only ST2, ST5, ST8 are turned on. Accordingly, the charges collected in the power regenerative capacitor C _SY are applied to all or selected Y electrode lines Y ₁ ,..., Y _n .

Next, only the third, fifth, and eighth transistors ST3, ST5, ST8 are turned on so that the second potential V _S as the discharge-hold potential is all or selected Y electrode lines. Is applied to.

Next, only the second, fifth, and eighth transistors ST2, ST5, ST8 are turned on at the time of falling from the second potential V _S to the ground potential V _G. Accordingly, the charges that remain unnecessarily in the discharge cells (electrical capacitors) are collected in the power regeneration capacitor C _SY .

Finally, only the fourth, fifth, and eighth transistors ST4, ST5, ST8 are turned on so that the ground potential V _G is applied to all Y electrode lines.

As described above, according to the discharge display apparatus according to the present invention, since the potential applied to the electrode lines of the discharge display panel does not fall continuously but gradually falls in the reset period, the same voltage is applied to all the discharge cells. Time exists periodically. Accordingly, the discharge cells causing overdischarge in the reset period can be minimized and the charge states of each discharge cell can be made uniform. In addition, since the composite capacitance of the plurality of capacitors becomes constant with respect to temperature, the charge states of each discharge cell can be made more uniform. Accordingly, erroneous discharge can be prevented in the addressing and sustain-discharge cycles, thereby increasing display performance.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

1 is an internal perspective view showing the structure of a three-electrode surface discharge plasma display panel as a display panel of the discharge display device according to the present invention.

FIG. 2 is a cross-sectional view illustrating an example of one discharge cell of the plasma display panel of FIG. 1.

3 is a timing diagram illustrating a method of driving the discharge display panel of FIG. 1 in the discharge display apparatus according to the present invention.

FIG. 4 is a timing diagram illustrating driving signals applied to respective electrode lines of the discharge display panel of FIG. 1 in one subfield of FIG. 3.

5A is a cross-sectional view illustrating a wall charge state of each discharge cell at time t ₃ of FIG. 4.

5B is a cross-sectional view illustrating a wall charge state of each discharge cell at time t ₄ of FIG. 4.

Figure 6 is a block diagram showing an overall discharge display device according to the present invention.

FIG. 7 illustrates a scan driving circuit and a switching output circuit of the Y driver of FIG. 6.

FIG. 8 is a diagram illustrating the reset / hold circuit of FIG. 7.

9 is a circuit diagram illustrating a falling circuit of FIG. 8.

<Explanation of symbols for main parts of the drawings>

1 ... plasma display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 protective layer,

13 ... back glass substrate, 14 ... discharge space,

16 fluorescent layers, 17 bulkheads,

X ₁ , ..., X _n ... X electrode lines, Y ₁ , ..., Y _n ... Y electrode lines,

A _R1 , ..., A _Bm ... address electrode lines, X _na , Y _na ... transparent electrode lines,

X _nb , Y _nb ... metal electrode lines, SF ₁ , ... SF ₅ ... sub-field,

S _Y1 , ..., S _Yn ... Y electrode drive signals, 62 ... logical control,

S _X1 , ..., S _Xn ... X electrode drive signals, 63 .. address driver,

S _AR1 .. _ABm ... display data signals, 64 ... X driver,

65 ... Y drive unit, 66 ... image processing unit,

RSC ... reset / hold circuit, AC ... scan drive circuit,

SIC ... switching output circuit, D _U , S _SCH ...

S _SCL ... lower scanning circuit, S _SSU1 , S _SSU2 ... first switching circuit,

S _SSL ... second switching circuit.

Claims (13)

A discharge display apparatus in which a unit frame includes a plurality of subfields, and a reset period is initially included in at least one of the plurality of subfields. In the reset period, the potential applied to the electrode lines of the discharge display panel drops in stages, There are a plurality of capacitors that collect charges from all the discharge cells at the falling points of the applied potential, At least one of the plurality of capacitors is proportional to temperature, And at least one of the plurality of capacitors is inversely proportional to temperature. The method of claim 1, And a switch for periodically connecting and disconnecting the plurality of capacitors and the discharge cells. The method of claim 2, Discharge display device wherein the switch is a transistor. The method of claim 1, And a plurality of capacitors connected in parallel with each other. The method of claim 1, wherein the discharge display panel, X electrode lines, Y electrode lines formed parallel to the X electrode lines and XY electrode line pairs, and Including address electrode lines arranged in a direction crossing the XY electrode line pairs, And discharge cells are set in intersection regions of the XY electrode line pairs and the address electrode lines. The method of claim 5, wherein the drive device of the discharge display panel, An image processor converting an external analog image signal into a digital signal to generate an internal image signal; A controller configured to generate driving control signals according to an internal image signal from the image processor; An address driver for generating a display data signal according to the address signal from the controller and applying the generated display data signal to address electrode lines; An X driver for driving X electrode lines according to an X driving control signal from the controller; And And a Y driver for driving Y electrode lines according to a Y driving control signal from the controller. The method of claim 6, wherein in the reset period, A discharge display device in which the charge states of all discharge cells are uniform. The method of claim 7, wherein each of the plurality of subfields, The reset cycle, An addressing period for generating a set wall voltage in the selected discharge cells, and And a sustain-discharge cycle in which sustain-discharge occurs in the discharge cells in which the set wall voltage is formed. The method of claim 8, wherein the Y drive unit, A switching output circuit, in which upper and lower transistors are arranged so that a common output line of each upper transistor and each lower transistor is connected to correspond to the respective Y electrode lines; A reset / hold circuit for outputting drive signals required in the reset and sustain-discharge periods; An upper scanning circuit connected to a common power supply line of all upper transistors of the switching output circuit and applying a scanning bias voltage to Y electrode lines not scanned in the addressing period; A lower scan circuit connected to a common power supply line of all lower transistors of the switching output circuit and applying a scan voltage to the Y electrode lines scanned in the addressing step; A capacitor coupled between the upper scan circuit and the lower scan circuit; A first switching circuit connecting or disconnecting a common power supply line of all upper transistors of the switching output circuit to an output terminal of the reset / hold circuit; And And a second switching circuit connecting or disconnecting a common power line of all lower transistors of the switching output circuit to an output terminal of the reset / hold circuit. The method of claim 9, And the reset / hold circuit includes the plurality of capacitors. 11. The method of claim 10, wherein And a switch for periodically connecting and disconnecting the plurality of capacitors and the discharge cells. The method of claim 11, Discharge display device wherein the switch is a transistor. The method of claim 10, And a plurality of capacitors connected in parallel with each other.