JPH0990900A - Control method for plasma display panel driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a PDP driving circuit by integrating a scanning driver and a deleting driver of a driving circuit of an AC discharge type plasma display panel(PDP). SOLUTION: In a control method for a driving circuit driving a PDP 15, signals SBL, SDA, SCL, SST for writing-discharge, signals EBL, EDA, ECL, EST for holding-discharge-deletion are switched with a writing-discharge period and a holding-discharge period by a voltage selector 24, and inputted to a scanning driver 19. The scanning driver 19 generates a scanning pulse for writing- discharge and a holding-discharge-stop pulse switching for each period, and gives it to a scanning electrode of the PDP 15 through a mixer 25. The holding- discharge-stop pulse is a pulse given to each scanning electrode to eliminate phenomenon in which brightness is varied by variation of the number of display cells connected to one scanning electrode, a circuit scale of the PDP driving circuit is reduced by generating this holding-discharge-stop pulse with the scanning driver 19.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for controlling a plasma display panel drive circuit, and more particularly to a method for controlling an AC discharge memory type plasma display panel drive circuit.

[0002]

2. Description of the Related Art Generally, a plasma display panel (hereinafter abbreviated as PDP) has a thin structure, no flicker, a large display contrast ratio, a relatively large screen, and a fast response speed. In addition, since it is a self-luminous type, it has a number of advantages such as being capable of multicolor light emission by using a phosphor. Therefore, in recent years,
It is becoming widely used in the fields of computer-related display devices and color image displays.

The PDP has an AC discharge type in which an electrode is covered with a dielectric material to operate in an AC discharge state and a DC discharge type in which the electrode is exposed to a discharge space to operate in a DC discharge state, depending on its operation method. There is. Furthermore, in the AC discharge type,
As a driving method, there are a memory operation type that uses the memory function of the discharge cell and a refresh operation type that does not use the memory function. The brightness of the PDP is proportional to the number of discharges, that is, the number of repetitions of the pulse voltage. Since the refresh type decreases the brightness as the display capacity increases, the PDP having a small display capacity is mainly used.
Used for

FIG. 8 is a sectional view illustrating the structure of a display cell of a general AC discharge memory type color PDP. PD
P has a first insulating substrate 1 and a second insulating substrate 2 made of glass, which are arranged on the back surface and the front surface, respectively. The transparent scan electrode 3 and the sustain electrode 4 are formed on the second insulating substrate 2, and the scan electrode 3 and the sustain electrode 4 are formed to reduce the electrode resistance value.
And trace electrodes 5 and 6 are formed so as to overlap with. Data electrodes 7 are formed on the first insulating substrate 1 in a direction orthogonal to the scan electrodes 3 and the sustain electrodes 4 and opposite to each other. On the second insulating substrate 2, the scan electrodes 3
Further, the dielectric 12 is formed so as to cover the sustain electrodes 4, and the protective layer 13 made of magnesium oxide or the like for protecting the dielectric 12 from discharge is formed thereon. A dielectric 14 covering the data electrodes 7 is formed on the first insulating substrate 1, and a phosphor 11 for converting ultraviolet rays generated by the discharge of the discharge gas into visible light 10 is applied thereon. .

A discharge gas space 8 is provided between the first insulating substrate 1 and the second insulating substrate 2, and the discharge gas space 8 contains helium, neon and xenon or a mixed gas thereof. Is filled with a discharge gas. The discharge gas space 8 is maintained by a grid-shaped partition 9 that separates the first and second insulating substrates 1 and 2 from each other, and the partition 9 further partitions the discharge gas space 8 into each display cell.

The discharge operation of the selected display cell will be described below. First, a pulse voltage exceeding the discharge threshold value, that is, a data pulse is applied between the scan electrode 3 and the data electrode 7 to start discharge. As a result, data
Depending on the polarity of the pulse, positive and negative electric charges are applied to both dielectrics 1
It is attracted and deposited on the surfaces of 2 and 14 to form positive and negative wall charges. The equivalent internal voltage, or wall voltage, due to this wall charge deposition is of opposite polarity to the voltage of the data pulse. Therefore, as the discharge grows, the effective voltage inside the cell drops, and even if the voltage of the data pulse holds a constant value, the discharge cannot be maintained and eventually stops.

After that, a sustain pulse, which is a pulse voltage having the same polarity as the wall voltage, is applied between the scan electrode 3 and the sustain electrode 4 which are adjacent to each other. Since the sustain pulse is superimposed on the wall voltage, the sustain pulse can be discharged exceeding the discharge threshold value even if the voltage amplitude of the sustain pulse is low. Therefore, the discharge can be maintained by continuing to apply the sustain pulse between the scan electrode 3 and the sustain electrode 4. This function is the memory function described above. Further, the scan electrode 3 or the sustain electrode 4 has an erase pulse having an amplitude and a pulse width for neutralizing the wall voltage, for example, a low voltage pulse having a large pulse width or an amplitude of a sustain pulse having a short pulse width. The sustain discharge can be stopped by applying the voltage pulse.

By the way, in the AC discharge memory type PDP,
In the case of arranging a large number of display cells as described above to display various images, if the number of display cells that select light emission on one electrode changes, the same number of sustain discharge pulses are applied. It is known that the brightness is different. Therefore, conventionally, means for adjusting the number of sustain discharges for each electrode according to the number of light emitting cells has been adopted.

As one example of the above adjustment, there is a method of inserting a sustain erase pulse between sustain pulse trains and stopping the sustain discharge after the erase pulse. A conventional drive circuit that realizes this will be described below.

FIG. 9 is a block diagram showing the structure of the above-mentioned conventional drive circuit, for example, showing a system for driving a dot matrix display PDP having the electrode arrangement shown in FIG. In FIG. 10, the dot matrix display PDP 15 includes scan electrodes S _c1 , S _c2 , ..., Which are arranged in parallel with each other on a second insulating substrate and constitute row electrodes.
A pair of S _cj and sustain electrodes S _u1 , S _u2 , ..., S _uj , and
Data electrodes D ₁ , D ₂ , ..., D _k arranged orthogonally (intersecting) to these row electrodes are provided on an insulating substrate. Each display cell 16 is arranged at the intersection of the row electrode and the column electrode.
In the figure, paying attention to the structure of the electrode arrangement of the PDP, the display cells 16 are block-displayed as a matrix of j × k.

The driving circuit of FIG. 9 has a high voltage pulse generator 17 for generating a pulse for commonly driving the sustain electrodes.
A high voltage pulse generator 18 for generating a pulse for commonly driving the scan electrodes, a scan driver 19 for sequentially applying a scan pulse, an erase driver 20 for sequentially applying a sustain erase pulse, and a high voltage pulse A mixer 21 that mixes the outputs of the generator 18, the scan driver 19, and the erase driver 20 and supplies the mixed output to each scan electrode to drive the scan electrode, and data drivers 22 and 23 that individually drive the data electrodes.

FIG. 11 shows the scan driver 19 shown in FIG.
2 is a block section showing the internal circuit of FIG. Scan driver 19
Is a shift register 31, a latch 32, a high voltage switching circuit 33, AND gates 34 _i , ...
5 _j . In each signal line shown in the figure, the signal line LBL is a scan pulse signal input line that determines the basic output waveform of the high-voltage switching circuit, the signal line LDA is a data signal input line to the shift register, and the signal line LCL is shifted. The clock signal input line of the register and the signal line LST indicate the strobe signal input line of the latch, respectively.

The erase driver 20 shown in FIG. 9 has the same structure as the scan driver 19 shown in FIG. 11, and includes a shift register, a latch, a high voltage switching circuit and an AN.
It consists of a D-gate.

FIG. 12 shows an example of a drive voltage waveform obtained by using the drive circuit of FIG. FIG 12, sustain electrodes S _u1, S _u2, · · ·, a common sustain electrode driving waveform W _u to be applied to S _uj, respective scanning electrodes S _c1, S _c2, · · ·, respectively applied to the S _cj Scan electrode drive waveforms W _s1 , W s ₂ , ..., W
_sj and the data electrode drive waveform Wd applied to the data electrode D _i (1 ≦ i ≦ k) are shown. One driving cycle includes a preliminary discharge period A, an address discharge period B, and a sustain discharge period C.
And is repeated, and these are repeated to obtain a desired video display.

In the preliminary discharge period A, the preliminary discharge pulse P _p
Then, a pre-discharge erasing pulse P _pe subsequent thereto is applied to each sustain electrode and scan electrode to pre-discharge all cells at the same time to erase them. In the address discharge period B, the scan electrodes S _c1 , S
_c2, · · ·, to the S _cj, it is successively with independent timing advance by applying a scan pulse P _w, period for line-sequentially writing discharge. Display data is selectively written to each cell at the intersection with the data electrode in accordance with the timing of the scanning pulse P _w . Here, when writing data to a desired display cell, the data pulse P _d is applied to the corresponding data electrode,
When not writing, the data pulse P _d is not applied to the corresponding data electrode.

In the sustain discharge period C, sustain discharge pulses P _s and P _u are applied to each sustain electrode and scan electrode in common, and the display cells in which the address discharge is performed in the address discharge period B are:
This is a period in which the sustain discharge is performed to emit light in order to obtain desired brightness. When the sustain erasing pulse P _e is applied during the sustain discharge period, the wall charges in the display cell are neutralized and the subsequent sustain discharge is stopped. Thereby, the brightness adjustment is performed for each scan electrode.

FIG. 13 is a timing chart showing control signal waveforms for generating the above-mentioned drive pulses, particularly the scan pulse P _w and the sustain erasing pulse P _e . In the figure, signals SBL, SDA, SCL, and SST are signals for the scan driver, and indicate a scan pulse signal, a data signal, a clock signal, and a strobe signal, respectively.

The clock signal SCL determines the period of the scan pulse P _w and shifts the data signal SDA in the shift register. The strobe signal SST sequentially shifts the data in the shift register 31 to the latch 32 in time shift with the shift operation of the shift register 31. As a result, the high-voltage switching circuits 33 corresponding to the scan electrodes and the one-to-one correspondence are sequentially selected, and the scan pulse obtained by voltage-amplifying the scan pulse signal SBL is output to each scan electrode.

Further, the signals EBL, EDA, ECL, and EST are signals for the erase driver and indicate an erase pulse signal, a data signal, a clock signal, and a strobe signal, respectively.
The clock signal ECL defines a cycle in the sustain discharge period C, and transfers the data signal EDA corresponding to each scan electrode by the clock signal ECL. Strobe signal E after transfer is completed
By ST, the data in the shift register is transferred to the latch, and the erase pulse obtained by voltage-amplifying the erase pulse signal EBL is output to each scan electrode.

[0020]

In the above-mentioned conventional PDP driving circuit, the scan driver and the erasing driver are provided independently, and the circuit scale including the mixer for mixing these outputs is large. It has the drawback of increasing costs.

In view of the above, the present invention reduces the circuit scale and realizes a drive waveform similar to that of a conventional drive circuit.
It is an object to provide a method for controlling a PDP drive circuit.

[0022]

In order to achieve the above object, a method of controlling a plasma display panel driving circuit according to the present invention comprises display cells arranged in a matrix at each intersection of a plurality of row electrodes and a plurality of column electrodes. In a method of controlling a plasma display panel drive circuit of a type in which the display cell is made to emit light by performing a data write discharge and a sustain discharge on the display cell, the drive circuit is provided with an address discharge period and a sustain discharge period. It is characterized in that the supplied control signal is switched to output the address discharge scan pulse and the sustain discharge stop pulse from the common drive circuit portion to the scan electrode.

The present invention can be applied to any type of AC discharge memory type PDP, for example, a PD having a three-electrode structure.
Besides P, it is applicable to other types of PDPs such as a two-electrode structure.

Here, in the control method of the PDP driving circuit of the present invention, the sustain discharge stop pulse can be an erase discharge pulse inserted between the sustain pulse trains, or
It is also possible to use a sustain cancel pulse that cancels the potential difference between the pair of electrodes during sustain discharge.

The address discharge scan pulse and the sustain discharge stop pulse can be pulses of the same amplitude supplied from a common power supply, or can be pulses of different amplitude supplied from different power supplies. .

Preferably, the common drive circuit portion for outputting the scan pulse for address discharge and the sustain discharge stop pulse is
It has a register and a latch, and selects a control signal that sequentially shifts the selection output for each scanning cycle in the address discharge period,
In the sustain discharge period, a control signal for transferring the sustain discharge stop data corresponding to all outputs to the latch via the shift register is selected for each sustain cycle.

It is preferable that the shift register is a bidirectional shift register. In this case, it is also preferable that the shift directions are reversed between the address discharge period and the sustain discharge period.

[0028]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a first method of the present invention.
3 is a block diagram showing a configuration of a PDP drive circuit for the embodiment of FIG. The PDP driving circuit shown in the figure has a high voltage pulse generator 17 that generates a pulse for commonly driving the sustain electrodes and a high voltage pulse generator 18 that generates a pulse for commonly driving the scan electrodes. And scan driver 19
And a signal selector 2 for selecting a control signal for the scan driver
4, a mixer 25 for driving the scan electrodes by mixing the respective outputs of the high voltage pulse generator 18 for the scan electrodes and the scan driver 19, and data drivers 22, 2 for driving the data electrodes.
3 is provided. The scan driver 19 is similar to the conventional example,
11, the shift register 31, the latch 32, the high voltage switching circuit 33, the AND gates 34 _i ,.
.. 34 _j

FIG. 2 is a timing chart showing a drive voltage waveform obtained by the drive circuit of FIG. 1 and a control signal waveform for generating the scan pulse P _w and the sustain erasing pulse P _e . In FIG. 2, W _s1 and W _s2 are examples of drive voltage waveforms of the scan electrodes S _c1 and S _c2 . The signals SBL, SDA, SCL and SST are
All of them are signals used during the writing operation, and show a scanning pulse signal, a data signal, a clock signal, and a strobe signal, respectively. The signals EBL, EDA, ECL, and EST are all signals used during the sustain erasing operation, and represent the erase pulse signal, the data signal, the clock signal, and the strobe signal, respectively. The signal SE is a select signal to the selector 24.

In the address discharge period, the select signal
Set SE to low level and write signals SBL and S
DA, SCL, SST are selected to control the scan driver 19.
In the address discharge period, the clock signal SCL defines the scanning pulse period and shifts the data signal SDA in the shift register. The strobe signal SST causes the data in the shift register 31 to be sequentially transferred to the latch 32 by being shifted in time from this shift operation. This allows one-to-one correspondence with the scan electrodes.
The high voltage switching circuit 33 corresponding to the above is sequentially selected, and the scan pulse P _w which is a drive voltage obtained by voltage amplifying the scan pulse signal SBL is output.

In the sustain discharge period, the select signal SE
Is set to high level, and each signal for sustain erase operation EBL, E
DA, ECL, EST are selected to control the scan driver 19.
In the sustain discharge period, the clock signal ECL defines the sustain discharge cycle and transfers the data signal EDA corresponding to each scan electrode to the shift register 31. After the transfer is completed, the strobe signal EST shifts the data in the shift register 31 to the latch 32. As a result, the erase pulse signal EBL
The erase pulse P _e obtained by voltage-amplifying is output.

Since the high voltage output supply voltage to the scan driver 19 is V _w , the scan pulse P _w and the erase pulse P
The amplitude of _e is specified by V _w . Therefore, V _w
If the amplitude of is set to an appropriate value, it is sufficiently applicable to any operation.

FIG. 3 is a block diagram showing a PDP driving circuit for the second embodiment of the method of the present invention. P in the figure
The DP drive circuit includes, in addition to the drive circuit for the first embodiment, a voltage selector 26 that is controlled by the select signal SE and selects either the voltage waveform of the voltage V _w or the voltage waveform of V _e . The control signal and its selection in the scan driver 19 are the same as those in the drive circuit for the first embodiment, and the same reference numerals are given and detailed description thereof is omitted. The voltage selector 26 selects the voltage V _w during the address discharge period and the voltage V _e during the sustain discharge period, respectively.
Supply to 9. Therefore, the amplitude of the scan pulse P _w is regulated to V _w , and the amplitude of the erase pulse P _e is regulated to V _e . Therefore, the drive condition can be set independently for the write operation and the sustain erase operation.

In the first and second embodiments described above,
The shift direction of the shift register 31 in the scan driver 19 is the same in the address discharge period and the sustain discharge period. In this case, scanning during address discharge is S _c1 , S _c2 , _...
.., S _cj , that is, in ascending order from the youngest scan line, the shift direction in the sustain discharge period is also defined according to this scan direction.

By the way, during the sustain discharge period, the erase data signal EDA corresponding to all the scan electrodes is transferred to the shift register 31 of the scan driver 19 for each sustain period. Therefore, in order to make the shift direction of the sustain discharge period the same as the shift direction during scanning, the data signal EDA is set to S _cj ,
S _cj-1, ···, in the order of S _c1, that is, from the erase data corresponding to the final of the scan line it must be fed to the descending order. As described above, in order to rearrange the data signal EDA in descending order, the addresses of the memory storing the data are input in descending order and the data is read out in the necessary order, or the data is stored in descending order from the head address in advance. A data conversion circuit, such as a storage device, is required.

FIG. 4 is a block diagram showing a PDP drive circuit for the third embodiment of the method of the present invention, which does not require the above-mentioned data conversion circuit for erase data. The PDP driving circuit shown in the figure has a high voltage pulse generator 17 that generates a pulse for commonly driving the sustain electrodes and a high voltage pulse generator 18 that generates a pulse for commonly driving the scan electrodes. A scan driver 27, a signal selector 28 for selecting a control signal for the scan driver, a mixer 25 for mixing the outputs of the high voltage pulse generator 18 for the scan electrode and the scan driver 27 to drive the scan electrode, Data drivers 22 and 23 for driving the data electrodes are provided.

FIG. 5 is a block diagram showing an internal circuit of the scan driver 27 of FIG. The scan driver 27 includes a shift register 36, a latch 32, a high voltage switching circuit 33, and AND gates 34 _i , ..., 34 _j . The shift register 36 has a bidirectional function capable of reversing the shift direction. Signal line LB
L is an input line of a scan pulse signal that determines the basic output waveform of the high voltage switching circuit 33. The signal lines LDA-A and LDA-B are data signal input lines to the shift register 36, and one of them is selected as an input to the shift register 36 under the control of the select signal input line LSE. , Data is input to one or the other end of the shift register 36. The signal line LCL is a clock signal input line for the shift register, and the signal line LST is a strobe signal input line for the latch.

The drive waveforms shown in FIG. 2 will also be referred to.
In this drive circuit, the select signal SE is set to the low level during the address discharge period, and each signal SB for the address operation is set.
The scan driver 19 is controlled by selecting L, SCL and SST. At this time, the select signal SE causes the signal line LDA-A to be an input line to the shift register of the scan driver 27, and the data signal SDA is allowed to pass through the gate 37 and input to the scan driver 27, while the data signal EDA is input. Is prohibited from passing through the gate 38.

In the sustain discharge period, the select signal SE
Is set to high level, and each signal for sustain erase operation EBL, E
The scan driver 19 is controlled by selecting CL and EST. At this time, the select signal SE causes the shift register of the scan driver 27 to use the signal line LDA-B as an input line to prevent the data signal SDA from passing through the gate 37, while allowing the data signal EDA to pass through the gate 38. Input to the scan driver 27.

As described above, by reversing the shift direction of the shift register in the scan driver 27 in the address discharge period and the sustain discharge period, the scan driver 27 does not require data conversion such as rearrangement of erase data. Both the ascending scan pulse P _w and the descending erase pulse P _e are realized by the internal circuit configuration.

In this embodiment, as in the second embodiment, it is possible to provide a voltage selector for selecting the supply voltage of the scan driver.

The control method of the drive circuit of the present invention has been described above mainly with respect to the generation control means of the scan pulse P _w and the erase pulse P _e . Here, in the control method of the present invention, as shown in FIG. 6, for example, the sustain cancel pulse P _cl can be continuously applied to the scan electrodes instead of the erase pulse P _e in the above embodiment. In this case, the sustain cancel pulse P _c1 is a pulse having the same phase as the sustain pulse P _u applied to the sustain electrodes to relatively lower the voltage applied between the sustain electrodes and the scan electrodes to stop the sustain discharge. It is also possible.

As shown in FIG. 7, the sustain cancel pulse P _c2 for stopping the sustain discharge applied to the scan electrodes can be applied in accordance with the application timing of the sustain pulse P _u .

Although the present invention has been described based on its preferred embodiment, the control method of the PDP drive circuit of the present invention is not limited to the configuration of the above embodiment, and the configuration of the above embodiment. Various control and modification methods of the PDP drive circuit are also included in the scope of the present invention. For example, although the AC discharge memory type PDP having a three-electrode structure has been described in the above embodiment, the present invention can be applied to a memory type PDP having another electrode structure.

[0045]

As described above, according to the control method of the plasma display panel drive circuit of the present invention, the control signal is switched between the address discharge period and the sustain discharge period to stop the scan pulse for the address discharge and the sustain discharge stop. Since it is possible to generate the sustaining stop pulse for use from the common drive circuit portion, the present invention has the remarkable effect of reducing the circuit scale of the drive circuit of the plasma display panel and reducing its cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a drive circuit configuration for implementing a method of controlling a drive circuit of a PDP according to a first embodiment of the present invention.

FIG. 2 is a timing diagram showing voltage drive waveforms and control signal waveforms in the drive circuit of FIG.

FIG. 3 is a block diagram showing a drive circuit configuration for implementing a method for controlling a drive circuit of a PDP according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a drive circuit configuration for implementing a method for controlling a drive circuit of a PDP according to a third embodiment of the present invention.

5 is a block diagram showing an internal circuit of a scan driver in the drive circuit of FIG.

FIG. 6 is a second example of drive waveforms obtained by the control method of the PDP drive circuit of the present invention.

FIG. 7 is a third example of drive waveforms obtained by the method for controlling a PDP drive circuit according to the present invention.

FIG. 8 is a cross-sectional view showing the configuration of one display cell of a general AC memory operation type PDP.

FIG. 9 is a block diagram showing a drive circuit configuration for implementing a conventional control method.

FIG. 10 is a plan view showing an electrode arrangement of a general AC memory operation type PDP.

FIG. 11 is a block diagram showing an internal circuit of a scan driver in a drive circuit that implements a conventional control method.

FIG. 12 is a timing chart of drive waveforms of a PDP obtained by a conventional control method.

FIG. 13 is a timing diagram of control signal waveforms of a drive circuit of a PDP used in a conventional control method.

[Explanation of symbols]

A preliminary discharge period B address discharge period C sustain discharge period P _p preliminary discharge pulse P _pe preliminary discharge erase pulse P _w scan pulse P _u , P _s sustain pulse P _d data pulse P _e erase pulse P _c1 , P _c2 sustain cancel Pulse 1, 2 Insulating substrate 3, S _{c1 to} S _cj scan electrode 4, S _{u1 to} S _uj sustain electrode 7, D _{1 to} D _k data electrode 8 discharge gas space 9 partition wall 11 phosphor 12, 14 dielectric 13 protective film 15 PDP 16 Display cell 17, 18 High voltage pulse generator 19, 27 Scan driver 20 Erase driver 21, 25 Mixer 22, 23 Data driver 24, 28 Selector 26 Voltage selector 31, 36 Shift register 32 Latch 33 High voltage switching circuit 34 _{i to} 34 _j AND gates 37 and 38 gates

Claims (6)

[Claims] 1. A display cell is arranged in a matrix at each intersection of a plurality of row electrodes and a plurality of column electrodes, and data writing discharge and sustain discharge are performed on the display cells to cause the display cells to emit light. In a control method of a plasma display panel drive circuit of a type, a control signal supplied to the drive circuit is switched between an address discharge period and a sustain discharge period, and a scan pulse for address discharge and a sustain discharge stop pulse are supplied from a common drive circuit portion. A method of controlling a plasma display panel drive circuit, which is characterized in that output is performed to a scan electrode. 2. The control method of the plasma display panel driving circuit according to claim 1, wherein the sustain discharge stop pulse is an erase discharge pulse inserted in a sustain pulse train. 3. The sustain discharge stop pulse is a pulse that is applied to the other pair of electrodes at the time of sustain discharge to cancel the potential difference between the electrodes due to the sustain pulse.
The control method of the plasma display panel drive circuit according to claim 1. 4. A plurality of power supplies having mutually different voltage amplitudes are supplied to the common drive circuit part, and the common drive circuit part switches the plurality of power supplies between an address discharge period and a sustain discharge period to output the same. The method for controlling a plasma display panel drive circuit according to claim 1, wherein 5. The common drive circuit portion includes a shift register and a latch, selects a control signal that sequentially shifts a selected output for each scan cycle during the address discharge period, and selects each control cycle during the sustain discharge period. 5. A control signal for transferring the sustain discharge stop data corresponding to all outputs to the latch via the shift register is selected.
A method for controlling a plasma display panel drive circuit according to any one of 1. 6. The plasma display panel drive circuit according to claim 5, wherein the shift direction of the shift register is bidirectional, and the shift directions are opposite between the address discharge period and the sustain discharge period. Control method.