KR100576416B1 - Method for formating junction in semiconductor - Google Patents
Method for formating junction in semiconductor Download PDFInfo
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- KR100576416B1 KR100576416B1 KR1020030088930A KR20030088930A KR100576416B1 KR 100576416 B1 KR100576416 B1 KR 100576416B1 KR 1020030088930 A KR1020030088930 A KR 1020030088930A KR 20030088930 A KR20030088930 A KR 20030088930A KR 100576416 B1 KR100576416 B1 KR 100576416B1
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- gate electrode
- oxide film
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000007772 electrode material Substances 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- 239000012535 impurity Substances 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims abstract description 3
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 238000000137 annealing Methods 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- 229920005591 polysilicon Polymers 0.000 abstract description 8
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체의 정션 형성 방법에 관한 것으로, 반도체 기판 상에 게이트 산화막 및 게이트 전극 형성 물질을 순차적으로 적층하는 단계와, 게이트 전극 물질이 형성된 영역을 제외한 기판상의 게이트 산화막을 제거하는 단계와, 게이트 산화막이 제거된 상태에서, 열처리 공정을 수행하여 게이트 전극물질에 형성된 불순물이 아웃-확산(out-diffusion) 되어, 게이트 전극 양측의 기판내에 정션(junction)을 형성하는 단계를 포함한다. 따라서, 종래 공정 과정에 의한 많은 공정 시간의 소요와, 이로 인한 전체 공정 단가를 높여 경제적으로 부담을 느끼게 되는 문제점을 해결할 수 있다. 또한, 어닐링 수행에 따른 아웃 확산이 되는 량을 폴리 실리콘의 도핑에 의해서 아주 쉽게 임의로 조절할 수 있는 효과가 있다. The present invention relates to a method for forming a junction of a semiconductor, comprising sequentially depositing a gate oxide film and a gate electrode forming material on a semiconductor substrate, removing the gate oxide film on the substrate except for the region where the gate electrode material is formed, and In the state in which the oxide film is removed, an impurity formed in the gate electrode material is out-diffused by performing a heat treatment process to form a junction in the substrate on both sides of the gate electrode. Therefore, it is possible to solve the problem that a large amount of processing time due to the conventional process process, and thereby the overall process unit cost thereby increasing the economic burden. In addition, there is an effect that can be easily adjusted arbitrarily easily by the doping of polysilicon amount due to the annealing performed.
Out-diffusion, 어닐링(annealing), 폴리 실리콘Out-diffusion, Annealing, Polysilicon
Description
도 1은 종래 반도체의 정션 형성 공정 과정에 대하여 도시한 도면이고, 1 is a view showing a process for forming a junction of a conventional semiconductor,
도 2는 본 발명에 따른 반도체의 정션 형성 공정 과정에 대하여 도시한 도면이다.2 is a view illustrating a process of forming a junction of a semiconductor according to the present invention.
본 발명은 반도체의 정션(junction) 형성 방법에 관한 것으로, 공정단계를 줄임으로서, 공정단순화 및 원가절감의 효과를 얻을 수 있는 트랜지터의 정션(junction) 형성 방법이다. BACKGROUND OF THE
일반적으로, 반도체의 정션 형성 과정은, 도 1a에 도시된 바와 같이, P-기판(sub)(S1) 상에 게이트 산화막(S2)을 증착하며, 증착된 게이트 산화막(S2)상에 폴리 실리콘(S3)을 형성한다.In general, a process of forming a junction of a semiconductor may be performed by depositing a gate oxide film S2 on a P-sub substrate S1 as illustrated in FIG. 1A, and using polysilicon on the deposited gate oxide film S2. S3) is formed.
이후, 도 1b와 같이, 게이트 산화막(S2) 상에 포토 레지스터(S4)를 증착한 상태에서, 추가적으로 패터닝 공정 과정 및 이온 주입 공정 과정을 수행한다.Thereafter, as shown in FIG. 1B, in the state in which the photoresist S4 is deposited on the gate oxide film S2, an additional patterning process and an ion implantation process are performed.
다음으로, 도 1c와 같이, 포토 레지스터(S4)를 제거하면, P-기판(sub)(S1)에 정션(junction)(S5)이 형성된다.Next, as shown in FIG. 1C, when the photoresist S4 is removed, a junction S5 is formed in the P-sub substrate S1.
이와 같이, 트랜지스터의 정션은 패터닝 공정 과정과 이온 주입 공정 과정을 단계적으로 거쳐 형성되므로, 많은 공정 시간을 소요하게 되며, 이로 인하여 전체 공정 단가를 높여 경제적으로 부담을 느끼게 되는 문제점을 갖는다. As described above, since the junction of the transistor is formed through the patterning process and the ion implantation process step by step, it takes a lot of processing time, thereby increasing the overall process cost and having a problem of economic burden.
이에, 본 발명은 상술한 문제점을 해결하기 위해 안출된 것으로, 그 목적은 패터닝 공정 및 이온 주입 공정 과정을 스킵(skip)한 상태에서, 어닐링을 이용하여 트랜지스터의 정션을 형성할 수 있도록 하는 반도체의 정션 형성 방법을 제공함에 있다.Accordingly, an object of the present invention is to solve the above-described problems, and an object thereof is to provide a junction of a transistor using annealing in a state in which a patterning process and an ion implantation process are skipped. The present invention provides a method for forming a junction.
이러한 목적을 달성하기 위한 본 발명에서 반도체의 정션 형성 방법은 반도체 기판 상에 게이트 산화막 및 게이트 전극 형성 물질을 순차적으로 적층하는 단계와, 게이트 전극 물질이 형성된 영역을 제외한 기판상의 게이트 산화막을 제거하는 단계와, 게이트 산화막이 제거된 상태에서, 열처리 공정을 수행하여 게이트 전극물질에 형성된 불순물이 아웃-확산(out-diffusion) 되어, 게이트 전극 양측의 기판내에 정션(junction)을 형성하는 단계를 포함하는 것을 특징으로 한다.In the present invention, a method of forming a junction of a semiconductor according to the present invention comprises sequentially depositing a gate oxide film and a gate electrode forming material on a semiconductor substrate, and removing the gate oxide film on the substrate except for the region where the gate electrode material is formed. And performing a heat treatment to remove impurities formed in the gate electrode material by out-diffusion in a state where the gate oxide film is removed, thereby forming a junction in the substrate on both sides of the gate electrode. It features.
이하, 첨부된 도면을 참조하여 본 발명의 구성 및 동작에 대하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the present invention.
도 2는 본 발명에 따른 반도체의 정션 형성 과정에 대하여 도시한 도면이다.2 is a view illustrating a process of forming a junction of a semiconductor according to the present invention.
즉, 도 2a를 참조하면, P-기판(sub)(SS1) 상에 게이트 산화막(SS2)을 증착하며, 증착된 게이트 산화막(SS2)상에 폴리 실리콘(SS3)을 형성한다.That is, referring to FIG. 2A, the gate oxide layer SS2 is deposited on the P-sub substrate SS1, and the polysilicon SS3 is formed on the deposited gate oxide layer SS2.
이후, 도 2b와 같이, P-기판(sub)(SS1) 상에 폴리 실리콘(SS3)이 형성된 부분의 게이트 산화막(SS2)만을 남겨둔 상태에서, P-기판(sub)(SS1) 상의 나머지 게이트 산화막을 제거한다. Thereafter, as shown in FIG. 2B, the remaining gate oxide film on the P-sub substrate SS1 is left in the state in which only the gate oxide film SS2 of the portion where the polysilicon SS3 is formed on the P-sub substrate SS1 is left. Remove it.
다음으로, 도 2c와 같이, P-기판(sub)(SS1) 상에 폴리 실리콘(SS3)이 형성된 부분의 게이트 산화막(SS2)을 남겨두고, 나머지 게이트 산화막을 제거한 상태에서, 어닐링(annealing)(예컨대,어닐링 조건은 어닐링 시작시점에 있어서 산소(O2) 가스가 들어가기 전에 750℃ 이상의 열처리 공정)을 수행하여 아웃-확산(out-diffusion)이 폴리 실리콘(SS3) 양쪽으로 발생하도록 하여 P-기판(sub)(SS1)에 정션(junction)(SS4)을 형성하는 것이다. Next, as shown in FIG. 2C, annealing is performed while leaving the gate oxide film SS2 of the portion where the polysilicon SS3 is formed on the P-sub substrate SS1 and removing the remaining gate oxide film. For example, the annealing condition is a heat treatment process of 750 ° C. or more before oxygen (O 2) gas enters at the start of the annealing so that out-diffusion occurs to both sides of the polysilicon (SS3). The junction SS4 is formed in the sub SS1.
이로 인하여, 트랩(trap)을 만들 수 있는 절연막을 이용한 SONOS 셀(cell)을 이용하여 스프리트 게이트(split gate) 형태의 비휘발성 메모리 셀(cell)을 구현할 수 있다.As a result, a non-volatile memory cell having a split gate shape may be implemented by using a SONOS cell using an insulating film capable of forming a trap.
이상, 본 발명의 바람직한 실시예를 설명하였지만, 본 발명은 상기 실시예에 국한 되는 것이 아니라, 본 발명이 속하는 분야의 숙련자에 의해 본 발명의 기술사항을 벗어남 없이 다양한 변화나 변경 또는 조절이 가능함은 자명하다.Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various changes, modifications, or adjustments can be made by those skilled in the art without departing from the technical details of the present invention. Self-explanatory
상기와 같이 설명한 본 발명은 패터닝 공정 및 이온 주입 공정 과정을 스킵(skip)한 상태에서, 어닐링(annealing)을 이용하여 트랜지스터의 정션을 형성함으로써, 종래 공정 과정에 비해 공정시간 및 공정단가를 절감할 수 있다.According to the present invention as described above, by forming the junction of the transistor using annealing in a state in which the patterning process and the ion implantation process are skipped, process time and cost can be reduced as compared with the conventional process. Can be.
또한, 어닐링 수행에 따른 out-diffusion이 되는 량을 폴리 실리콘의 도핑에 의해서 용이하게 조절할 수 있어, 작업자의 의도대로 정션깊이를 조절할 수 있다. In addition, the amount of out-diffusion due to annealing can be easily controlled by doping polysilicon, and thus the depth of the junction can be adjusted according to the intention of the operator.
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