KR100575868B1 - method of fabricating chip scale package - Google Patents

method of fabricating chip scale package Download PDF

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KR100575868B1
KR100575868B1 KR1020020084413A KR20020084413A KR100575868B1 KR 100575868 B1 KR100575868 B1 KR 100575868B1 KR 1020020084413 A KR1020020084413 A KR 1020020084413A KR 20020084413 A KR20020084413 A KR 20020084413A KR 100575868 B1 KR100575868 B1 KR 100575868B1
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substrate
chip
wiring
semiconductor chip
forming
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KR1020020084413A
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KR20040057646A (en
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조철호
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

본 발명은 반도체 칩과 기판을 전기적으로 연결시키는 금속와이어의 본딩 공정을 생략하여 제조공정을 단순화하여 제품의 신뢰성이 우수한 칩크기(chip scale) 패키지의 제조방법에 관해 개시한 것으로서, 제 1및 제 2면을 연결시키는 배선이 구비된 기판을 제공하는 단계와, 칩패드가 구비된 반도체 칩을 제공하는 단계와, 기판의 제 1면 위에 상기 반도체 칩을 부착시키는 단계와, 상기 결과의 기판 위에 상기 배선 및 칩패드를 노출시키는 금속 마스크를 씌우는 단계와, 금속 마스크를 이용하여 기판 전면에 금속을 스퍼터링하여 배선과 칩패드를 덮는 전도선을 형성하는 단계와, 금속 마스크를 제거하는 단계와, 기판 상에 전도선 및 반도체 칩을 덮는 몰딩체를 형성하는 단계와, 기판의 제 2면의 배선과 연결되는 솔더 볼을 형성하는 단계를 포함한다.The present invention discloses a method of manufacturing a chip scale package having excellent product reliability by simplifying a manufacturing process by omitting a bonding process of a metal wire electrically connecting a semiconductor chip and a substrate. Providing a substrate with wiring connecting two sides, providing a semiconductor chip with chip pads, attaching the semiconductor chip on a first surface of the substrate, and Overlaying a metal mask that exposes the wiring and the chip pad; forming a conductive wire covering the wiring and the chip pad by sputtering metal on the entire surface of the substrate using the metal mask; removing the metal mask; Forming a molding body covering the conductive line and the semiconductor chip, and forming a solder ball connected to the wiring of the second surface of the substrate.

Description

칩크기 패키지의 제조방법{method of fabricating chip scale package}Method of fabricating chip scale package

도 1은 종래 기술에 따른 칩크기 패키지의 제조 방법을 설명하기 위한 단면도.1 is a cross-sectional view illustrating a method for manufacturing a chip size package according to the prior art.

도 2a 내지 도 2d는 본 발명에 따른 칩크기 패키지의 제조 방법을 설명하기 위한 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a chip size package according to the present invention.

도 3은 본 발명의 제 2실시예에 따른 패키지 단면도.3 is a cross-sectional view of a package according to a second embodiment of the present invention.

도 4는 본 발명의 제 3실시예에 따른 패키지 단면도.4 is a cross-sectional view of a package according to a third embodiment of the present invention.

도 5는 본 발명의 제 4실시예에 따른 패키지 단면도.5 is a cross-sectional view of a package according to a fourth embodiment of the present invention.

본 발명은 반도체 패키지(package)의 제조방법에 관한 것으로, 보다 상세하게는 반도체 칩과 기판을 전기적으로 연결시키는 금속와이어의 본딩 공정을 생략하여 제조공정을 단순화하여 제품의 신뢰성이 우수한 칩크기(chip scale) 패키지의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor package, and more particularly, a chip size that simplifies the manufacturing process by omitting the bonding process of metal wires electrically connecting the semiconductor chip and the substrate, thereby providing excellent chip reliability. scale) relates to a method for manufacturing a package.

일반적으로 널리 알려진 바와 같이, 웨이퍼의 박막 성장 기법에 의해 제조된 칩(chip)을 웨이퍼로 부터 절단(sawing)분리한 다음, 분리된 칩을 실드(shield)나 몰딩(molding)으로 외부의 습기나 불순물로부터 보호되고 또한 외부회로와의 접속을 위한 리드를 부착한 패키지 형태로 상품화된다.As is generally known, chips produced by the thin film growth technique of the wafer are sawed from the wafer, and then the separated chips are shielded or molded from external moisture. It is commercialized in the form of a package protected from impurities and attached with a lead for connection with an external circuit.

이러한 패키지중 대부분의 공간을 칩이 차지하는 정도의 크기로 몰딩되는 칩크기의 패키지는 그 자체가 단일한 미소 소자(micro device)로 상품화되어 회로기판에 있어서의 실장밀도를 높이고 응용 주문형 집적회로(ASIC:Application Specific IC)등 각종 집적회로에서의 집적도를 높이는 데 유용하다.Chip-sized packages, which are molded to the extent that the chip takes up most of the space, are themselves commercialized as a single micro device, which increases the mounting density of the circuit board and the application specific integrated circuit (ASIC). It is useful for increasing the degree of integration in various integrated circuits such as application specific ICs.

도 1은 종래 기술에 따른 칩크기 패키지의 제조 방법을 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a method of manufacturing a chip size package according to the prior art.

종래 기술에 따른 칩크기 패키지의 제조 방법은, 도 1에 도시된 바와 같이, 먼저 PCB(Printed Circuit Board)기판(12) 위에 접착 테이프(14)를 개재시켜 반도체 칩(10)을 부착시킨다. 이어, 반도체 칩(10)의 칩패드(11)와 기판(12)의 배선(15)과의 전기적 연결을 위하여 본딩 공정을 진행하여 금속 와이어(13)를 형성한다. In the method of manufacturing a chip size package according to the prior art, as shown in FIG. 1, the semiconductor chip 10 is attached to the printed circuit board (PCB) substrate 12 via an adhesive tape 14. Subsequently, a bonding process is performed to electrically connect the chip pad 11 of the semiconductor chip 10 and the wiring 15 of the substrate 12 to form a metal wire 13.

그런 다음, 외부의 먼지나 습기를 차단하기 위해, PCB기판(12) 상에 금속 와이어(13) 및 반도체 칩(10)을 덮도록 몰딩체(19)를 형성한 다음, 외부와의 전기적 연결을 위하여 기판(12)의 배선(15) 상에 솔더볼(17)을 부착시킨다.Then, in order to block external dust or moisture, the molding body 19 is formed on the PCB substrate 12 to cover the metal wire 13 and the semiconductor chip 10, and then the electrical connection with the outside is formed. In order to attach the solder ball 17 on the wiring 15 of the substrate 12.

이 후, 도면에 도시되지 않았지만, 개별적인 칩단위로 절단하여 칩크기의 패키지 제조를 완료한다.  Thereafter, although not shown in the figure, the chip size package is completed by cutting the individual chip units.

그러나, 종래 기술에서는 반도체 칩과 기판과의 전기적인 연결을 위해 금속 와이어를 형성함으로써, 금속 와이어의 길이만큼 전기적 연결 길이가 증가하게되어 금속와이어로부터 발생되는 커패시턴스(capacitance), 인덕턴스(inductance) 및 레지스턴스(resistance)가 증가하게 된다. 따라서, 신호전달이 지연되고 노이즈(noise)가 발생되어 제품의 동작 특성을 저하시킨다.However, in the prior art, by forming a metal wire for the electrical connection between the semiconductor chip and the substrate, the electrical connection length is increased by the length of the metal wire, so that capacitance, inductance and resistance generated from the metal wire are increased. (resistance) increases. Therefore, signal transmission is delayed and noise is generated, which lowers the operating characteristics of the product.

또한, 종래의 기술에서는 별도의 본딩 장비 구입에 따른 생산 비용의 증가 및 골드 와이어를 사용함에 따른 와이어 스위핑 및 와이어의 노출 현상 등이 발생되는 문제점이 있었다.In addition, in the conventional technology, there is a problem that an increase in production cost according to the purchase of a separate bonding equipment and wire sweeping and exposure of wires due to the use of gold wires occur.

이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 반도체 칩과 기판을 전기적으로 연결시키는 금속와이어의 본딩 공정을 생략하여 제조공정을 단순화하여 제품의 신뢰성이 우수한 칩크기 패키지의 제조 방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems, and the manufacturing process is simplified by omitting the bonding process of the metal wire that electrically connects the semiconductor chip and the substrate, thereby producing a chip size package having excellent product reliability. The purpose is to provide.

상기 목적을 달성하기 위한 본 발명의 칩크기 패키지의 제조 방법은 제 1및 제 2면을 연결시키는 배선이 구비된 기판을 제공하는 단계와, 칩패드가 구비된 반도체 칩을 제공하는 단계와, 기판의 제 1면 위에 상기 반도체 칩을 부착시키는 단계와, 상기 결과의 기판 위에 상기 배선 및 칩패드를 노출시키는 금속 마스크를 씌우는 단계와, 금속 마스크를 이용하여 기판 전면에 금속을 스퍼터링하여 배선과 칩패드를 덮는 전도선을 형성하는 단계와, 금속 마스크를 제거하는 단계와, 기판 상에 전도선 및 반도체 칩을 덮는 몰딩체를 형성하는 단계와, 기판의 제 2면의 배선과 연결되는 솔더 볼을 형성하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a chip size package, the method including: providing a substrate having wirings connecting the first and second surfaces; providing a semiconductor chip having a chip pad; Attaching the semiconductor chip on a first surface of the substrate; applying a metal mask to expose the wiring and chip pads on the resultant substrate; and sputtering metal on the entire surface of the substrate using a metal mask; Forming a conductive line covering the conductive layer, removing the metal mask, forming a molding covering the conductive line and the semiconductor chip on the substrate, and forming a solder ball connected to the wiring on the second surface of the substrate. Characterized in that it comprises a step.

상기 전도선을 형성하기 이전에, 금속 마스크를 이용하여 기판 전면에 전도성 접착층을 형성하는 단계를 추가한다.Prior to forming the conductive line, a step of forming a conductive adhesive layer on the entire surface of the substrate using a metal mask is added.

상기 전도성 접착층은 티타늄(Ti)막 및 크롬(Cr)막 중 어느 하나를 이용한다.The conductive adhesive layer uses any one of a titanium (Ti) film and a chromium (Cr) film.

상기 전도선은 구리(Cu)막을 이용한다.The conductive line uses a copper (Cu) film.

상기 전도선을 형성한 다음에, 전도선에 도금처리를 실시하여 도금층을 형성하는 단계를 더 추가한다.After forming the conductive line, the conductive line is further plated to form a plating layer.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명에 따른 칩크기 패키지의 제조방법은, 도 2에 도시된 바와 같이, 먼저 PCB기판(112) 위에 접착 테이프 등의 비전도성 접착층(114)를 개재시켜 반도체 칩(110)들을 부착시킨 다음, 상기 구조의 기판을 플라즈마(plasma) 세정 처리(미도시)를 실시한다. 이때, 상기 반도체 칩(110)은 가장자리 부분에 칩패드(111)가 형성된 구조를 가진다. 또한, 상기 기판(112)은 배선(113)이 형성되어 이 후의 공정에서 반도체 칩의 칩패드(111)와 연결된다.In the method of manufacturing a chip size package according to the present invention, as shown in FIG. 2, first, the semiconductor chips 110 are attached to each other by interposing a non-conductive adhesive layer 114 such as an adhesive tape on the PCB substrate 112. The substrate having the above structure is subjected to a plasma cleaning process (not shown). In this case, the semiconductor chip 110 has a structure in which a chip pad 111 is formed at an edge portion thereof. In addition, a wiring 113 is formed on the substrate 112 and is connected to the chip pad 111 of the semiconductor chip in a subsequent process.

한편, 상기 세정 처리는 이 후의 공정에서 전도성 접착층을 형성할 경우 반도체 칩과 전도성 접착층 간의 부착력을 향상시키기 위한 것이다.On the other hand, the cleaning treatment is to improve the adhesion between the semiconductor chip and the conductive adhesive layer when the conductive adhesive layer is formed in a subsequent step.

이어, 도 2b에 도시된 바와 같이, 상기 세정 처리가 완료된 반도체 칩 위에 반도체 칩(110)의 칩패드(111)와 기판(112)의 배선(113) 사이를 노출시키는 금속 마스크(140)를 올려 놓는다. 상기 금속 마스크(140)는 상기 기판(112)과 동일 크기 로서, 반도체 칩(110)의 칩패드(111)와 기판(112)의 배선(113) 사이를 노출시키도록 패터닝된다.Subsequently, as shown in FIG. 2B, the metal mask 140 is placed on the semiconductor chip on which the cleaning process is completed, exposing the chip pad 111 of the semiconductor chip 110 and the wiring 113 of the substrate 112. Release. The metal mask 140 is the same size as the substrate 112 and is patterned to expose the chip pad 111 of the semiconductor chip 110 and the wiring 113 of the substrate 112.

그런 다음, 상기 금속 마스크(140)를 이용하여 상기 결과물에 스퍼터링(sputtering) 공정에 의해 티타늄(Ti)막 또는 크롬(Cr)막을 증착하여 전도성 접착층(116)을 형성한다. 이때, 상기 전도성 접착층(116)은 반도체 칩(110)의 칩패드(111)와 기판(112)의 배선(113) 사이에 형성된다. Then, the conductive mask layer 116 is formed by depositing a titanium (Ti) film or a chromium (Cr) film on the resultant by sputtering using the metal mask 140. In this case, the conductive adhesive layer 116 is formed between the chip pad 111 of the semiconductor chip 110 and the wiring 113 of the substrate 112.

한편, 전도성 접착층(116)은 반도체 칩과 이 후의 공정에서 형성될 전도선 간의 부착력이 약하기 때문에 이들 간의 부착력을 향상시키기 위해 개재시킨다. 또한, 상기 전도성 접착층(116)의 재질로서 티타늄(Ti)막 또는 크롬(Cr)막을 사용하는 이유는 구리(Cu)막에 비해 부착력이 우수한 특성을 가지기 때문이다.On the other hand, the conductive adhesive layer 116 is interposed to improve the adhesion between the semiconductor chip and the conductive wire to be formed in the subsequent process is weak. In addition, the reason why the titanium (Ti) film or the chromium (Cr) film is used as the material of the conductive adhesive layer 116 is because the adhesive force is superior to the copper (Cu) film.

계속해서, 상기 금속 마스크(140)을 이용하여 전도성 접착층(114) 위에 다시 스퍼터링 공정에 의해 구리(Cu)막을 증착하여 전도선(118)을 형성한다. 상기 구리막은 골드 와이어에 비해 전기적 특성이 우수하다.Subsequently, a copper (Cu) film is deposited on the conductive adhesive layer 114 again by the sputtering process using the metal mask 140 to form a conductive line 118. The copper film has better electrical characteristics than gold wire.

이 후, 상기 전도선(118)을 도금처리하여 도금층(119)을 형성한다. 이때, 상기 도금처리 공정은 증착된 구리막의 두께를 최소화하고 그 위에 구리막을 전해 또는 비전해의 방법으로 도금하여 구리막의 두께 증가에 따른 시간 및 비용을 절감할 수 있다. 상기 도금층(119) 형성은 필요에 따라 생략할 수도 있다.Thereafter, the conductive line 118 is plated to form a plating layer 119. In this case, the plating process may minimize the thickness of the deposited copper film and plate the copper film thereon by an electrolytic or non-electrolytic method, thereby reducing time and cost according to an increase in the thickness of the copper film. Formation of the plating layer 119 may be omitted as necessary.

이어, 도 2c에 도시된 바와 같이, 금속 마스크를 제거한다.Next, as shown in FIG. 2C, the metal mask is removed.

그런 다음, 도 2d에 도시된 바와 같이, 외부의 먼지나 습기를 차단하기 위해, 상기 전도선 패턴(120)을 포함한 PCB기판 전면을 덮도록 몰딩체(130)를 형성한 다음, 외부와의 전기적 연결을 위하여 기판(112)의 금속 배선(113) 상에 솔더볼(132)을 부착시킨다.Then, as shown in Figure 2d, in order to block the dust and moisture outside, the molding body 130 is formed to cover the front surface of the PCB substrate including the conductive line pattern 120, and then electrical The solder ball 132 is attached to the metal wire 113 of the substrate 112 for the connection.

이 후, 도면에 도시되지 않았지만, 개별적인 칩단위로 절단하여 칩크기의 패키지 제조를 완료한다.  Thereafter, although not shown in the figure, the chip size package is completed by cutting the individual chip units.

도 3은 본 발명의 제 2실시예에 따른 패키지 단면도이다.3 is a cross-sectional view of a package according to a second embodiment of the present invention.

본 발명의 제 2실시예에서는, 도 3에 도시된 바와 같이, 본 발명의 제 1실시예에 따른 방법을 이용하여 2개 이상의 반도체 칩을 적층시켜 형성할 수도 있다.In the second embodiment of the present invention, as shown in FIG. 3, two or more semiconductor chips may be stacked by using the method according to the first embodiment of the present invention.

도 4는 본 발명의 제 3실시예에 따른 패키지 단면도이다.4 is a cross-sectional view of a package according to a third embodiment of the present invention.

본 발명의 제 3실시예에서는, 도 4에 도시된 바와 같이, 본 발명의 제 1실시예에 따른 방법을 센터 패드를 구비한 반도체 칩에 적용하여 칩크기 패키지를 제조할 수 있다.In the third embodiment of the present invention, as shown in FIG. 4, the chip size package may be manufactured by applying the method according to the first embodiment of the present invention to a semiconductor chip having a center pad.

도 5는 본 발명의 제 4실시예에 따른 패키지 단면도이다.5 is a cross-sectional view of a package according to a fourth embodiment of the present invention.

본 발명의 제 4실시예에서는, 도 5에 도시된 바와 같이, 본 발명의 제 3실시예에 따른 방법을 이용하여 센터 패드를 구비한 반도체 칩을 2개 이상 적층시켜 칩크기 패키지를 제조할 수 있다.In the fourth embodiment of the present invention, as illustrated in FIG. 5, a chip size package may be manufactured by stacking two or more semiconductor chips having a center pad using the method according to the third embodiment of the present invention. have.

본 발명에 따르면, 와이어 본딩 공정 대신 반도체 칩의 칩패드와 기판의 배선과의 전기적 연결을 위하여 스퍼터링 공정에 의해 전도선을 형성함으로써, 골드 와이어에 비해 전도선의 트레이스(trace)가 짧아진다.According to the present invention, since the conductive line is formed by the sputtering process for the electrical connection between the chip pad of the semiconductor chip and the wiring of the substrate instead of the wire bonding process, the trace of the conductive line is shorter than that of the gold wire.

이상에서와 같이, 반도체 칩의 칩패드와 기판의 배선과의 전기적 연결을 위 한 공정에서 골드 와이어 대신 1회의 스퍼터링 공정에 의한 전도선(Cu)을 이용함으로써, 골드 와이어에 비해 전도선의 트레이스가 짧아지고 전기적 특성도 우수해진다. As described above, in the process for electrical connection between the chip pad of the semiconductor chip and the wiring of the substrate, the conductive wire (Cu) is used by one sputtering process instead of the gold wire, so that the trace of the conductive wire is shorter than that of the gold wire. The electrical characteristics are also excellent.

또한, 본 발명은 골드 와이어를 사용하지 않음으로써, 본딩하는데 소요도되는 시간에 비해 공정 시간을 단축시킬 수 있으며, 별도의 본딩 장비가 불필요하고, 와이어 스위핑 및 와이어 노출 등의 현상이 발생되지 않아 작업성이 향상된다.In addition, the present invention can shorten the process time compared to the time required for bonding by not using the gold wire, no need for a separate bonding equipment, work such as wire sweeping and wire exposure does not occur Sex is improved.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (5)

제 1및 제 2면을 연결시키는 배선이 구비된 기판을 제공하는 단계와,Providing a substrate having a wiring connecting the first and second surfaces thereof, 칩패드가 구비된 반도체 칩을 제공하는 단계와,Providing a semiconductor chip equipped with a chip pad, 상기 기판의 제 1면 위에 상기 반도체 칩을 부착시키는 단계와,Attaching the semiconductor chip onto the first surface of the substrate; 상기 결과의 기판 위에 상기 배선 및 칩패드를 노출시키는 금속 마스크를 씌우는 단계와,Placing a metal mask over the resulting substrate exposing the wiring and chip pads; 상기 금속 마스크를 이용하여 상기 기판 전면에 금속을 스퍼터링하여 상기 배선과 칩패드를 덮는 전도선을 형성하는 단계와,Sputtering metal on the entire surface of the substrate using the metal mask to form a conductive line covering the wiring and the chip pad; 상기 금속 마스크를 제거하는 단계와,Removing the metal mask; 상기 기판 상에 전도선 및 반도체 칩을 덮는 몰딩체를 형성하는 단계와,Forming a molding on the substrate to cover the conductive line and the semiconductor chip; 상기 기판의 제 2면의 배선과 연결되는 솔더 볼을 형성하는 단계를 포함하는 것을 특징으로 하는 칩크기 패키지의 제조 방법.Forming a solder ball connected to the wiring of the second surface of the substrate. 제 1항에 있어서, 상기 전도선을 형성하기 이전에, 상기 금속 마스크를 이용하여 상기 기판 전면에 전도성 접착층을 형성하는 단계를 추가하는 것을 특징으로 하는 칩크기 패키지의 제조 방법.The method of claim 1, further comprising forming a conductive adhesive layer on the entire surface of the substrate using the metal mask before forming the conductive line. 제 2항에 있어서, 상기 전도성 접착층은 티타늄(Ti)막 및 크롬(Cr)막 중 어느 하나를 이용하는 것을 특징으로 하는 칩크기 패키지의 제조 방법.The method of claim 2, wherein the conductive adhesive layer is formed of any one of a titanium (Ti) film and a chromium (Cr) film. 제 1항에 있어서, 상기 전도선은 구리(Cu)막을 이용하는 것을 특징으로 하는 칩크기 패키지의 제조 방법.The method of claim 1, wherein the conductive line uses a copper (Cu) film. 제 1항에 있어서, 상기 전도선을 형성한 다음에, 상기 전도선에 도금처리를 실시하여 도금층을 형성하는 단계를 더 추가하는 것을 특징으로 하는 칩크기 패키지의 제조 방법.The method of claim 1, further comprising forming a plating layer by plating the conductive line after forming the conductive line.
KR1020020084413A 2002-12-26 2002-12-26 method of fabricating chip scale package KR100575868B1 (en)

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