KR100572308B1 - Frequency doubler - Google Patents

Abstract

The frequency multiplier disclosed herein includes a first triangle wave generator circuit, a first clock signal and a second clock signal that generate a first triangle wave signal in response to a first clock signal and a second clock signal complementary to the first clock signal. A second triangle wave generator circuit for generating a second triangle wave signal complementary to the first triangle wave signal, a comparison circuit for generating a comparison signal by comparing voltage levels of the first triangle wave signal and the second triangle wave signal, and the comparison And a detection circuit for detecting whether the signal and the first clock signal are at different voltage levels.

Description

Frequency Multiplier {FREQUENCY DOUBLER}

The present invention relates to a frequency doubler, and more particularly, to a frequency multiplier that has a simple circuit configuration and produces a multiplier clock signal of 50% duty.

Frequency multipliers typically use a phase lock loop (PLL) (1). However, the frequency multiplier always produces a clock signal having a frequency twice that of the input clock signal, unlike a frequency synthesizer that can freely produce a desired frequency by adjusting the division of the input clock signal.

1 schematically shows the configuration of a phase locked loop.

Referring to FIG. 1, the phase locked loop 1 includes a phase detection circuit 10, a charge pump circuit 12, a loop filter 14, and a voltage controlled oscillation. Circuit (voltage control oscillation circuit) 16 and divider (18).

When the frequency multiplier is implemented in a phase locked loop having the configuration as described above, the configuration of each of the circuits is complicated, and thus takes up a large area when the frequency multiplier is implemented in the memory chip. In addition, the frequency multiplier composed of a conventional phase locked loop makes it difficult to generate a 50% duty clock signal due to the delay of the signals in the phase locked loop.

The frequency multiplier can produce a clock signal of 50% duty through a delay circuit in addition to the phase locked loop. The delay circuit shifts the phase of the input clock signal by 90 °, and when the shifted clock signal is input to the exclusive or gate together with the input clock signal, a clock signal having twice the frequency of the input clock signal is generated. The clock signal obtained through the delay circuit has a large signal delay and a process variation in the delay circuit, and thus it is difficult to obtain a clock signal accurately shifted by 90 ° with respect to the input clock signal. As a result, there is a limit to generating a clock signal of 50% duty.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide a frequency multiplier having a simple circuit configuration.

It is still another object of the present invention to provide a frequency multiplier that produces a clock signal of exactly 50% duty.

According to a feature of the present invention for achieving the object of the present invention as described above, the frequency multiplier is a first clock signal and a second clock signal in response to the second clock signal complementary to the first clock signal; A second triangle wave generator for generating a second triangle wave signal complementary to the first triangle wave signal and a first triangle wave signal and the second triangle wave signal in response to a first triangle wave generator circuit and the first clock signal and the second clock signal; And a detection circuit for comparing the voltage levels of the signal generators to generate a comparison signal and detecting whether the comparison signal and the first clock signal have different voltage levels.

In a preferred embodiment, the first triangle wave generator circuit is connected between a first node for outputting the first triangle wave signal, a power supply terminal for receiving a power supply voltage, and a first current source for supplying current; A first switch and the first node connected between the first current source and the first node and transferring the current supplied to the first current source to the first node when the first clock signal is 'H'; A first capacitor connected between ground and a second switch connected between the first node and the ground, and between the second switch and the ground, when the second clock signal is 'H'; And a second current source for discharging said first node with a switch.

In a preferred embodiment, the second triangle wave generator circuit is connected between a second node for outputting the second triangle wave signal, a power supply terminal for receiving a power supply voltage, and a second current source for supplying current; A third switch and the second node connected between the third current source and the second node and transferring the current supplied to the third current source to the second node when the second clock signal is 'H'; A second capacitor connected between ground; a third switch connected between the second node and the ground; and between the third switch and the ground, wherein the first clock signal is 'H'. And a fourth current source for discharging said second node with a third switch.

(Action)

According to the present invention, a clock signal of 50% duty can be accurately obtained from the frequency multiplier, and the area occupied by the frequency multiplier in the memory chip can be reduced.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 and 3.

Referring to FIG. 3, the frequency multiplier is composed of switches, current sources, and a comparison circuit, which simplifies the circuit configuration compared to that implemented with a phase locked loop. By comparing the voltage levels of the triangular wave signals generated by the capacitors, a clock signal that is shifted by 90 ° with respect to the input clock signal can be precisely obtained. You can create a clock signal.

2 is a block diagram of a frequency multiplier according to the present invention.

2, a first triangular wave generator circuit 100 generating a first triangular wave signal to a first node Node1 in response to first and second clock signals CLK and CLKB, wherein the first multiplier And a second triangle wave generator circuit 110 for generating a second triangle wave signal complementary to the first triangle wave signal to a second node Node2 in response to a second clock signal CLK and CLKB. A comparison circuit 120 for comparing the voltage levels of the triangular wave signal and a detection circuit 130 for detecting whether the output COMPS of the comparison circuit 120 and the first clock signal CLK are at different levels. .

3 is a circuit diagram showing in detail the configuration of a frequency multiplier according to the present invention.

Referring to FIG. 3, the first triangle wave generator circuit 100 includes first and second current sources I1 and I2, first and second switches SW1 and SW2, and a first capacitor C1. do. The first current source I1 and the first switch SW1 are connected in series between the power supply terminal 1 and the first node Node1. The first capacitor C1 is connected between the first node Node1 and ground 2 and the second switch SW2 and the second current source I2 are connected to the first node Node1 and ground 2. Are connected in series. The first current source I1 and the first switch SW1 operate as a current supply unit for supplying current to the first node Node1, and the second current source I2 and the second switch SW2 are the first It operates as a current charged in the capacitor C1 or a current sink which discharges the first node Node1 to ground.

The second triangle wave generator circuit 110 is composed of third and fourth current sources I3 and I4, third and fourth switches SW3 and SW4 and a second capacitor C2. The third current source I3 and the third switch SW3 are connected in series between the power supply terminal 1 and the second node Node2. The second capacitor C2 is connected between the second node Node2 and ground 2. The fourth switch SW4 and the current source I4 are connected in series between the second node Node2 and the ground 2. The third current source I3 and the third switch SW3 operate as a current supply unit supplying current to the second node Node2, and the fourth current source I4 and the fourth switch SW4 are the second It acts as a current sink that discharges the current charged in capacitor C2 to ground (2).

The comparison circuit 120 has a non-inverting input terminal connected to the first node Node1, an inverting input terminal connected to the second node Node2, and an output terminal connected to the input terminal of the detection circuit 130. The comparison circuit 120 generates a comparison signal COMPS by comparing the voltage levels of the first node Node1 and the second node Node2.

The detection circuit 130 is configured with an exclusive OR gate (XOR) or an exclusive NOR gate (XNOR) that receives the comparison signal COMPS and the first clock signal CLK. In the present invention, only the exclusive or gate (XOR) will be described.

Hereinafter, the operation of the frequency multiplier according to the present invention will be described with reference to FIGS. 3 and 4.

4 is an operation timing diagram of a frequency multiplier according to clock signals.

Referring to FIG. 4, the first clock signal CLK is 'L' and the second clock signal CLKB is 'H' in the interval between t0 and t1, and the first node Node1 descends from the highest point. Two nodes Node2 will rise from the lowest point. The second clock signal CLKB can be easily obtained from an inverter (not shown) which receives the first clock signal CLK as an input.

In the first triangle wave generator circuit 100, the first clock signal CLK of 'L' causes the first switch SW1 to be turned off and the second clock signal CLKB of 'H' is the second switch. Make sure (SW2) is on. The second switch SW2 causes the potential of the first capacitor C1, that is, the potential of the first node Node1, to be discharged through the second current source I2.

In the second triangle wave generator circuit 110, the second clock signal CLKB of 'H' causes the third switch SW3 to be turned on, and the first clock signal CLK of 'L' is The fourth switch SW4 is turned off. The third switch SW3 allows the current supplied from the third current source I3 to be delivered to the second capacitor C2 and the second node Node2.

At t1, the first node Node1 descends and the second node Node2 rises to intersect the two nodes Node1 and Node2. When the voltage levels of the two nodes Node1 and Node2 intersect, the comparison signal COMPS transitions from 'H' to 'L'. The comparison signal COMPS and the first clock signal CLK are input to XOR to output a clock signal OUTPUT transitioning from 'H' to 'L'.

In the period between t2 and t3, the first clock signal CLK is 'H', the second clock signal CLKB is 'L', and the voltage level of the first node Node1 rises from the lowest point and the second clock signal CLK. The voltage level of the node Node2 falls from the highest point. The comparison signal COMPS remains at 'L' until the voltage levels of the first node Node1 and the second node Node2 cross each other. The comparison signal COMPS is inputted to the XOR together with the clock signal CLK so that the clock signal OUTPUT transitions from 'L' to 'H'.

In the first triangle wave generator circuit 100, the first clock signal CLK of 'H' causes the first switch SW1 to be turned on, and the second clock signal CLKB of 'L' is the second. Make sure switch SW2 is off. The first switch SW1 allows the current supplied from the first current source I1 to be delivered to the first capacitor C1 and the first node Node1.

In the second triangle wave generator circuit 110, the second clock signal CLKB of 'L' causes the third switch SW3 to be turned off, and the first clock signal CLK of 'H' is the fourth. Make sure switch SW4 is on. As a result, the capacitor C2 and the second node Node2 are discharged through the fourth current source I4 and the fourth switch SW4.

In the interval between t3 and t4, the comparison signal COMPS transitions from 'L' to 'H' and the clock signal OUTPUT transitions from 'H' to 'L'.

As described above, the first node Node1 generates a triangular wave signal rising in the 'H' section of the first clock signal CLK and falling in the 'L' section of the first clock signal CLK. On the other hand, the second node Node2 descends in the 'H' section of the first clock signal CLK and rises in the 'L' section of the first clock signal CLK, complementarily with the first node Node1. A triangular wave signal is generated.

The triangular wave signals of the first and second nodes Node1 and Node2 are input to the comparison circuit 120 so that the comparison signal COMPPS 90 ° shifted with respect to the clock signal fi (the first clock signal) to be multiplied. To be printed. This is because capacitors C1 and C2 having good matching characteristics are connected to the first and second nodes Node1 and Node2, respectively, to generate complementary triangle wave signals. The comparison signal COMPS is a clock signal accurately shifted by 90 ° with respect to the input clock signal fi because it is a result of comparing the complementary triangle wave signals.

The comparison signal COMPS is input to an exclusive or gate XOR together with an input clock signal fi (CLK) to be multiplied. Since the exclusive or gate XOR receives the clock signal COMPPS shifted by 90 ° with respect to the input clock signal CLK, the section maintaining 'H' and the section maintaining 'L' are the same. Outputs a multiplied clock signal (OUTPUT: fo) of 50% duty.

The frequency multiplier having the configuration as described above generates a complementary triangle wave signals in response to the complementary clock signals, and compares the voltage levels of the triangle wave signals accurately by 90 ° with respect to the input clock signal CLK. Can be obtained. When the clock signal accurately shifted by 90 ° with respect to the input clock signal and the input clock signal are inputted as XOR, a clock signal having a duty of 50% having twice the frequency of the input clock signal CLK can be obtained. If the frequency multiplier having the above-described configuration is implemented in the memory chip, the circuit configuration is simpler than that of the conventional PLL, thereby reducing the area occupied by the frequency multiplier in the memory chip.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

According to the present invention as described above, a clock signal of 50% duty can be obtained accurately.

According to the present invention, the area of the frequency multiplier implemented in the memory chip can be reduced.

1 is a block diagram showing the configuration of a frequency multiplier according to the prior art;

2 is a block diagram showing a configuration of a frequency multiplier according to the present invention;

3 is a circuit diagram showing in detail the configuration of a frequency multiplier according to the present invention; And

4 is an operation timing diagram of a frequency multiplier according to clock signals.

* Description of the symbols for the main parts of the drawings *

10: phase detection circuit 12: charge pump circuit

14 loop filter 16 voltage controlled oscillation circuit

18: dividing circuit 100: first triangle wave generator circuit

110: second triangle wave generator circuit 120: comparison circuit

130: detection circuit

Claims (2)

A first triangle wave generator circuit for generating a first triangle wave signal in response to a first clock signal and a second clock signal complementary to the first clock signal; A second triangle wave generator circuit for generating a second triangle wave signal complementary to the first triangle wave signal in response to the first clock signal and the second clock signal; A comparison circuit for comparing a voltage level of the first triangle wave signal with the second triangle wave signal to generate a comparison signal; And A detection circuit for detecting whether the comparison signal and the first clock signal are at different voltage levels, The first triangle wave generator circuit, A first node for outputting the first triangle wave signal; A first current source connected between a power supply terminal receiving a power supply voltage and the first node, the first current source supplying a current; A first switch connected between the first current source and the first node and transferring a current supplied to the first current source to the first node when the first clock signal is 'H'; A first capacitor coupled between the first node and ground; A second switch connected between the first node and the ground; And And a second current source coupled between the second switch and the ground and discharging the first node with the second switch when the second clock signal is 'H'. The method of claim 1, The second triangle wave generator circuit, A second node for outputting the second triangle wave signal; A third current source connected between a power supply terminal for receiving a power supply voltage and the second node, for supplying current; A third switch connected between the third current source and the second node and transferring a current supplied to the third current source to the second node when the second clock signal is 'H'; A second capacitor connected between the second node and ground; A fourth switch connected between the second node and the ground; And And a fourth current source coupled between the fourth switch and the ground and discharging the second node with the fourth switch when the first clock signal is 'H'.