KR100800143B1 - Phase locked loop and phase locked method - Google Patents

Abstract

The present invention discloses a phase locked loop that can reduce the time that occurs during the initial locking process by adjusting the initial output clock signal. The circuit divides the reference clock signal REF_CLK and then supplies the initial voltage CKD corresponding to one period of the divided signal CK to the voltage controlled oscillator 500 so that the voltage controlled oscillator 500 An initial frequency difference between the output clock signal CLKOUT and the reference clock signal REF_CLK may be reduced.

Description

Phase Locked Loop and Phase Locked Method {PHASE LOCKED LOOP AND PHASE LOCKED METHOD}

1 is a block circuit diagram of a phase locked loop according to the prior art.

2 is a block circuit diagram of a phase locked loop according to an embodiment of the present invention.

3 is a block circuit diagram illustrating the initial voltage generator 200 of FIG. 2.

4 is a circuit diagram illustrating the controller 220 of FIG. 3.

5 is a waveform diagram illustrating an operation of the initial voltage generator 200 of FIG. 2.

The present invention relates to a phase locked loop, and more particularly, to a phase locked loop and a phase locked method capable of reducing a time occurring during an initial locking process by adjusting a frequency of an initial output clock signal.

Generally, a phase locked loop is a kind of negative feedback circuit that locks a frequency by continuously rotating the transmitted signal until it matches the reference frequency. Forcibly hold the correct fixed point to ensure that the signal remains in a certain phase.

In particular, since phase is a concept of frequency integration, the concept of phase lock and frequency lock is almost the same, so the phase lock loop is used to prevent the frequency oscillation mainly used as a frequency source in an RF system.

On the other hand, the bandwidth of the phase locked loop should be designed in consideration of both noise, speed, and stability of the circuit, but not all of them can be satisfied because there is a trade-off relationship with each other. For example, choosing a narrower frequency will ensure the noise of the input signal and the stability of the circuit, but it will take longer to lock the phase locked loop and be vulnerable to noise.

Generally, as shown in FIG. 1, the phase-locked loop determines the frequency of the output clock signal CLKOUT of the voltage controlled oscillator 40 by the voltage charged in the loop filter unit 30, and then the phase frequency. The detector 10 compares the frequency of the reference clock signal REF_CLK provided from the outside with the output clock signal CLKOUT of the voltage controlled oscillator 40 to selectively select the up pulse signal UP and the down pulse signal DN. to provide.

In addition, a current corresponding to the pulse widths of the signals UP and DN is generated in the charge pump unit 20, and the level of the voltage charged in the loop filter unit 30 is adjusted by the generated current, and the voltage is again generated. The control oscillator 40 is provided.

As described above, the conventional phase locked loop compares the frequency difference between the output clock signal CLKOUT and the reference clock signal REF_CLK having a frequency corresponding to the voltage charged in the loop filter unit 30, and then outputs the output clock signal ( The above operation is repeated until the frequency difference between CLKOUT and the reference clock signal REF_CLK falls within a predetermined range.

In this case, in the conventional phase locked loop, the frequency difference between the output clock signal CLKOUT and the reference clock signal REF_CLK initially generated by the voltage controlled oscillator 40 determines the initial lock acquisition of the phase locked loop. If the frequency difference between the initial output clock signal CLKOUT and the reference clock signal REF_CLK is large, the locking time of the phase locked loop is increased.

Accordingly, an object of the present invention is to reduce the locking time of the phase locked loop by reducing the frequency difference between the reference clock signal and the initial output clock signal.

The phase locked loop for achieving the above object includes a phase frequency detector for generating a pulse signal by comparing the externally provided reference clock signal and the feedback output clock signal; An initial voltage generator for dividing the reference clock signal to generate a divided signal and providing an initial voltage corresponding to one period of the divided signal; A charge pump unit generating a current proportional to a pulse width of the pulse signal; A loop filter unit charging the initial voltage and adjusting and providing a level of the initial voltage by a current generated from the charge pump unit; And a voltage controlled oscillator for outputting the output clock signal having a frequency corresponding to the voltage provided to the loop filter unit.

In the above configuration, the initial voltage generator comprises: a divider for dividing the reference clock signal to generate the divided signal; A controller which is enabled during an initial operation and generates a control signal that is disabled at the end of one period of the divided signal; And an output unit configured to charge the predetermined voltage while the control signal is in an enabled state and to provide the charged voltage as the initial voltage when the control signal is disabled.

In the above configuration, the division unit divides the reference clock signal by two to generate the division signal having a period twice as long as the reference clock signal.

In the above configuration, the divider may be configured as a D flip-flop that receives the reference clock signal through a clock input terminal and has an input terminal and an inverted output terminal connected to each other.

In the above configuration, the control unit includes: interval setting means for setting an operation section of the initial voltage generator by latching a predetermined voltage by a power-up signal for an initial operation; A D flip-flop initialized by the power up signal and outputting the control signal synchronized with an edge of the divided signal at an inverted output terminal; Combining means for logically combining the signal latched by the interval setting means and the control signal to an input terminal of the D flip-flop; And a pulse generating means for generating a pulse when the output signal of the control state in the inverted output terminal of the D flip-flop is output to the section setting means.

In the above configuration, the interval setting means includes: first switching means for switching by the power up signal to selectively provide a power supply voltage to a first node; Second switching means for switching by the output of said pulse generating means to selectively provide said power supply voltage to a second node which is an output node; And cross-coupled latch means for latching the potentials of the first and second nodes, respectively.

In the above configuration, the D flip-flop preferably has a rising edge trigger structure for outputting the control signal synchronized with the rising edge of the divided signal.

In the above configuration, the combining means includes: a first AND gate for AND combining a signal latched by the interval setting means and a signal in phase with the control signal; An inverter for inverting the phase of the signal latched by the section setting means; A second AND gate for AND-combining the signal whose phase is inverted by the inverter and the control signal; And an ora gate configured to ora-combine the signals combined and combined in the first and second AND gates to deliver the input signals to the input terminal of the D flip-flop.

In the above configuration, the output unit includes conversion means for converting the divided signal into a predetermined analog voltage; Switching means for switching by said control signal to selectively provide a predetermined voltage supplied from said conversion means; And a capacitor means for charging the predetermined voltage supplied from the conversion means when the switching means is turned on, and providing the charged voltage as the initial voltage when the switching means is turned off.

In the above configuration, the converting means comprises: pull-up means for switching by the divided signal to selectively provide a power supply voltage; And pull-down means for switching by the division signal to selectively provide a ground voltage.

A phase locked loop that receives feedback of an output clock signal for achieving the above object and compares it with an externally provided reference clock signal to compensate for a frequency difference between the output clock signal and the reference clock signal includes: A division unit for dividing to generate a division signal; A controller which is enabled during an initial operation and generates a control signal that is disabled at the end of one period of the divided signal; And an output unit which charges a predetermined voltage while the control signal is in an enabled state, and provides the charged voltage as an initial voltage when the control signal is disabled, and corresponds to the initial voltage during an initial operation. It is characterized by providing a frequency to the output clock signal.

In the above configuration, the division unit divides the output clock signal by two to generate the division signal having a period twice as long as the output clock signal.

In the above configuration, the divider may be configured as a D flip-flop which receives the output clock signal through a clock input terminal and has an input terminal and an inverted output terminal connected to each other.

In the above configuration, the control unit includes: interval setting means for setting an operation section of the initial voltage generator by latching a predetermined voltage by a power-up signal for an initial operation; A D flip-flop initialized by the power up signal and outputting the control signal synchronized with an edge of the divided signal at an inverted output terminal; Combining means for logically combining the signal latched by the interval setting means and the control signal to an input terminal of the D flip-flop; And a pulse generating means for generating a pulse when the output signal of the control state in the inverted output terminal of the D flip-flop is output to the section setting means.

In the above configuration, the interval setting means includes: first switching means for switching by the power up signal to selectively provide a power supply voltage to a first node; Second switching means for switching by an output of said pulse generating means to selectively provide said power supply voltage to a second node which is an output node; And cross-coupled latch means for latching potentials of the first and second nodes.

In the above configuration, the D flip-flop preferably has a rising edge trigger structure for outputting the control signal synchronized with the rising edge of the divided signal.

In the above configuration, the combining means includes: a first AND gate for AND combining a signal latched by the interval setting means and a signal in phase with the control signal; An inverter for inverting the phase of the signal latched by the section setting means; A second AND gate for AND-combining the signal whose phase is inverted by the inverter and the control signal; And an ora gate configured to ora-combine the signals combined and combined in the first and second AND gates to deliver the input signals to the input terminal of the D flip-flop.

In the above configuration, the output unit includes conversion means for converting the divided signal into a predetermined analog voltage; Switching means for switching by said control signal to selectively provide a predetermined voltage supplied from said conversion means; And a capacitor means for charging the predetermined voltage supplied from the conversion means when the switching means is turned on, and providing the charged voltage as the initial voltage when the switching means is turned off.

In the above configuration, the converting means comprises: pull-up means for switching by the divided signal to selectively provide a power supply voltage; And pull-down means for switching by the division signal to selectively provide a ground voltage.

The phase lock method for achieving the above object comprises a first step of dividing an externally provided reference clock signal as a divided signal; A second step of providing an initial voltage corresponding to a period of the divided signal; Providing an output clock signal having a frequency corresponding to the initial voltage; A fourth step of receiving the output clock signal and comparing the frequency of the output clock signal with the reference clock signal to generate a pulse signal; And a fifth step of adjusting the level of the initial voltage according to the pulse signal.

In the above method, the first step divides the reference clock signal by two to provide the divided signal having a period twice as long as the reference clock signal.

In the method, the second step may be to charge the predetermined voltage for one period of the divided signal, and then provide the charged voltage as the initial voltage until the end of one period of the divided signal.

In the method, the second step charges a power supply voltage while the divided signal is in an enabled state, then discharges the charged voltage to ground while the divided signal is in a disabled state, and the divided signal is again in It is preferable to provide a charged voltage as the initial voltage at the time when it becomes an enable state.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

According to an embodiment of the present invention, the circuit of FIG. 2 is provided. The embodiment of the present invention divides the reference clock signal REF_CLK, and then converts the initial voltage CKD corresponding to one period of the divided signal into a voltage controlled oscillator. 500, the frequency difference between the output clock signal CLKOUT and the reference clock signal REF_CLK initially generated by the voltage controlled oscillator 500 may be reduced.

In detail, the embodiment of FIG. 2 compares the frequency of the reference clock signal REF_CLK and the fed back output clock signal CLKOUT to selectively output an up pulse signal UP and a down pulse signal DN. 100, an initial voltage generator 200 generating an initial voltage CKD using the reference clock signal REF_CLK, a current IP and IN by an up pulse signal UP and a down pulse signal DN. After generating the charge pump unit 300 to control the amount of charge charged in the loop filter unit 400, the initial voltage (CKD), and then adjust the voltage (VC) level by the charge pump unit 300 to output And a voltage controlled oscillator 500 for outputting an output clock signal CLKOUT corresponding to the voltage applied by the loop filter 400.

According to the exemplary embodiment of the present invention, the initial voltage generator 200 divides the reference clock signal REF_CLK from the initial voltage generator 200 and charges a predetermined voltage for one period of the divided signal CK. To provide.

In this case, as shown in FIG. 3, the initial voltage generator 200 divides the reference clock signal REF_CLK and outputs the divided signal CK, which is enabled and initially divided. When the control signal (INIT) is disabled after charging a predetermined voltage by the control unit (220) for generating the control signal (INIT) that is disabled at the end of one cycle of (CK) and the divided signal (CK) The output unit 230 provides the charged voltage as the initial voltage CKD.

Here, the divider 210 divides the reference clock signal REF_CLK by 'n' (n is a natural number of 2 or more) and outputs the divided signal CK. In an embodiment of the present invention, the reference clock signal REF_CLK is an example. Is divided into 2 and used as the division signal CK. To this end, the divider 210 receives a reference clock signal REF_CLK as a clock input terminal and constitutes a rising edge triggered D flip-flop D_FF1 having an input terminal D and an inverted output terminal Qb connected to each other. Can be.

In addition, the output unit 230 is connected to the output states of the PMOS and NMOS transistors P1 and N1 and the PMOS and NMOS transistors P1 and N1 that selectively perform pull-up and pull-down operations by the divided signal CK. Accordingly, the PMOS and NMOS transistors P2 and N2 and the control signal INIT output from the controller 220 selectively perform pull-up and pull-down operations, respectively, selectively between the node ND1 and the node ND2. The NMOS transistor N3 to be connected and the predetermined voltage supplied from the PMOS and the NMOS transistors P2 and N2 when the NMOS transistor N3 is turned on and then the charged voltage when the NMOS transistor N3 is turned off are charged. The capacitor C3 may be configured to provide the initial voltage CKD.

And, the control unit 220, as shown in Figure 4, the NMOS transistor (N4) for selectively supplying the power supply voltage (VDD) to the node (ND3) by the power-up signal (PWRUP); PMOS transistors P3 and P4 and NMOS transistors N5 and N6 connected in a cross-coupled form to latch the potentials of the node ND3 and the node ND4; An NMOS transistor N7 which selectively supplies the power supply voltage VDD to the node ND4 by the pulse RISE generated by the pulse generator 221; An AND gate AN1 that AND-combines the signal CTRL and the inversion control signal INITB output from the output terminal Q of the D flip-flop D_FF2; An inverter IV inverting the phase of the signal CTRL; An AND gate AN2 for and combining the signal inverted by the inverter IV with the control signal INIT output from the inverted output terminal QB of the D flip-flop D_FF2; An OR gate OR for combining the AND-combined signals at the AND gates AN1 and AN2, respectively; A reset terminal for receiving the power-up signal PWRUP, an input terminal D for receiving a combined signal from the OR gate OR, a clock input terminal for receiving a division signal CK, and an inverting control signal INITB. A rising edge triggered D flip-flop D_FF2 having an output terminal Q for outputting and an inverting output terminal QB for outputting a control signal INIT; And a pulse generator 221 generating a pulse RISE when the control signal INIT is disabled.

An operation of the initial voltage generator 200 having such a configuration will be described in detail with reference to FIGS. 3 to 5. First, the divided signal CK divided by the D flip-flop D_FF1 of the divider 210 is controlled. D flip-flop D_FF2 of 220.

In the D flip-flop D_FF2, when the power-up signal PWRUP signal is enabled, the power-up signal PWRUP in the enabled state is input to the reset terminal and the output of the output terminal Q is set to a low level. The control signal INIT output from the inverting output terminal QB has a high level state.

In addition, when the power-up signal PWRUP is enabled, the NMOS transistor N4 is turned on so that the potential of the node ND3 rises to a power supply level, and the PMOS and NMOS transistors P3, P4, The signals CTRL are brought low by N5 and N6.

Thereafter, the signal CTRL, the signal inverted by the inverter IV, the control signal INIT initially set in the D flip-flop D_FF2, and the inversion control signal INITB are connected to the two AND gates AN1 and AN2. The logic is combined through the OR gate OR to be transmitted to the input terminal D of the D flip-flop D_FF2 as a low level signal.

That is, the control signal INIT output from the inverted output terminal of the D flip-flop D_FF2 is enabled from the time when the power-up signal PWRUP is enabled, and the control signal INIT is enabled. In the meantime, the capacitor C3 is charged with a predetermined voltage by the PMOS and NMOS transistors P2 and N2 of the output unit 230.

At this time, the capacitor C3 of the output unit 230 charges the power supply voltage VDD when the divided signal CK is at the high level, and then discharges the charged voltage to ground when the divided signal CK is at the low level. do.

Thereafter, when the power-up signal PWRUP is disabled, a high level signal is input to the input terminal D of the D flip-flop D_FF2, and the input high level signal is a D flip-flop of a rising edge trigger method. The output signal is output as the control signal INIT in the disabled state at the rising edge at the end of one cycle of the divided signal CK by D_FF2.

When the control signal INIT is disabled, since the NMOS transistor N3 of the output unit 230 is turned off to cut off the current flowing between the node ND1 and the node ND2, the capacitor C3 is controlled by the control signal ( The voltage charged while INIT is enabled is provided to the loop filter unit 400 as the initial voltage CKD.

In this case, as shown in FIG. 5, the capacitor C3 of the output unit 230 may have a difference in the amount of charges charged according to one period of the divided signal CK. For example, the divided signal CK may have a period. In the case of the short signal CKH, the voltage CKDH provided to the loop filter unit 400 has a level higher than that of the initial voltage CKD, and the loop filter unit when the divided signal CK is a long signal CKL. The voltage CKDL provided to 400 has a level lower than the initial voltage CKD.

The loop filter unit 400 receives the initial voltage CKD provided from the initial voltage generator 200 through the resistor R and two capacitors C1 and C2, and the loop filter unit 500 controls the loop filter. The initial output clock signal CLKOUT having a frequency proportional to the initial voltage CKD supplied to the unit 400 is output.

The initial output clock signal CLKOUT is fed back to the phase frequency detector 100 and compared with the frequency of the reference clock signal REF_CLK. In the phase frequency detector 100, the frequency of the initial output clock signal CLKOUT is referenced to the reference clock. When the frequency of the initial output clock signal CLKOUT is higher than the frequency of the reference clock signal REF_CLK, the up pulse signal UP is generated when it is lower than the frequency of the signal REF_CLK. do.

In the charge pump unit 300, when the up pulse signal UP is generated by the phase frequency detector 100, an amount of the current IP corresponding to the pulse width of the up pulse signal UP is further added to the loop filter unit 400. When the down pulse signal DN is generated by the phase frequency detection unit 100, the charge charged in the loop filter unit 400 is grounded by an amount of current IN corresponding to the pulse width of the down pulse signal DN. Release.

Thereafter, the exemplary embodiment of the present invention repeats the above operation until the frequency of the output clock signal CLKOUT output from the voltage controlled oscillator 500 approaches the frequency of the reference clock signal REF_CLK. At this time, the initial voltage generator 200 is activated only during the initial operation, and is maintained in an inactive state in subsequent operations.

In an operation of matching the frequency of the output clock signal CLKOUT with the frequency of the reference clock signal REF_CLK, an embodiment of the present invention has a frequency in which the initial output clock signal CLKOUT corresponds to the initial voltage CKD. Therefore, the frequency difference between the output clock signal CLKOUT and the reference clock signal REF_CLK input to the initial phase frequency detector 100 is not large.

That is, according to the exemplary embodiment of the present invention, the reference clock signal REF_CLK is divided to generate the divided signal CK, and then the initial voltage CKD corresponding to the period of the divided signal CK is transferred to the voltage controlled oscillator 500. to provide.

Therefore, in the embodiment of the present invention, since the frequency of the output clock signal CLKOUT input to the phase frequency detector 100 during initial operation does not differ significantly from the frequency of the reference clock signal REF_CLK, the initial lock acquisition time can be reduced. .

As described above, the present invention divides the reference clock signal REF_CLK to generate the divided signal CK, and then provides the voltage controlled oscillator 500 with the initial voltage CKD corresponding to the period of the divided signal CK. Therefore, the locking time of the phase locked loop can be reduced.

While the invention has been shown and described with reference to specific embodiments, the invention is not limited thereto, and the invention is not limited to the scope of the invention as defined by the following claims. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (23)

A phase frequency detector for generating a pulse signal by comparing an externally provided reference clock signal with a feedbacked output clock signal; An initial voltage generator for dividing the reference clock signal to generate a divided signal and providing an initial voltage corresponding to one period of the divided signal; A charge pump unit generating a current proportional to a pulse width of the pulse signal; A loop filter unit charging the initial voltage and adjusting and providing a level of the initial voltage by a current generated from the charge pump unit; And And a voltage controlled oscillator for outputting the output clock signal having a frequency corresponding to the voltage provided to the loop filter unit. The method of claim 1, The initial voltage generator, A divider for dividing the reference clock signal to generate the divided signal; A controller which is enabled during an initial operation and generates a control signal that is disabled at the end of one period of the divided signal; And And an output unit which charges the predetermined voltage while the control signal is in an enabled state, and provides the charged voltage as the initial voltage when the control signal is disabled. The method of claim 2, And the division unit divides the reference clock signal into two to generate the divided signal having a period twice as large as that of the reference clock signal. The method of claim 3, wherein And the divider receives the reference clock signal through a clock input terminal, and includes a D flip-flop connected to an input terminal and an inverted output terminal. The method of claim 2, The control unit, Section setting means for setting an operation section of the initial voltage generator by latching a predetermined voltage by a power-up signal for an initial operation; A D flip-flop initialized by the power up signal and outputting the control signal synchronized with an edge of the divided signal at an inverted output terminal; Combining means for logically combining the signal latched by the interval setting means and the control signal to an input terminal of the D flip-flop; And And a pulse generating means for generating a pulse when the output signal of the control state in the inverted output terminal of the D flip-flop is output to the section setting means. The method of claim 5, wherein The section setting means, First switching means for switching by said power up signal to selectively provide a power supply voltage to a first node; Second switching means for switching by an output of said pulse generating means to selectively provide said power supply voltage to a second node which is an output node; And And a phase coupled latch means for latching the potentials of the first and second nodes. The method of claim 5, wherein And the D flip-flop has a rising edge trigger structure for outputting the control signal synchronized with the rising edge of the divided signal. The method of claim 5, wherein The combining means, A first AND gate for AND-combining a signal latched by the interval setting means and a signal whose phase is opposite to the control signal; An inverter for inverting the phase of the signal latched by the section setting means; A second AND gate for AND-combining the signal whose phase is inverted by the inverter and the control signal; And And an ora gate configured to orally combine the AND-combined signals at the first and second AND gates to deliver the input signals to the input terminal of the D flip-flop. The method of claim 2, The output unit, Conversion means for converting the divided signal into a predetermined analog voltage; Switching means for switching by said control signal to selectively provide a predetermined voltage supplied from said conversion means; And And a capacitor means for charging the predetermined voltage supplied from the conversion means when the switching means is turned on, and providing the charged voltage as the initial voltage when the switching means is turned off. . The method of claim 9, The conversion means, Pull-up means for switching by the division signal to selectively provide a power supply voltage; And And a pull-down means for switching by the division signal to selectively provide a ground voltage. A phase locked loop for receiving an output clock signal and comparing the output clock signal with a reference clock signal provided from an external source to compensate for a frequency difference between the output clock signal and the reference clock signal. A divider for dividing the reference clock signal to generate a divided signal; A controller which is enabled during an initial operation and generates a control signal that is disabled at the end of one period of the divided signal; And And an output unit configured to charge a predetermined voltage while the control signal is in an enabled state and to provide the charged voltage as an initial voltage when the control signal is disabled. And a phase corresponding to the initial voltage is provided to the output clock signal during initial operation. The method of claim 11, And the division unit divides the output clock signal into two to generate the division signal having a period twice as long as the output clock signal. The method of claim 12, And the division unit receives the output clock signal through a clock input terminal, and includes a D flip-flop connected to an input terminal and an inverted output terminal. The method of claim 11, The control unit, Section setting means for setting an operation section of the initial voltage generator by latching a predetermined voltage by a power-up signal for an initial operation; A D flip-flop initialized by the power up signal and outputting the control signal synchronized with an edge of the divided signal at an inverted output terminal; Combining means for logically combining the signal latched by the interval setting means and the control signal to an input terminal of the D flip-flop; And And a pulse generating means for generating a pulse when the output signal of the control state in the inverted output terminal of the D flip-flop is output to the section setting means. The method of claim 14, The section setting means, First switching means for switching by said power up signal to selectively provide a power supply voltage to a first node; Second switching means for switching by an output of said pulse generating means to selectively provide said power supply voltage to a second node which is an output node; And And a phase coupled latch means for latching the potentials of the first and second nodes. The method of claim 14, And the D flip-flop has a rising edge trigger structure for outputting the control signal synchronized with the rising edge of the divided signal. The method of claim 14, The combining means, A first AND gate for AND-combining a signal latched by the interval setting means and a signal whose phase is opposite to the control signal; An inverter for inverting the phase of the signal latched by the section setting means; A second AND gate for AND-combining the signal whose phase is inverted by the inverter and the control signal; And And an ora gate configured to orally combine the AND-combined signals at the first and second AND gates to deliver the input signals to the input terminal of the D flip-flop. The method of claim 11, The output unit, Conversion means for converting the divided signal into a predetermined analog voltage; Switching means for switching by said control signal to selectively provide a predetermined voltage supplied from said conversion means; And And a capacitor means for charging the predetermined voltage supplied from the conversion means when the switching means is turned on, and providing the charged voltage as the initial voltage when the switching means is turned off. . The method of claim 18, The conversion means, Pull-up means for switching by the division signal to selectively provide a power supply voltage; And And a pull-down means for switching by the division signal to selectively provide a ground voltage. A first step of dividing an externally provided reference clock signal as a divided signal; A second step of providing an initial voltage corresponding to a period of the divided signal; Providing an output clock signal having a frequency corresponding to the initial voltage; A fourth step of receiving the output clock signal and comparing the frequency of the output clock signal with the reference clock signal to generate a pulse signal; And And a fifth step of adjusting the level of the initial voltage according to the pulse signal. The method of claim 20, And the first step divides the reference clock signal into two and provides the divided signal having a period twice as large as that of the reference clock signal. The method of claim 20, In the second step, the predetermined voltage is charged for one period of the divided signal, and then the charged voltage is provided as the initial voltage until the end of one period of the divided signal. The method of claim 22, In the second step, after the power supply voltage is charged while the divided signal is in the enabled state, the charged voltage is discharged to the ground while the divided signal is in the disabled state, and the divided signal is enabled again. And a voltage charged at a time point as the initial voltage.

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