KR100567147B1 - Data transmission method and device - Google Patents

Abstract

The first bus 11 and the second bus 12 are connected via a bus repeater 13 having a buffer memory, and each of the buses 11 and 12 has a DMA (direct memory access) controller 22, 27. Connected. The bus repeater 13 can output DMA requests to the respective DMA controllers 22 and 27, and can mask their DMA requests by the respective CPUs 22 and 27. The DMA controller 22 transfers the data on the bus 11 between the buffer memories in the bus repeater 13 and the DMA controller 27 transfers the DMA between the buffer memory and the bus 12. The CPU 22 can check the DMA function by masking the DMA request of the bus repeater 13 and directly accessing the buffer. This facilitates debugging a system that transfers DMA through a buffer between different buses.

Description

Data transmission method and device

The present invention relates to a data transfer method and apparatus for transferring data between a device or a memory respectively connected to two different buses, and more particularly, to a data transfer method capable of diagnosing whether data transfer is functioning normally. Relates to the device.

Background Art Conventionally, it is known to connect other buses such as a main bus and a subbus through a bus repeater such as a gateway, and perform DMA transfer of data between these buses by a DMA (direct memory access) controller provided in the main bus. .

For example, in the structure shown in FIG. 1, the main bus 101 and the sub bus 102 are each connected to the bus repeater 103, such as a bus gateway. The main bus 101 is connected with devices 104 such as a CPU and various interfaces, and a DMA controller 105, and the sub-bus 102 is connected with a device 106 and a memory 107 such as a ROM.

In the example of FIG. 1, the DMA controller 105 on the main bus 101 also controls the sub-bus 102 via the bus repeater 103, for example, between the device 104 and the device 106. DMA transfer is realized. In this manner, even if the access times of the respective buses are the same between the different buses 101 and 102, there is no unnecessary waiting time and efficient data transfer can be performed.

By the way, when different buses coexist in one system, the bus width and data access speed are often different. For example, in the example of FIG. 1, the main bus 101 is 32 bits wide and the high-speed sub-bus 102 is used. ) Is 16 bits wide and slow.

As described above, when DMA transfer is performed between buses having different bus widths or data access rates, there is a drawback that unnecessary latency is generated on a high-speed bus, for example, the main bus 101 of FIG.

Therefore, it is considered to connect between two different buses through a buffer memory and perform a DMA transfer through this buffer memory, but if you want to diagnose whether the DMA transfer is functioning normally, run the CPU of each bus in debug mode. It is cumbersome to have to.

In addition, in the case where data transfer is not performed normally, it is assumed that the CPU and the diagnostic program of both buses are defective, so that the cause is often very difficult to find.

In particular, when a CPU, a DMA controller, or the like is installed in one LSI, a long development period is required, and a schedule of diagnosis is a big problem.

Before actually starting the design of the LSI, software simulations including peripherals are used to verify as many functions as possible.However, the simulation takes time, so sufficient verification cannot be performed, and the problem is investigated shortly after the start LSI is made. Because of the fact that this must be done, the above difficulty of debugging is often a bottleneck for product development.

In addition, when data is transferred between devices, there is a proper arrangement of data for each device, and in order to cope with this, it is necessary to separate the extra data or insert another data between the transmitted data strings. There is.

When the CPU intends to perform the above operation on the data string developed on the memory, it is very inefficient because the CPU must read the register once and then write it again, which reduces the time that the CPU wants to do other work. It may or may not be desirable.

It is also contemplated that the DMA controller changes the transfer source address or transfer destination address each time during data transfer, in which case a list of transfer source addresses and transfer amounts is prepared and the DMA controller transfers the DMA according to the list each time. However, the CPU has to prepare the transfer specification table, and there is an overhead such as an overhead to check the transfer specification each time.

In addition, when different buses coexist in one system as described above, the bus widths are often different. For example, in the example of FIG. 1, the main bus 101 is 32 bits wide and the high-speed subbus 102 is used. Is slow at 16 bits wide. Even when DMA transfers are made between buses with different bus widths in this way, extra data may be removed or other data may be inserted between the transferred data strings. It is desirable to be able to do this.

1 is a block diagram showing a conventional example of a system using two buses.

2 is a block diagram showing a schematic configuration of an embodiment of the present invention.

3 is a block diagram showing an example of an internal configuration of a bus repeater used in an embodiment of the present invention.

4 is a flowchart for explaining an example of the operation of the embodiment of the present invention.

5 is a flowchart for explaining another example of the operation of the embodiment of the present invention.

6 is a diagram illustrating a specific example of a data string before transmission.

Fig. 7 is a diagram showing a specific example of a data string obtained by omitting part of the transfer.

Fig. 8 is a diagram showing a specific example of a data string obtained by adding other data at the time of transmission.

9 is a diagram illustrating an example of a data area to be transmitted on a texture image.

10 is a diagram showing the data arrangement on the memory of FIG.

11 is a diagram illustrating an example in which a header is added to some data columns.

FIG. 12 is a diagram showing a specific example of the header added in FIG. 11. FIG.

13 is a block diagram illustrating an example of a system to which an embodiment of the present invention is applied.

(Initiation of invention)

SUMMARY OF THE INVENTION The present invention has been made in view of such a situation, and an object thereof is to provide a data transfer method and apparatus in which a diagnosis of a DMA transfer function can be easily performed between two different buses, and a problem location can be specified in a short time. do.

Another object of the present invention is to provide a data transfer method capable of simply changing the size of a transfer data block without burdening the CPU when transferring data between two different buses, and improving work efficiency. To provide a device.

In other words, the present invention provides a bus relay means having a first bus and a second bus, a buffer memory connected to the first bus and a second bus, and a first bus connected to the first bus to solve the above problems. One DMA (direct memory access) control means, a first data processing means (CPU) connected to the first bus, the bus relay means for outputting a DMA request to the first DMA control means; And having a function of masking this DMA request by the first data processing means, masking the DMA request of the bus relay means by the first data processing means, and directly accessing the buffer memory in the bus relay means. I am doing it.

Here, a second DMA (direct memory access) control means and a second data processing means (CPU) are connected to the second bus, and the first and second DMA control means provide data to the buffer memory in the bus relay means. Reading / writing the data to transfer data between the first and second buses, and the bus relaying means outputs a DMA request to the second DMA control means, and transmits the DMA request to the second data. And a function of masking by the processing means, masking the DMA request of the bus relaying means by the second data processing means, and directly accessing the buffer memory in the bus relaying means.

In this case, one of the first and second data processing means (CPUs) masks the DMA request on the other bus in the bus repeater, and the buffer memory in the bus repeater on the other bus. And access.

In addition, the present invention connects the first bus and the second bus to each other via a bus relay means having a buffer memory, and connects a first DMA (direct memory access) control means to the first bus. The second DMA control unit is connected to each other, and the DMA transfer is performed between the memory or device connected to the first bus and the memory or device connected to the second bus by these first and second DMA control means. The DMA request from the bus relay means to the first or second DMA control means by a data processing means (CPU) and the buffer in the bus relay means by the data processing means. And access the memory directly.

In this case, a first data processing means is provided on the first bus, a second data processing means is provided on the second bus, and the first data processing means masks a DMA request on the first bus. The second data processing means masks a direct memory access request on a two bus, and the first and second data processing means are subject to the bus repeater with the same transfer conditions as the first and second direct memory access control means on each bus. Direct access to the buffer memory therein.

The first data processing means masks a DMA request on the second bus, and the first data processing means directly accesses the buffer memory in the bus repeater on the second bus side.

Between each memory or device on another bus through this buffer memory by DMA transfer between the memory or device on each bus by means of each DMA control means on the first and second buses and the buffer memory of the bus relay means. DMA transfer at At this time, the DMA function can be checked by masking the DMA request on each bus by the data processing means (CPU) on each bus and directly accessing the buffer memory. The data processing means on the first bus can also check the DMA function of the second bus by masking the DMA request on the second bus and accessing the buffer memory on the second bus side.

In addition, the present invention is to solve the above problems by connecting different first bus and second bus via a bus intermediation means having a buffer memory and the data transfer between the first bus and the second bus; Via the buffer memory in the bus relay means, the bus relay means increases the size of the transmission data block by adding dummy data at the time of data transfer, or the bus relay means at the time of data transfer. The size of the transmission data block is reduced by omitting some data.

Here, data transfer control is performed between the first bus and the buffer memory in the bus relay means by a first direct memory access control means connected to the first bus, and a second direct memory access connected to the second bus. And controlling data transfer between the second bus and the buffer memory in the bus relay means by the control means. In addition, the bus relay means increases the size of the transfer data block by outputting dummy data when there is an output request, even if data in the buffer memory is lost during data transfer, or the data transfer on the output side is terminated at the time of data transfer. In this case, when the data in the buffer memory remains, discarding the remaining data reduces the size of the transfer data block.

By adding a function such as increasing or decreasing the block size of the transmission data to the bus repeater which relays the transmission, a simple data configuration can be changed during data transmission.

Best Mode for Carrying Out the Invention

EMBODIMENT OF THE INVENTION Hereinafter, embodiment which concerns on this invention is described, referring drawings.

2 is a block diagram showing a system configuration to which the data transmission method according to the embodiment of the present invention is applied.

In FIG. 2, the first bus 11 and the second bus 12 are respectively connected to a bus repeater 13 made of a buffer memory such as a FIFO, and the bus 11, via the bus repeater 13. 12) Data can be transferred between each other. The first bus 11 is connected with a CPU 21, a DMA (direct memory access) controller 22, a device 23, a memory 24, and the like, and the second bus 12 is provided with a CPU 26, The DMA controller 27, the device 28, the memory 29, and the like are connected.

The device 23 can output the DMA request to the DMA controller 22 and the device 28 to the DMA controller 27, respectively. These devices 23 and 28 are, for example, encoders and decoders for images and audio, graphics engines for graphics processing, image processing and audio processing ICs, or the like, or hard disk devices, magneto-optical disk devices, floppy disks via respective interfaces. Peripheral devices such as devices and CD-ROM devices. The bus repeater 13 may output a DMA request (DREQ) to the DMA controllers 22 and 27, respectively. These DMA requests can specify which DMA channel among a plurality of DMA channels. In addition, the bus repeater 13 outputs a request for use of the bus 12 (BREQ: bus request) to the CPU 26 on the bus 12, for example. A BACK (bus acknowledgment) can be received.

An example of the structure of the bus repeater 13 used for such a system of FIG. 2 is shown in FIG. In Fig. 3, the first bus 11 of Fig. 2 is divided into a data bus 11a and an address control bus 11b, and the second bus 12 is divided into a data bus 12a and an address control. The figure is divided into buses 12b. In the bus repeater 13, an internal bus 31 connected to the data bus 11a of the first bus 11 and an internal bus 32 connected to the data bus 12a of the second bus 12 are provided. FIFO (first in first out) memory 33 is connected to these internal buses 31 and 32. The buffer control unit 34 may also be connected to these internal buses 31 and 32. The buffer control unit 34 is also connected to the address control bus 11b of the first bus 11 and the address control bus 12b of the second bus. Further, a control signal line for making a DMA request (DREQ), a channel designation, or the like is connected to the buffer control unit 34 with the DMA controllers 22 and 27 shown in FIG.

The mask flag 35 is a flag for prohibiting DMA on the bus 11 side, and when the flag is set to ON or " 1 " under the control of the CPU 21 in FIG. The DMA request DREQ is not output to the DMA controller 22 of 2. The mask flag 36 is a flag for prohibiting DMA on the bus 12 side, and when the flag is set to ON or " 1 " The DMA request DREQ to the DMA controller 27 is not output.

The DREQ bits 37 and 38 are flags indicating ON / OFF (or "1" / "0") of DMA requests for the respective buses 11 and 12, and from either of the CPUs 21 and 22, respectively. Can be read. The flags of these DREQ bits 37 and 38 are not masked even when the mask flags 35 and 36 are ON, and appear in the DMA request (DREQ) from the bus repeater 13 to the respective DMA controllers 22 and 27. The status of the unsuccessful DMA request can be read by each of the CPUs 21 and 26.

The bus gateway 39 connects the internal buses 31 and 32 for the CPU 21 on the bus 11 side of FIG. 2 to access the bus 12. These mask flags 35 and 36, the DREQ bits 37 and 38 and the bus gateway 39 are connected to the buffer control unit 34.

In the bus repeater 13 shown in FIG. 3, the FIFO memory 33 is a memory serving as a buffer, and the buses 11 and 12 accessed by the bus control unit 34, that is, internal buses connected to them. Input / output of data is controlled for (31, 32). The buffer control unit 24 controls the bus access operation of the FIFO memory 33 and outputs a DMA request (DREQ) to the DMA controllers 22 and 27 of the respective buses 11 and 12, and responds thereto. (DACK: DMA acknowledge) is received. This DMA request can designate and output one of a plurality of DMA channels. DMA channel selection information from the DMA controllers 22 and 27 is also sent to this buffer control unit 34.

Further, for example, when the CPU 21 accesses the address of the bus 12, the buffer control unit 34 of the bus repeater 13 causes the CPU 26 of the bus 12 to use the right to use the bus 12. Print a request (BREQ). The CPU 26 sends a buffer acknowledgment (BACK: bus acknowledgment) to the buffer control unit 34 of the bus repeater 13 in accordance with this bus request. The CPU 21 then has a mask flag 36 on the internal bus 32 side of the bus repeater 13, a FIFO 33 and a DMA controller 27 on the bus 12, a device 28, a memory ( 29) and the like.

By the way, when DMA transfer is performed between the first bus 11 and the second bus 12 via the bus repeater 13, the DMA setting of the DMA controllers 22 and 27 (e.g., data size, etc.) It is necessary to respond without this contradiction. The CPU 21 sets the DMA on the respective buses for the DMA controller 22 and the CPU 26 for the DMA controller 27.

For example, when data transfer is performed by the DMA from the memory 24 of the first bus 11 to the memory 28 of the second bus 12, the DMA controller 22 of the first bus 11 is used. The same data size (data amount) for DMA from the memory 24 to the bus repeater 13 and for the DMA from the bus repeater 13 to the memory 29 in the DMA controller 27 of the second bus 12, respectively. It is necessary to set so as to become a corresponding DMA channel. The processing sequence after these settings are as shown in FIG.

In FIG. 4, the bus repeater 13 makes a DMA request (DREQ) to the DMA controller 22 in the first step S61. In the next step S62, the DMA controller 22 requests (BREQ) the license for the bus 11 from the CPU 21, receives the bus license, and transfers the DMA from the memory 24 to the bus repeater 13. do. In the next step S63, the bus repeater 13 makes a DMA request (DREQ) to the DMA controller 27. In the next step S64, the DMA controller 27 requests (BREQ) the license for the bus 12 from the CPU 26, receives the bus license, and transfers the DMA from the bus repeater 13 to the memory 29. do.

In addition, when DMA transfers data from the device 28 on the second bus 12 to the device 23 on the first bus 11, the DMA controller 27 transfers the data from the device 28 to the bus repeater 13. For DMAs, the DMA controller 22 also needs to be set so that the DMA channels corresponding to the DMAs from the bus repeater 13 to the device 23 each have the same data size. The processing sequence after these settings are as shown in FIG.

In the first step S71 of FIG. 5, the device 28 on the second bus 12 issues a DMA request (DREQ) to the DMA controller 27. In the next step S72, the bus repeater 13 issues a DMA request (DREQ) to the DMA controller 27. In step S73, the DMA controller 27 makes a request (BREQ) of the usage right of the bus 12 to the CPU 26 in response to receiving respective DMA requests from the device 28 and the bus repeater 13. It receives the bus right to use and performs DMA transfer from the device 28 to the bus repeater 13. At this time, the CPU 26 returns the response when the bus is opened in response to the bus request BREQ to the DMA controller 27, and the DMA controller 27 returns the DMA response (DACK) to the bus relay 13 or the like. Is the same as a normal DMA transfer. In the next step S74, the bus repeater 13 makes a DMA request DREQ to the DMA controller 22 on the first bus 11, and in step S75 the device 23 makes the DMA controller 22 DMA request (DREQ). In the next step S76, the DMA controller 22 requests the CPU 21 the right to use the bus 11 in response to receiving respective DMA requests from the device 23 and the bus repeater 13 (BREQ). To receive the bus use right, and perform DMA transfer from the bus repeater 13 to the device 23.

In addition, since the memory capacity of the FIFO or the like of the bus repeater 13 is finite, when transferring data having a size larger than that, the divided transfer is set to the DMA controllers 22 and 27, and the steps S61 to S64 above, or What is necessary is just to repeat step S71 to S76. One transmission unit (block) at the time of divided transmission is determined by the memory capacity of the bus repeater 13.

Therefore, DMA transfer between the two buses 11 and 12 can be performed through the buffer memory of the bus repeater 13 without causing unnecessary waiting time. In addition, by enabling the operation of a plurality of DMA channels simultaneously, processing of the CPU can be simplified, and easy programming and low overhead can be realized. In addition, the buffers of the repeaters between the buses can be utilized efficiently. In addition, multi-threaded programs can be easily recorded.

By the way, for example, when the CPU 21 accesses the bus 12, the bus repeater 13 outputs a request BREQ of the usage rights of the bus 12 to the CPU 26, and the response BACK ) To access the DMA controller 27, the device 28, the memory 29, and the like on the bus 12.

At this time, when the FIFO 33 of FIG. 3 inhibits the output of the DMA request DREQ to the respective DMA controllers 22 and 27 by the mask flags 35 and 36, the respective buses 11 and 12 Although I / O access is enabled at, the I / O access must be performed equally without contradiction with the processing of DMA. Therefore, it is not accessible arbitrarily, but is permitted under the same conditions as DMA access. An example of the conditions for this I / O access is shown in Table 1 below.

TABLE 1

"*" In the column of the "signal and flag state" of this Table 1 shows the state of Don't care.

Here, the following cases are considered as conditions for diagnosing the DMA function.

Condition # 1: Both the bus 11 and the bus 12 transfer data using the DMA controllers 22 and 27.

Condition # 2: Only the bus 11 side receives the data from the CPU 21 by I / O access.

Condition # 3: Only the bus 12 side receives the data from the CPU 26 by I / O access.

Condition # 4: The CPUs 21 and 26 receive data by I / O access on both the bus 11 and bus 12 sides.

Condition # 5: The device on the bus 12 side does not exist or the device on the bus 12 side is not used, the bus 11 side is DMA by the DMA controller 22, and the bus 12 side is a CPU. 21 performs data transfer with I / O access.

Condition # 6: There is no device on the bus 12 side, or the bus 21 and the bus 12 side both use the CPU 21 for I / O access without using the device on the bus 12 side. Data transfer.

In addition, it is assumed that the actual debug order is to increase the DMA function in the reverse order under condition # 6.

An incomplete or problematic functional unit can be specified by investigating in which condition a problem occurs by performing data transmission in the following order in the conditions of each of the above conditions # 1 to # 6.

Condition # 1

Mask flag (35): off, mask flag (36): off

Transmission direction: *

CPU 21: Instruction of transfer to DMAC 22

CPU 26: Instructs the DMAC 27 to transfer.

Condition # 2

Mask flag (35): on, mask flag (36): off

Transmission direction: bus (11) → bus (12)

CPU 26: Instruction of transfer to DMAC 27

CPU 21: waits for the DREQ bit 37 to be written to bus repeater 13

Transmission direction: bus (12) → bus (11)

CPU 26: Instruction of transfer to DMAC 27

CPU 21: Read data from bus repeater 13 by waiting for the DREQ bit 37 to be on.

Condition # 3

Mask flag (35): off, mask flag (36): on

Transmission direction: bus (11) → bus (12)

CPU 21: Instruction of transfer to DMAC 22

CPU 26 reads data from bus repeater 13 by waiting for the DREQ bit 38 to be on

Transmission direction: bus (12) → bus (11)

CPU 21: Instruction of transfer to DMAC 22

CPU 26: Waits for the DREQ bit 38 to turn on and write data to bus repeater 13.

Condition # 4

Mask flag (35): on, mask flag (36): on

Transmission direction: bus (11) → bus (12)

CPU 21: waits for the DREQ bit 37 to be written to bus repeater 13

CPU 26 reads data from bus repeater 13 by waiting for the DREQ bit 38 to be on

Transmission direction: bus (12) → bus (11)

CPU 26: Waits for on of DREQ bit 38 to write data to bus repeater 13

CPU 21: Read data from bus repeater 13 by waiting for the DREQ bit 37 to be on.

Condition # 5

Mask flag (35): off, mask flag (36): on

Transmission direction: bus (11) → bus (12)

CPU 21: Instruction of transfer to DMAC 22

      : Read data from bus repeater 13 by waiting for the DREQ bit 38 to be on

Transmission direction: bus (12) → bus (11)

CPU 21: Instruction of transfer to DMAC 22

       : Wait for ON of DREQ bit 38 to write data to bus repeater 13.

Condition # 6

Mask flag (35): on, mask flag (36): on

Transmission direction: bus (11) → bus (12)

CPU 21: waits for the DREQ bit 37 to be written to bus repeater 13

      : Read data from bus repeater 13 by waiting for the DREQ bit 38 to be on

Transmission direction: bus (12) → bus (11)

CPU 21: Waits for on of DREQ bit 38 to write data to bus repeater 13

      : Wait for on of DREQ bit 37 to read data from bus repeater 13.

It is to check which of these six types of conditions causes an abnormality to diagnose a fault part or a problem. In addition, the data transmitted on the bus 12 can be confirmed by the test program of the CPU 21 as the CPU 21 directly accesses the bus 12.

Therefore, according to this embodiment of the present invention, it is possible to easily debug the DMA transfer function between the different buses 11 and 12, and to specify a problem place. In addition, the function can be confirmed only by the CPU 21 on the bus 11 serving as the main body, and debugging other than the DMA function can be performed by directly accessing the other bus 12.

In summary, according to the embodiment of the present invention, a bus relay means having a buffer memory is provided between the first bus and the second bus, and the first direct memory access (DMA) control means is provided on the first bus. The second direct memory access control means is connected to the second bus, respectively, and the memory or device connected to the first bus by these first and second direct memory access control means and the memory or device connected to the second bus. Direct memory access transfer to and from the buffer memory and direct memory access request from the bus relay means to the first or second direct memory access control means are performed by the data processing means (CPU). Masked by and directly buffer the buffer memory in the bus relay means by the data processing means. By accessing, this buffer memory allows direct memory access transfers between individual memories or devices on different buses. At this time, the data processing means (CPU) on each bus mask the direct memory access request on each bus, and the direct memory access function can be checked by directly accessing the buffer memory. The data processing means on the first bus may also mask the direct memory access request on the second bus and check the direct memory access function of the second bus by accessing the buffer memory on the second bus side.

Therefore, it is possible to easily debug the direct memory access transfer function between different buses and to specify a problem place. In addition, the function can be confirmed only by the data processing means on the main bus, and debugging other than the direct memory access function can also be performed by directly accessing the other bus.

Next, an example in which the block size of the transfer data of a system for DMA transfer through a buffer between different buses can be easily changed will be described.

In this example, the bus repeater 13 changes the block size by adding dummy data or omitting some data during data transfer.

That is, as described above with reference to FIGS. 2 to 5, when all the continuous data sequences from the transfer time point are recorded as they are at the transfer end point in the DMA transfer, one transfer unit (block) is used for the DMA controllers 22 and 27. By setting all the same as the size of the FIFO 33 in the bus repeater 13, the most efficient transmission is performed.

The bus repeater 13 has a function of performing the following processing when the amount of incoming and outgoing data input to the buffer (FIFO 33) is different.

That is, the first outputs dummy data when the output request comes back even if the input data is lost in the buffer (FIFO 33).

The second discards the remaining data when the input data remains in the buffer (FIFO 33) at the time when the DMA on the output side ends.

The structure of the data string to be transmitted can be changed by the function of the bus repeater 13 as described above. Examples of the configuration of the data string include increasing the size of the data block by adding dummy data during the DMA transfer, and reducing the size of the data block by omitting some data during the DMA transfer. .

Hereinafter, a specific example in the case where the capacity of the buffer (FIFO 33) of the bus repeater 13 is 64 bytes will be described.

For example, it is assumed that the data strings S _1A , S _1B , S _1C , S _2A ,..., As shown in FIG. 6 are developed in the memory 29 of FIG. 2. The subscripts A, B, and C of the data strings S _1A , S _1B , S _1C , S _2A ,... Represent data of different types, and only B and C types of data among these three types of data are shown in FIG. 2. It is assumed that the data is transmitted to the device 23.

At this time, it is necessary to record the data string as shown in FIG. In addition, the data string _{(S 1A, S 1B, S} 1C, S 2A, ...) the number of subscripts 1, 2, 3, ... of Indicates the number of data blocks that are one transmission unit.

In the DMA controller 27, all types (A, B, C) of the data S _1A , S _1B , S _1C , S _{2A ,.} The same DMA transfer is set as transfer of blocks. In contrast, the DMA controller 22 is set so that only two types of B and C, i.e., 24 blocks are transmitted as one block for 24 bytes. As a result, 8 bytes (data strings S _2A and S _3A ) following the data strings S _1C and S _2C of the type C are discarded, and as a result, the data string as shown in FIG. 7 is recorded in the device 23. Can be.

Next, the data string of the format as shown in FIG. 7 is output from the device 23 of FIG. 2, and this is expanded to the memory 29, for example, and as shown in FIG. Next, suppose that a data string of type D is to be inserted.

In this case, the DMA controller 27 is set to transmit three blocks of 36 bytes as one block. At this time, as a result of the DMA transfer, the 12-byte dummy data is written after the 24-byte data string of the types B and C, so that the CPU 26 of FIG. 2 stores the data of the type D in this dummy data area. You can record the heat yourself. In other words, the CPU 26 can reduce the effort of moving data on the memory 29.

In the example of FIG. 2, when the device 28 outputs a data string as shown in FIG. 8 and writes a data string of only B and C types in the device 23, the data is stored in the DMA controller 27. At the beginning of the column, 36 bytes may be set to be transmitted as three blocks by one block, and the DMA controller 27 may be set to transmit three blocks by 24 blocks as one block.

By simply adding the above-described functions to the bus relay 13 for relaying transmission in this way, a simple data configuration can be converted at the time of data string transfer, and the performance of the system can be improved.

Here, a specific example in the case where the redundant data as described above is removed or another data is inserted between the data columns will be described with reference to the drawings.

Fig. 9 shows a texture image region for texture mapping in image processing such as computer graphics, and the region T ₁ , T ₂ , T ₃ , T ₄ represented by a part of the wide texture region, for example, an oblique line in the figure. Assume to send). This texture image is developed in the memory as shown in FIG. 10, for example, and when transferring data of some areas T ₁ , T ₂ , T ₃ , and T ₄ on this memory, it is necessary to separate the extra data. .

As an example of data addition, as shown in Fig. 11, a header is added to several data columns, for example, polygon data. In other words, polygon data may have different data string sizes depending on vertex count, shading, texture, or the like, and a header (GPUIFtag) may be added to distinguish the texture data from the transmission destination. Data transmitted by the Graphical Process Unit Interface (GUIF) interface is based on a chunk of data called a primitive consisting of a header (GPUIFtag) and subsequent data. In addition, a plurality of primitives processed in a batch are referred to as GPU packets.

Fig. 12 shows an example of the configuration of the header GPUIFtag, and is composed of a register descriptor (REGS), a register descriptor number (NREG), a data format (FLG), and the like sequentially from the MSB. In this case, when adding a header (GPUIFtag) to the polygon data, it is necessary to insert other data between the data columns.

In the case where the above-described simple data configuration is required to be converted, the CPU can rearrange the data strings DMA transferred to the memory or the data strings to be DMA transferred to the memory by using the above-described embodiment of the present invention. It can reduce inefficient work such as, and the performance of the system is improved. It also allows DMA transfers between devices of different data formats. In addition, it is possible to prepare a table of the transfer time address and the transfer amount of a special specification or to refer to the table.

As is clear from the above description, according to the example described with reference to Figs. 6 to 11 of the embodiment of the present invention, bus relay means having a buffer memory is provided between the first bus and the second bus, Data transfer between the second bus is made through the buffer memory in the bus relaying means, and the bus relaying means increases the size of the transmission data block by adding dummy data at the time of data transmission or at the time of data transmission. By omitting some data, the size of the transmission data block can be reduced, so that a simple data configuration can be changed at the time of data transmission, and the performance of the system can be improved.

Further, a first direct memory access control means is connected to the first bus, data transfer control is performed between the first bus and a buffer memory in the bus relay means, and a second direct memory access control is provided to the second bus. Means for connecting and controlling data transfer between the second bus and the buffer memory in the bus relay means, and the bus relay means a dummy when there is an output request even when there is no data in the buffer memory during data transfer. A data transfer or data transfer is to be performed by having a function of outputting data and a function of discarding the remaining data when data in the buffer memory remains at the end of data transfer on the output side during data transfer. CPU, etc. rearrange data in memory May reduce the efficiency of bad operation, for example, it can also reduce the effort to see careful if prepared a table of special transfer specification, such as the sending address and the transmission rate for data transmission. It is also possible to transfer data between devices of different data formats.

Next, Fig. 13 shows an example of a system to which the embodiments of the present invention as described above are applied. In this system, a low speed such as a main bus 111 for performing high speed image processing and a CD-ROM drive or the like is shown. The sub-bus 112 to which peripheral devices of the to-be-connected are connected via a bus repeater 113 having a buffer memory such as a FIFO.

That is, in Fig. 13, the main CPU 121, the DMA controller 122, the graphics engine 123 for the high speed image processing, and the main memory 124 are connected to the high speed main bus 111, and the relatively low speed is achieved. The sub bus 122 is connected to a sub CPU 126, a DMA controller 127, a data recording medium 128 such as a CD-ROM, and a sub memory 129. These main buses 111 and sub-buses 112 are connected via a bus repeater 113 having a buffer memory such as FIFO as described above, and the bus repeater 113 is connected to a plurality of DMA controllers 122 and 127. A plurality of types of DMA requests corresponding to DMA channels, for example, three types of DMA requests can be output. Since the specific structure and operation of this bus repeater 113 may be the same as the bus repeater 13 of the embodiment demonstrated with FIG. 2 thru | or FIG. 5, description is abbreviate | omitted.

In this way, when DMA transfer is performed between the high speed bus and the low speed bus, data transfer can be performed without incurring unnecessary waiting time on the high speed bus, and the CPU processing can be simplified. It can also facilitate the debugging of DMA transfers between different buses.

In addition, the present invention is not limited to the above embodiment only. For example, in the above embodiment, an example in which bidirectional DMA transfers are performed between the first bus and the second bus has been described. The present invention can also be applied to the case where only the DMA transfers or the DMA transfers from the second bus to the first bus are performed. It goes without saying that the number of DMA channels, the circuits connected to the respective buses, and the like are not limited to the embodiments.

Claims (9)

Connect different first buses and second buses through bus relay means having a buffer memory, Data transfer control between the first bus and a buffer memory in the bus relay means by a first direct memory access control means connected to the first bus, Data transfer control between the second bus and a buffer memory in the bus relay means by second direct memory access control means connected to the second bus, Mask a direct memory access request from the bus relay means to the first or second direct memory access control means by a data processing means, and directly access the buffer memory in the bus relay means by the data processing means. A data transmission method, characterized in that. The method of claim 1, The data processing means may include first data processing means on the first bus, and second data processing means on the second bus, respectively. The first data processing means masks a direct memory access request on the first bus, The second data processing means masks a direct memory access request on the second bus, And the first and second data processing means directly access the buffer memory in the bus repeater under the same transfer conditions as the first and second direct memory access control means on each bus. The method of claim 1, The data processing means is provided with first data processing means on the first bus, The first data processing means masks a direct memory access request on the second bus, And the first data processing means directly accesses the buffer memory in the bus repeater on the second bus side. With the first bus and the second bus, Bus relay means having buffer memories connected to these first buses and second buses, respectively; First direct memory access control means connected to said first bus, Having first data processing means connected to said first bus, The bus relay means has a function of outputting a direct memory access request to the first direct memory access control means, and a function of masking the direct memory access request by the first data processing means, And the first data processing means masks a direct memory access request of the bus relaying means, and directly accesses the buffer memory in the bus relaying means. The method of claim 4, wherein A second direct memory access control means and a second data processing means are connected to the second bus; The first and second direct memory access control means performs data transfer between the first and second buses by reading and writing data to the buffer memory in the bus relay means, The bus relay means has a function of outputting a direct memory access request to the second direct memory access control means, and a function of masking the direct memory access request by the second data processing means, And the second data processing means masks a direct memory access request of the bus relaying means, and directly accesses the buffer memory in the bus relaying means. The method of claim 5, wherein One of the first and second data processing means masks a direct memory access request on the other bus in the bus repeater, and accesses the buffer memory in the bus repeater on the other bus. A data transmission device. Connect different first buses and second buses through bus relay means having a buffer memory, Data transfer between the first bus and the second bus is performed through a buffer memory in the bus relaying means, The bus relay means reduces the size of the transmission data block by omitting some data during data transmission. Data transfer control between the first bus and a buffer memory in the bus relay means by first direct memory access control means connected to the first bus, Data transfer control between the second bus and a buffer memory in the bus relay means by second direct memory access control means connected to the second bus, And the bus relay means discards the remaining data when data in the buffer memory remains at the time when data transmission on the output side ends at the time of data transmission. With the first bus and the second bus, Bus relay means having buffer memories connected to these first buses and second buses, respectively; First direct memory access control means connected to said first bus, Having second direct memory access control means connected to said second bus, The bus relay means outputs dummy data when there is an output request even if data in the buffer memory is lost at the time of data transfer, And the bus relay means discards the remaining data when data in the buffer memory remains at the time when the data transfer on the output side ends at the time of data transfer. With the first bus and the second bus, Bus relay means having buffer memories connected to these first buses and second buses, respectively; First direct memory access control means connected to said first bus, Having second direct memory access control means connected to said second bus, And the bus relay means discards the remaining data when data in the buffer memory remains at the time when data transmission on the output side ends at the time of data transmission.