JPH05128049A - Input/output controller - Google Patents

Abstract

PURPOSE:To execute the processing of dummy data for handling a fixed length packet at a high speed. CONSTITUTION:A counter 430 for counting up the data words of a sending packet and a selector 4063 for selecting data to be transferred and dummy data are included in a transfer means 140 and sending data are sent under control from a DMA control circuit 407. Simultaneously the contents of the counter 430 are counted up by an output from a selector 434, and when the value of the counter 430 is less than the number of data words of the packet at the time of terminating DMA transfer, the dummy data are sent to an I/O device interface circuit 405 as sending data through the selector 4063 and the sending of the dummy data is terminated when the value of the counter 430 exceeds the number of data words of the packet.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control device for an information processing device.

[0002]

2. Description of the Related Art FIG. 1 is a conceptual diagram showing the positioning of an input / output control device of an information processing apparatus. In the figure, 1 is a host processor, 2 is a host memory, 3 is a host processor bus, 4 is an input / output control device, Reference numeral 5 is an input / output device, and 6 is an input / output device cable connecting the input / output control device 4 and the input / output device 5. FIG. 7 is a block diagram of a conventional input / output control device 4. In the figure, 401 is a host interface circuit that interfaces the host processor bus 3 and the input / output control device 4, 402 is a local bus for data transfer, and 403 is A local RAM, 405 is an input / output device interface circuit for interfacing with the input / output device cable 6, and 406 is an input / output device interface circuit 4.
FIFO for storing received data from 05, 407 is 3
→ 401 → 402 → 405 → 6 or 6 → 405 → 40
DMA control circuit for controlling DMA data transfer of 6 → 402 → 401 → 3, 410 is a microprocessor, 411
Is a microprocessor bus, 412 is a ROM, 413 is a RAM, and 414 is a bus adapter circuit that interfaces the local bus 402 and the microprocessor bus 411. The DMA control circuit 407 uses a large-scale PLD, and its configuration information is stored in the ROM 412. The microprocessor 410 reads the information from the ROM 412 in the initialization sequence, and the DMA control circuit 4
By writing to 07, it functions as the DMA control circuit. The data handled by the input / output device 5 is fixed length data.

Next, the operation will be described separately for the case of transmitting the data of FIG. 8 and the case of receiving the data of FIG. (1) When data is sent from the host memory 2 in FIG. 1 to the input / output device 5 (see FIG. 8): The host processor 1 sends a command (data write command, transfer source, transfer destination designation) and data to the host memory 2. And the host processor 1 activates the input / output control device 4. The activation request is transmitted to the microprocessor 410 via the host interface 401, and at the same time, the host interface 401
Commands in the host memory 2 to the local memory 403
Transfer to. The microprocessor 410 analyzes the command in the local memory 403 and finds that there is a request to send the data in the host memory 2 to the input / output device 5. Although the data in the host memory 2 has an arbitrary length, the data sent to the input / output device 5 is preceded by a heading portion containing the identification information of the data, and the data length is fixed, so the host memory If the data in 2 is less than the fixed length, dummy data is added after the data and sent (see FIG. 6). Therefore, the microprocessor 410 will perform the following operations. i) generate a heading portion to generate a bus adapter circuit 414,
Local bus 402, input / output device interface circuit 4
It is sent to the input / output device 5 via 05. ii) A command is sent to the DMA control circuit 407 via the processor bus 411, and DMA transfer of data (3 → 401 → 4) is performed.
02 → 405 → 6 → 5) is started. DMA control circuit 4
A signal 07 is sent to the input / output interface circuit 405 every time one word is transferred with the signal being transferred set to "1". iii) When the transfer data is less than the data length of the packet, the microprocessor 410 writes dummy data to the input / output interface circuit 405 via the microprocessor bus 411 and the bus adapter circuit 414 to complete the packet. This completes the data transfer from the host processor 1 to the input / output device 5.

(2) When receiving data from the input / output device 5 to the host memory 2 (see FIG. 9): The host processor 1 sends a command (data read command, transfer source, transfer destination, number of words) to the host memory 2. Then, the host processor 1 activates the input / output control device 4. The activation request is transmitted to the microprocessor 410 via the host interface circuit 401, and at the same time, the host interface circuit 401 transmits the host command to the local memory 40.
Transfer to 3. The microprocessor 410 analyzes the command in the local memory 403 and finds that there is a request to read data from the input / output device 5. The microprocessor 410 sends a read request to the input / output device 5 via the bus adapter circuit 414 and the input / output interface circuit 405. The input / output device 5 sends a packet of heading + fixed length data to the input / output control device 4, and the data is received by the FIFO 406 via the input / output interface circuit 405. 1 from the input / output interface circuit 405
A write signal is output as a pulse each time a word is received, and is input as a write signal to the FIFO 406. After that, the microprocessor 410 performs the following operations. i) The heading portion is read from the FIFO 406 and analyzed, and it is determined that this is a packet containing desired data. ii) A command is sent to the DMA control circuit 407 via the processor bus 411, and the DMA of the specified number of words of data is performed.
Transfer (406 → 402 → 401 → 3 → 2) is activated. iii) If the received packet contains dummy data, the dummy data is read and removed from the FIFO 406. F
A read signal is sent as a pulse from the DMA control circuit 407 to the FIFO 406 every time one word is read from the IFO. This completes the data transfer from the input / output device 5 to the host processor 1.

[0005]

Since the conventional input / output control device is configured as described above, it is necessary to write dummy data when writing data and read dummy data when reading data. This imposes a burden on the microprocessor and reduces the processing performance. In addition, there is a problem that the next packet that has entered the reception FIFO cannot be read during the DMA transfer at the time of data read, and the current DMA transfer must be completed.

The present invention has been made in order to solve the above-mentioned problems, and performs the read / write of dummy data at high speed with less intervention of the microprocessor and during the DMA transfer of data read. Receive FI
An object is to obtain an input / output control device capable of reading and analyzing the header part of the next packet that has entered the FO.

[0007]

An input / output control device according to a first aspect of the present invention enables writing of dummy data with less intervention of a microprocessor, and has the following elements. .. (A) Input means for inputting data of arbitrary length, (b) Output means for outputting data of fixed length, (c) Counter for counting data length of data, (d) Value of counter is input by input means Transfer means for transmitting the data input by the input means to the output means until the data has an arbitrary length, and transmitting dummy data to the output means until the value of the counter reaches the fixed length used by the output means.

The input / output control device according to the second aspect of the present invention allows dummy data to be ignored by reducing the intervention of the microprocessor, and has the following elements. (A) input means for inputting fixed length data including effective data length, (b) output means for outputting arbitrary length data, (c) buffer for storing data from the input means,
(D) A counter that counts the data length of data,
(E) Transfer means for sending data from the buffer to the output means until the value of the counter reaches the effective data length of the data input by the input means.

The input / output control device according to the third invention is adapted to analyze the following data, and has the following elements. (A) input means for inputting data having a heading portion having a predetermined length and a data portion, (b) a heading buffer for storing the heading portion, (c) a data buffer for storing the data portion, ( d) A counter that counts the data length of the data,
(E) Transfer means for storing the data input by the input means in the heading buffer until the value of the counter reaches the length of the heading information, and for storing the data in the data buffer after exceeding the length.

[0010]

In the input / output control device according to the first aspect of the present invention, since the transfer means writes the dummy data by using the counter, the load on the microprocessor can be reduced and the dummy data can be generated at high speed.

In the input / output control device according to the second aspect of the present invention, since the transfer means transfers the data from the data buffer of the reception data using the counter, the burden on the microprocessor is reduced and the dummy data is removed at high speed. Is possible.

The input / output control device according to the third aspect of the present invention makes it possible to prefetch the heading portion of the packet next by dividing the received data buffer into one for heading and one for data.

[0013]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 2, 401 is a host interface circuit, 402 is a local bus, 403 is a local RAM,
Reference numeral 405 is an external interface circuit, 4061 is a reception data FIFO, 4062a is a preceding data FIFO, 4062b is a subsequent data FIFO,
063 is a selector for selecting dummy data, 407 is DM
A DMA control circuit for controlling A data transfer, 410 is a microprocessor, 411 is a microprocessor bus, 4
Reference numeral 12 is a ROM, 413 is a RAM, and 414 is a bus adapter circuit. FIG. 3 shows an embodiment of the first invention, and is a block diagram showing control at the time of data transmission. 430 is a counter, 431 is a comparator, and 432 is AN.
The D gate 433 is a NOT element, and 434 and 435 are selectors. Further, 100 is an input unit, 200 is an output unit, 300 is a counter, and 400 is a transfer unit.

FIG. 4 is a diagram showing an embodiment of the second invention, and FIG. 5 is a diagram showing an embodiment of the third invention. Both FIG. 4 and FIG. And 440 is a counter, 441 is a comparator, 442,
443 is an AND gate, 444 is a NOT element, 450 is a counter, 451 is a comparator, and 452 is an AND gate. Further, in FIG. 4, 210 is an input means, 220 is an output means, 230 is a buffer, 240 is a counter, 25
0 is a transfer means. Further, in FIG. 5, 310 is an input unit, 320 is an output unit, 330 is a heading buffer, 340 is a data buffer, 350 is a counter,
Reference numeral 360 is a transfer means.

The data to be transferred can take an arbitrary number of words on the host memory 2, but the data handled by the input / output device 5 has a packet format as shown in FIG. Stores identification information of the data, and the fixed-length data portion stores the data to be transferred. When this data length is smaller than the length of the data part, dummy data is stored after it.

Next, the operation will be described separately for transmitting and receiving data. (1) When data is sent (written) from the host memory 2 to the input / output device 5 (see FIG. 2): host processor 1
Command to the host memory 2 (data write command,
The transfer source, transfer destination, number of words) and transfer target data are stored, and the host processor 1 activates the input / output control device 4. The activation request is transmitted to the microprocessor 410 via the host interface circuit 401, and at the same time, the host interface circuit 401 transfers the command in the host memory 2 to the local memory 403. The microprocessor 410 analyzes the command in the local memory 403 and finds that there is a request to send (write) the data in the host memory 2 to the input / output device 5. i) The microprocessor 410 first generates a heading unit, and then the bus adapter circuit 414 and the local bus 40.
2, sent to the input / output device 5 via the selector 4063, the input / output device interface circuit 405, and the cable 6. ii) The microprocessor 410 uses the DMA control circuit 4
07 via the processor bus 411, and DMA transfer of data (3 → 401 → 402 → 4063 → 405
→ 6 → 5) is started. Host interface circuit 40
Data to be transferred is sent word by word from 1 and sent as send data to the input / output device interface circuit 405 via the local bus 402 and the selector 4063. On the other hand, the DMA control circuit 407 outputs the signal “in transfer”
1 ”, and then enters the transfer signal of the input / output device interface circuit 405 via the selector 435. The write signal outputs“ 1 ”as a pulse for each word, and the input / output device via the selector 434. The write signal of the interface circuit 405 is input, and the transmission data is transmitted.
At the same time, the output of the selector 434 causes the counter 430 to count up. When the DMA transfer of data is completed, D
When the signal under transfer from the MA control circuit 407 becomes "0", but when the value of the counter 430 is less than or equal to the number of data words of the packet, the pulse supplied from the clock passes through the selector 434 and the input / output device interface circuit. 405
Of the write signal, and the dummy data is input to the selector 4063.
“1” sent as output data to the input / output device interface circuit 405 via the selector 435.
Signal is transmitted to the input / output device interface circuit 405 as a transferring signal. When the value of the counter 430 exceeds the number of data words of the packet, the write signal and the transfer-in-progress signal of the input / output device interface circuit 405 become "0", and the transmission of the dummy data ends.

(2) When receiving (reading) data from the input / output device 5 to the host memory 2 (see FIGS. 4 and 5):
The host processor 1 stores a command (data read command, transfer source, transfer destination, number of words) in the host memory 2, and the host processor 1 activates the input / output control device 4. The activation request is transmitted to the microprocessor 410 via the host interface circuit 401, and at the same time, the host interface circuit 401 transfers the host command to the local memory 403. Microprocessor 4
10 analyzes the command in the local memory 403 and finds that there is a request to read data from the input / output device 5. The microprocessor 410 is the bus adapter circuit 41.
4. Send a read request to the input / output device 5 via the input / output device interface circuit 405. The input / output device 5 sends the packet to the input / output control device 4, the write signal of the input / output device interface circuit 405 outputs “1” as a pulse for each word, and the reception heading FIFO 4061 is output via the AND gate 443. Is input to the write signal of. This is the reception heading FIFO 4061
The data from the input / output interface circuit 405 is written for each pulse, and the counter 440 simultaneously counts up the value for each pulse. When the counter 440 exceeds the number of heading words (compared by the comparator 441), the write signal of the input / output device interface circuit 405 passes through the AND gate 442 and the FI for data in the previous stage.
The data of the input / output device interface circuit 405 input to the write signal of the FO 4062a is the data FIFO 40.
62a is written. In this way, the received packet is stored in separate FIFOs for the heading part and the data part. Here, the microprocessor 410 is connected to the heading FIFO 4061 via the microprocessor 411.
To lead the heading information. At this time, the microprocessor 410 sends a pulse of "1" to the heading FIFO read signal from the microprocessor bus 411 every time one word is read. The microprocessor 410 analyzes the heading information and outputs the data FIFO.
When it knows that the data is stored in 4062a, it issues a command to the DMA control circuit 407 via the microprocessor bus 411 to reset the counter 450. The data FIFO 4 whose clock is the previous stage via the AND gate 452
062a read signal and subsequent data FIFO 40
It is supplied to the write signal of 62b and data is transferred from 4062a to 4062b, and at the same time, the output of the AND gate 452 causes the counter 450 to count up. This transfer continues until the value of the counter 450 is less than or equal to the number of data words in the packet, and therefore continues until one packet of data is transferred to the subsequent data FIFO 4062b. When the transfer is started, the microprocessor 410 issues a command to the DMA control circuit 407 via the microprocessor bus 411 to transfer the data of the subsequent data FIFO 4062b by DMA. A read pulse for each word is sent from the DMA control circuit 407 to the subsequent data FIFO 4062b. This transfer is continued for the number of words to be transferred to the host memory 2. When the number of words to be transferred to the host memory 2 is smaller than the number of data words in the packet at the end of this transfer, the data FIFO 406 in the subsequent stage
Data remains in 2b. By clearing this with a reset signal from the DMA control circuit 407, there is no need for dummy reading of this residual data. Also, 2 consecutive
When one packet is received, the heading portion of the second packet can be read from the heading FIFO 4061 while data transfer of the first packet is being performed, so that analysis of that packet can be started. With the above, the data transfer can be completed.

As described above, in this embodiment, the host processor and the host memory device, the host bus, the input / output control device,
In an input / output control device in an information processing device including an input / output device, a host bust interface circuit, an input / output device interface circuit, a microprocessor for interpreting a command from a host, and a storage / execution of the microprogram A ROM / RAM, a DMA control circuit for performing DMA transfer of data between the input / output device and the host memory, and a FIFO for storing received data from the input / output device, and the input / output device connected thereto Data is input and output in the form of a packet consisting of a heading part that contains data identification information and fixed length data, and the host processor stores a command to the host memory device to instruct the type, direction, and size of data transfer. The I / O controller is activated by starting the data transfer. The microprocessor of the device interprets the data transfer request, activates the DMA control circuit, and performs the pre-processing / post-processing of the transfer, the input / output control device has a selector for selecting data and dummy data, and the number of words to be sent. Has a counter that counts the number of bytes of data transfer from the host memory,
After completion of the DMA transfer from the host memory, an input / output control device capable of sending dummy data selected by the selector up to the fixed length data word number of the packet by the clock for continuously counting up the counter. explained. That is, it has a counter that counts the number of words to be sent, counts the number of bytes of data transfer from the host memory, and after the DMA transfer from the host memory is completed, while continuing to count up the counter, the data word of the packet The dummy data is written up to the number to the external interface circuit.

Further, in the above-mentioned input / output control device, there are two stages of FIFO for data of the received packet, and the FIFO of the preceding stage is provided.
The counter has a counter for writing the data part of the packet from the input / output device interface circuit to O, and for transferring the data of one packet of the data stored in the FIFO of the preceding stage to the FIFO of the latter stage. Data of the number of data words from the first stage FIFO to the second stage FI
Transfer to FO, D from the subsequent FIFO to host memory
An input / output control device having a function of performing MA transfer and, if data (dummy data) remains in the subsequent FIFO after the completion of DMA transfer, resets the subsequent FIFO (in an empty state) to remove the dummy data in the packet Explained. That is, F for data of the received packet
It has two stages of IFOs and a counter for counting the number of transfer words. Until this counter reaches the number of words of the packet, a read pulse is given to the first stage FIFO and a write pulse is given to the second stage FIFO so that the first stage FIFO can be supplied. Data from the external interface circuit is written, and one of the data stored in the FIFO in the previous stage is written in the FIFO in the subsequent stage.
The data for the packet is transferred, and the DMA transfer to the host memory is performed for the data in the subsequent FIFO,
After the DMA transfer of the specified number of words is completed, the second stage FIFO
By resetting O (empty state), the dummy data in the packet can be removed.

Further, the input / output control device has two FIFOs for the received data, one for the heading and one for the data, and has a counter for counting the number of words of the received data, and the value of the counter is the number of words for the heading. The input / output control device has the function of storing the received data in the heading FIFO in the following cases and storing the received data in the data FIFO when the counter value exceeds the number of words in the heading. That is, a FIFO for received data
And a counter for counting the number of words of received data. When the value of the counter is less than or equal to the number of words in the heading, F for heading is used.
Applying a write pulse to the IFO and thus FI for heading
When the received data is written in the FO and the value of the counter is larger than the number of heading words, a write pulse is given to the data FIFO, so that the received data is written in the data FIFO.

[0021]

As described above, according to the first aspect of the present invention, the counter is provided so that the writing of dummy data can be executed without the burden on the microprocessor, so that high-speed transmission performance can be obtained.

Further, according to the second invention, unnecessary dummy data can be removed by resetting the buffer by the counter, so that there is an effect that a high reception performance can be obtained.

According to the third aspect of the invention, since the buffer for the received data is divided into the buffer for the heading portion and the buffer for the data portion, the heading portion of the next packet can be read before the end of the current data transfer, which is high. There is an effect that performance can be obtained.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing the positioning of an input / output control device.

FIG. 2 is a block diagram of an input / output control device according to an embodiment of the present invention.

FIG. 3 is a block diagram showing control at the time of data transmission in the embodiment of the first invention.

FIG. 4 is a block diagram showing control at the time of receiving data in an embodiment of the second invention.

FIG. 5 is a block diagram showing control at the time of receiving data in an embodiment of the third invention.

FIG. 6 is a conceptual diagram showing a data format of a packet.

FIG. 7 is a block diagram of a conventional input / output control device.

FIG. 8 is a block diagram showing control during data transmission in a conventional example.

FIG. 9 is a block diagram showing control in receiving data in a conventional example.

[Explanation of symbols]

 401 Host interface circuit 402 Local bus 403 Local RAM 405 External interface circuit 4061 FIFO for heading 4062a FIFO for front stage data 4062b FIFO for rear stage data 4063 Selector for dummy data 407 DMA control circuit 410 Microprocessor 411 Microprocessor bus 412 ROM 413 RAM 414 bus adapter circuit 430 counter 431 comparator 432 AND gate 433 NOT element 434, 435 selector 440 counter 441 comparator 442, 443 AND gate 444 NOT element 450 counter 451 comparator 452 AND gate

Claims (3)

[Claims] 1. An input / output control device having the following elements: (a) input means for inputting data of arbitrary length; (b) output means for outputting data of fixed length; (c) counting data length of data. Counter, (d) data input by the input means is sent to the output means until the value of the counter reaches an arbitrary length of the data input by the input means, and dummy data is output until the value of the counter reaches a fixed length used by the output means. Transfer means for sending to the output means. 2. An input / output control device having the following elements: (a) input means for inputting fixed length data including effective data length, (b) output means for outputting arbitrary length data, (c) input means A buffer for storing the data from the buffer, (d) a counter for counting the data length of the data, and (e) a transfer for sending the data from the buffer to the output means until the value of the counter reaches the effective data length of the data input by the input means. means. 3. An input / output control device having the following elements: (a) input means for inputting data having a heading portion having a predetermined length and a data portion, (b) a heading buffer storing the heading portion, (C) A data buffer for storing the data section, (d) a counter for counting the data length of the data, (e) data for heading input by the input means until the counter value reaches the length of the heading information. A transfer means for storing the data in the buffer and storing the data in the data buffer after the length is exceeded.